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EE534
VLSI Design System
summer 2004
Lecture 14:Chapter 10
Semiconductors memories
EE 534 summer 2004 University of South Alabama
Chapter 10: SEMICONDUCTOR MEMORIES
Memory classification (more history than
technical)
Memory architecture and basic operations
The memory core (data storage units)
Peripheral circuits (decorder, sens-amp, etc.)
Reliability concerns (processing and
operational)
General design considerations and future
trends
EE 534 summer 2004 University of South Alabama
Feynman’s Prediction in 1959
To store Encyclopedia Britannica on the head of a
pin (10-2 inch square), we need a dot every 8nm
To store all books in history (around 25 million
copies, which needs 1015 bits, or peta-bit) with
8nm in 2D, we need just a few square yards.
If we code the text part and do 3D storage of (55
5 atoms), all books in history will be smaller than
the sand dust (now you are talking about smart
dust).
There is NO physical principles that prohibit this.
EE 534 summer 2004 University of South Alabama
Far Away from the End...
“What I have demonstrated is that there is room---that you
can decrease the size of things in a practical way. I now want
to show that there is plenty of room. I will not now discuss
how we are going to do it, but only what is possible in
principle---in other words, what is possible according to the
laws of physics. I am not inventing anti-gravity, which is
possible someday only if the laws are not what we think. I am
telling you what could be done if the laws are what we think;
we are not doing it simply because we haven't yet gotten
around to it.”
(Richard P. Feynman, There is plenty of room at the
bottom, Dec. 1959)
EE 534 summer 2004 University of South Alabama
A Word on Terminology for Semiconductor Memories
Different unit to consider in design
circuit designers: bits
chip designers: bytes (8 or 9 bits), gigabyte (109 bytes),
terabyte (1012), peta bytes (1015), exa bytes (1018), googol
bytes (10100).
system designers: words (32 bits now, but many 64-bit
system appearing)
ROM (read-only memory), RAM (random-access memory),
EEPROM (electrically erasable programmable read-only
memory), etc. can take better names
SDRAM (synchronous dynamic RAM), etc.
off-chip access, embedded SRAM, etc.
EE 534 summer 2004 University of South Alabama
Semiconductor Memory Classification
RWM NVRWM ROM
Random Non-Random EPROM Mask-Programmed
Access Access
E2PROM Programmable (PROM)
SRAM FIFO FLASH
DRAM LIFO
Shift Register FIFO: First-in-first-out
LIFO: Last-in-first-out (stack)
CAM CAM: Content addressable memory
EE 534 summer 2004 University of South Alabama
Growth in DRAM Chip Capacity
1000000
256,000
100000
64,000
Kbit capacity
16,000
10000
4,000
1000 1,000
256
100
64
10
1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000
Year of introduction
EE 534 summer 2004 University of South Alabama
Memory Architecture: Decoders
pitch matched
line too long
EE 534 summer 2004 University of South Alabama
2D Memory Architecture
2k-j bit line
word line
Aj
Aj+1
storage
Ak-1 (RAM) cell
m2j
A0
A1 Column Decoder selects appropriate
Aj-1 word from memory row
Sense Amplifiers amplifies bit line swing
Read/Write Circuits
Input/Output (m bits)
EE 534 summer 2004 University of South Alabama
3D Memory Architecture
Input/Output (m bits)
Advantages:
1. Shorter word and/or bit lines
2. Block addr activates only 1 block saving power
EE 534 summer 2004 University of South Alabama
Hierarchical Memory Architecture
Row
Address
Column
Address
Block
Address
Global Data Bus
Control Block Selector Global
Circuitry Amplifier/Driver
I/O
Advantages:
shorter wires within blocks
block address activates only 1 block: power management
EE 534 summer 2004 University of South Alabama
Read-Write Memories (RAM)
Static (SRAM)
Data stored as long as supply is applied
Large (6 transistors per cell)
Fast
Differential signal (more reliable)
Dynamic (DRAM)
Periodic refresh required
Small (1-3 transistors per cell) but slower
Single ended (unless using dummy cell to generate
differential signals)
EE 534 summer 2004 University of South Alabama
Three Transistors DRAM cell
●Binary information is stored
in the from of charge in the
capacitor C1
●M2 is storage transistor
●Pass transistors act as access
switches for data read and
write operation
●All data read and data write
operation are performed when
PC is low.
Reads are non-destructive
No constraints on device ratios
Value stored at X when writing a “1”=VWWL-VTn
EE 534 summer 2004 University of South Alabama
Write ‘1’ and read ‘1’ operation
Write operation
●During write
operation signal WS is
high As a result M1 is
turned on and allow
charge sharing
between C2 and C1.,
which turned on M2.
●During read
operation: M1 is off
RS is high, M3 is on Read
and consequently C3 operation
discharge through M2
and M3.
Low level on Dout (C3) is the
of stored of South
finger print2004 University“1” Alabama
EE 534 summer
Write ‘0’ and read ‘0’ operation
For write “0” operation:
WS is high, M1 turn on
C1 and C2 discharge through M1
M2 turned off because of low
voltage level of C1.
During read “0” operation
RS is high
M3 turn on but M2 is off
C3 remains high
High level on Dout is the finger
print of stored “0”
bit.
EE 534 summer 2004 University of South Alabama
3-T DRAM cell during operation
EE 534 summer 2004 University of South Alabama
1-Transistor DRAM Cell
BL
WL Write "1" Read "1"
WL
M1 X
CS GND V -VT
DD
small
perturbation
VDD
BL
VDD/2 VDD/2 VDD /2
CBL sensing
Write: C S is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance,
The direction of which determines the value of data stored.
CS
DV = BL – V PRE = VDD/2 ---------------------
C S + CBL
---
Voltage swing is small; typically around 250 mV.
EE 534 summer 2004 University of South Alabama
DRAM Cell Observations
DRAM cells are single ended in contrast with SRAM cells
Read-out of 1T DRAM is destructive (3T is not), and refresh
is necessary after read.
1T DRAM needs an explicit capacitance (3T needs not)
1T DRAM requires a sense amp for each bit line, due to
charge redistribution read-out
When writing 1’s into DRAM cells, a Vth is lost. This charge
loss can be circumvented by bootstrapping the word line (not
the bit line) to a higher value than VDD.
EE 534 summer 2004 University of South Alabama
Read-Write Memories (RAM)
Static (SRAM)
Data stored as long as supply is applied
Large (6 transistors per cell)
Fast
Differential signal (more reliable)
Dynamic (DRAM)
Periodic refresh required
Small (1-3 transistors per cell) but slower
Single ended (unless using dummy cell to generate
differential signals)
EE 534 summer 2004 University of South Alabama
6-transistor SRAM Cell
WL
M2 M4
Q M6
M5 Q
M1 M3
!BL BL
Note that it is identical to the register cell from static sequential circuit - cross-coupled inverters
Consumes power only when switching - no standby power (other than leakage) is consumed
The major job of the pullups is to replenish loss due to leakage
Sizing of the transistors is critical!
EE 534 summer 2004 University of South Alabama
SRAM Cell Analysis (Read)
WL=1
M4
M6
M5 Q=0 Q=1
M1
Cbit Cbit
BL=1 BL=1
Read-disturb (read-upset): must carefully limit the allowed voltage
rise on Q to a value that prevents the read-upset condition from
occurring while simultaneously maintaining acceptable circuit
speed and area constraints
EE 534 summer 2004 University of South Alabama
SRAM Cell Analysis (Read)
WL=1
M4
M6
M5 Q=0 Q=1
M1
Cbit Cbit
BL=1
BL=1
Cell Ratio (CR) = (WM1/LM1)/(WM5/LM5)
VQ = [(Vdd - VTn)(1 + CR (CR(1 + CR))]/(1 + CR)
To avoid read-disturb, the voltage on node Q should remain below the trip point
of the inverter pair for all process, noise, and operating conditions.
EE 534 summer 2004 University of South Alabama
Read Voltages Ratios
Vdd = 2.5V
VTn = 0.5V
1.2
1
Voltage Rise on !Q
0.8
0.6
0.4
0.2
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4
Cell Ratio (CR)
The voltage rise inside the cell will not rise above the threshold if Cr>1.2
EE 534 summer 2004 University of South Alabama
SRAM Cell Analysis (Write)
WL=1
State shown is
M4
that before M6
write takes M5 Q=0 Q=1
effect (1 is M1
stored, trying
to write a 0)
BL=1 BL=0
Pullup Ratio (PR) = (WM4/LM4)/(WM6/LM6)
VQ = (Vdd - VTn) ((Vdd – VTn)2 – (p/n)(PR)((Vdd – VTn - VTp)2)
In order to write the cell, the pass gate M6 must be more conductive than the M4 to allow
node Q to be pulled to a value low enough for the inverter pair (M2/M1) to begin
amplifying the new data.
The maximum ratio of the pullup size to that of the pass gate required to guarantee that
the cell is writable – M6 in linear, M4 in saturation
EE 534 summer 2004 University of South Alabama
Write Voltages Ratios
Vdd = 2.5V
|VTp| = 0.5V
1 p/n = 0.5
0.8
Write Voltage (VQ)
0.6
0.4
0.2
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4
Pullup Ratio (PR)
EE 534 summer 2004 University of South Alabama
Design Issues: Cell Sizing
Keeping cell size minimized is critical for large caches
Minimum sized pull down fets (M1 and M3)
Requires minimum width and longer than minimum channel
length pass transistors (M5 and M6) to ensure proper CR
But sizing of the pass transistors increases capacitive load on
the word lines and limits the current discharged on the bit lines
both of which can adversely affect the speed of the read cycle
Minimum width and length pass transistors
Boost the width of the pull downs (M1 and M3)
Reduces the loading on the word lines and increases the
storage capacitance in the cell – both are good! – but cell size
may be slightly larger
EE 534 summer 2004 University of South Alabama
6T-SRAM — Layout
Actually all transistors in 6-T
SRAM cell can be minimum-
sized regardless of the M2 M4
VDD
writability concerns, as long as
the differential signal is
maintained (one side will be able
to write in, and then the bi- Q Q
stability takes over) M1 M3
The bit lines are usually pre- GND
charged to VDD/2 instead of VDD
M5 M6 WL
to take full advantage of the
differential signal.
BL BL
EE 534 summer 2004 University of South Alabama
Resistance-load SRAM Cell
WL
VDD
RL RL
Q Q
M3 M4
BL M1 M2 BL
Static power dissipation -- Want RL large
Bit lines precharged to VDD to address t p problem
EE 534 summer 2004 University of South Alabama
MOS NOR ROM
Logic 1 bit is stored as a the absence of an active transistor
While a logic 0 bit is stored as the presence of an active transitor.
VDD
Pull-up devices
WL[0] 1 0 1 1
GND
WL[1] 0 1 1 0
WL[2] 1 0 1 0
GND
WL[3] W0: 1011
1 1 1 1 W1: 0110
W2: 1010
BL[0] BL[1] BL[2] BL[3] W3: 1111
In actual ROM layout 1 bit is programmed by omitting the drain or source connection
0 534 is programmed of South Alabama
EE bit summer 2004 University by connecting the drain to the ground or metal to diffusion contact
Erasable Programmable ROM(EPROM): Floating-gate transistor
(FGMOS)
Floating gate Gate
D
Source Drain
tox G
tox
S
p
n+ n+
Substrate
(a) Device cross-section (b) Schematic symbol
EE 534 summer 2004 University of South Alabama
Floating-Gate Transistor Programming: EPROM
20 V 0V 5V
20 V 0V 5V
10 V 5 V -5 V -2.5 V
S D S D S D
Avalanche injection. Removing programming voltage Programming results in
leaves charge trapped. higher V T.
Hot-carrier injection is self-limiting: no detailed control circuitry necessary
Writing and sensing on the same transistor: simplified
Erase by UV may have residual effects
Virtually all nonvolatile memories are currently based on the floating gate approach.
EE 534 summer 2004 University of South Alabama
Floating gate tunneling oxide (FLOTOX): EEPROM
Floating gate Gate I
Source Drain
20-30 nm -10 V VGD
10 V
n+ n+
Substrate
p
10 nm
(a) Flotox transistor (b) Fowler-Nordheim I-V characteristic
BL
F-N tunneling is not as self-
limiting, and read/write need to
be carefully controlled.
WL
Vth variation is large: one more
control transistor
V DD
Other geometry possible (split-
gate, etc.)
(c) EEPROM cell during a read operation
EE 534 summer 2004 University of South Alabama
Floating-gate transistor (FGMOS) :Flash Memory
Control gate
Floating gate
erasure Thin tunneling oxide
n+ source n+ drain
programming
p-substrate
Hot-carrier injection write operation (self-limiting)
Block erase by F-N tunneling with careful tuning on the block level
Sensing by the same transistor (small cell footprint)
EE 534 summer 2004 University of South Alabama
Cross-sections of NVM cells
Flash Courtesy Intel
EPROM
EE 534 summer 2004 University of South Alabama
Characteristics of State-of-the-art NVM
EE 534 summer 2004 University of South Alabama
Next Lecture and Reminders
Next lecture
Project report due on 1st December
Project oral exam: 1st December full adder group.
EE 534 summer 2004 University of South Alabama
