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CSC Muon Trigger
On Detector Components
B. Paul Padley
Rice University
June, 2002
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 1
CMS Endcap Muon System
• 3 or 4 stations
• Each CSC chamber has
six planes:
1. Radial cathode strips for
precision muon position
and bend direction
measurement
2. Anode wires for timing
(bunch ID) and non-bend
position measurement
• There is also a RPC
system overlapping the
CSC‟s to provide a
redundant trigger
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 2
CSC Muon Triggering
• Trigger primitives are wire and strip segments
• Wires give 25ns bunch crossing
• Strips give precision information
• Link trigger primitives into tracks
• Assign pT , , and
• Send highest quality tracks to Global L1
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 3
Trigger requirements
Cathode LCT
• Identify cathode track segment.
Pt trigger based on angle of LCT
• For Pt threshold of 20-40 GeV requires
Dp/p < 30% (in order to limit single
muon trigger rate in Level-1 to a few
KHz)
• Track hits must be located to within ½
strip width in each chamber layer
Anode LCT
• Form anode track segment.
• Tag bunch crossing of track segment
with > 92 % efficiency per chamber
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 4
EMU “Trigger” Cards
Anode LCT Card (ALCT)
• Sits on Chamber
• Receives Anode Front End Board discriminator signals
• Finds eta coordinate of two best track stubs and quality
• Sends to Trigger Motherboard
Trigger Motherboard (TMB)
• Receives ALCT info
• Receives Cathode Front End Board discriminator
Signals
• Finds location, bend angle and quality of two best
cathode track stubs
• Correlates Anode and Cathode LCT‟s
• Sends to Port Card (MPC)
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 5
EMU “Trigger” Cards Cont‟d
EMU Clock and Control Board (CCB)
• Receives Clock and Control signals (such as
L1accept, reset…) from Trigger Timing and
Control system
• Redistributes these signals on the custom
backplane.
RPC Interface Module (RIM)
• Transition module that receives RPC trigger
information
• Could be used in TMB to eliminate ghosts (if
they are a problem).
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 6
Endcap Muon Trigger Primitive
Generation
Clock Control Board Trig Motherboard
DAQ Motherboard
D TD T D TD TDT CMTD T D TD TD
M M M MM M M M M M C P M MM M M MM M
CBB B BB BBB BB BCB BB BB BB B
O
N
T
R
Trigger-Timing-Control
O
Optical L
L
link E
R
Peripheral Crate
on iron disk
Muon Sector Receiver
Lev-1 Trigger Cathode Front-end Board
CFEB CFEB CFEB CFEB CFEB
LVDB ALCT
Anode LCT Board
In underground On detector
counting room
Anode Front-end Board
CSC
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 7
Peripheral Crate
Board # per Responsibility
crate
VME Cont. 1 OSU
There are
TMB/ 9 UCLA
DT D T D T D T D T CMT DT D T DT D 48
CLCT MM M MM M M M M M C P M MM M M MM M
C BB B BB BB B BB B CB BB B B BB B peripheral
O
DMB 9 OSU N crates in the
Clock and 1 Rice
T
R Endcap
Control O
L
Muon
Board L system
E
Muon 1 Rice R
Port Card
Only “on detector” “Trigger” board is the Muon
Port Card (MPC)
It accepts ALCT/CLCT pairs from each TMB
Selects the best 3 and sends to counting room.
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 8
CSC Sectors Data Mapping
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 9
CSC Muon Trigger Scheme
On-Chamber 3-D Track-Finding
Trigger Muon and Measurement
Trigger Primitives Port
Motherboard Sector
Strip FE cards (UCLA) Card
Receiver/ Processor
(Rice)
(U. Florida)
LCT OPTICAL
FE
MPC SR/SP SP
LCT
TMB 3 / port card
FE
2 / chamber 3 / sector
Wire LCT card
Wire FE cards In
counting
RIM house CSC Muon Sorter
RPC Interface RPC DT (Rice)
Module 4 4 4
Combination of all Global Trigger Global L1
3 Muon Systems 4
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 10
Responsibilities
USCMS Endcap Muon USCMS Trigger/DAQ 3.1.1
OSU Cathode LCT/
Motherboard/ Port Sector Receiver Sector Processor
Cathode Front-End RPC
Card
OPTICAL
LCT SR/SP
Florida
CFE 3.1.1.17
MPC
AFE
TMB
Anode Anode
CSC
Front-End LCT Rice
RPC Muon
Rice 3.1.1.15
in. Sorter
CMU 3.1.1.1
RPC DT
Rice
UCLA /UCLA
Global Global L1
Trigger Vienna
3.1.1.5
Clock & Clock & Also: 3.1.1.7 Backplanes - Florida
Control1 Rice Control2 3.1.1.8-11 controllers, crates, power
supplies, cables
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 11
Current Project Status
• Trigger primitives are formally part of Endcap Muon project
• ALCT
• 384 channel version, in production
• 672 and 288 channel versions – pre-production prototypes being
evaluated
• CLCT/TMB – 17 prototypes made – 3 debugged and being evaluated
• First Track Finder system (TRIDAS) prototyped successfully
in „00
• Also, trigger part of CMS OO simulation package was developed
• Some hardware modifications were desired:
• Decrease latency
• Implement DAQ diagnostic readout
• Currently Building 2nd prototypes of system
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 12
Technical Issues Addressed
with Second Prototypes
• Level 1 trigger latency
• Front-end buffer size is limited (tracking, pre-radiators)
• Track Finder must deliver muons to GMT by 79 crossings (1975 ns) after
muon collision
• Prototype 1 (including trigger primitive electronics) was too slow – some
surprises were encountered, e.g. Channel-Link latency about 100 ns ( x5
places used)
• How to reach requirement is being incorporated in new design:
Optimize data transfer protocols between boards
Decrease some bit counts
Faster FPGA chips (often 80 MHz versus 40 MHz)
Improved FPGA algorithms
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 13
Optical Link Radiation Tests
Three serializers: up to 270 kRad TID.
No permanent damage or SEU
Two Finisar optical modules: No errors up to 70 kRad.
Failed at
~70kRad
(well above
~10 kRad TID
inner CSC
dose for
10 years)
-- Rice
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 14
Muon Port Card Prototype 1
VME
Interface
Optical
links
Main FPGA
on Daughter
Card
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 15
New MPC Design (Rice)
9U x 400 MM BOARD VME J1
CONNECTOR
VME
INTERFACE
UCLA MEZZANINE CCB
CARD (XCV600E)
CCB
TMB_1
OPTO SER CCB
INTERFACE TMB_2
CUSTOM
3 OPTICAL SORTING TMB_3 PERIPHERAL
LOGIC
CABLES TO BACKPLANE
OPTO SER TMB_4
SECTOR INPUT
PROCESSOR AND TMB_5
OUTPUT
FIFO TMB_6
OPTO SER
TMB_7
FINISAR FTRJ-8519-1-2.5
OPTICAL TRANSCEIVERS
TMB_8
TLK2501 SERIALIZERS FPGA
TMB_9
SN74GTLP18612 GTLP TRANSCEIVERS
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 16
New Peripheral Backplane
Bit 3
VME/PCI
interface 3U
VME
A24D16
VME
Display
Custom
Backplane
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 17
New Port Card
Board is partially stuffed TLK2501 (1 of 3) Breadboard area
We are adding (always prudent)
components and then
testing, iteratively
VME
JTAG
Input/output FIFO’s VME
Sorting Logic connector
Finisar optical
transceiver Custom
(1 of 3) backplane
connector
Mezzanine card with PLD
(PLD is on other side)
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 18
Personnel
• Professors
• Jay Hauser (UCLA), Paul Padley (Rice)
• Postdocs
• Martin Von der Mey (UCLA), TBA (Rice)
• Students
• Greg Pawloski (Rice)
• Engineers
• JK (UCLA), Mike Matveev (Rice), Ted Nussbaum (Rice)
US CMS DOE/NSF Review: June 2002, B.Paul Padley, Rice University 19
