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MICROCONTROLLER BASED

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					        MICROCONTROLLER BASED
       ALARM ANNUNCIATOR SYSTEM

           VIIth SEMESTER, FINAL YEAR


GUIDE:
Ms. REEMA AGARWAL (FACULTY, Department of Electronics and
Communication Engineering)


SUBMITTED BY:

AKANKSHA SHARMA – 03
ALPANA GUPTA – 05
PRIYANKA SHARMA – 45
SHWETA SABOO – 54
SONAL SHARDA – 57
                                SYNOPSIS
  MICROCONTROLLER BASED ALARM ANUNCIATOR
                 SYSTEM
Today, all instrumentation systems pertaining to industrial process control as well
as domestic applications, involve some type of automatic fault - finding facility.
This facility detects the faulty condition of the system and draws the attention of
the operator towards it, enabling him to take suitable remedial action to ensure the
proper operation of the system.
One such method is annunciation in which activation of a visual or a mechanical
indicator (called annunciator) takes place when a remote switch or device has been
activated as result of fault in certain part of the system. An audio alarm may also
be associated with annunciators.
This microcontroller based annunciator system detects up to eight different faulty
conditions and informs the operator about them. It is assumed that each faulty
condition results in closing of one of the eight interlock links. Eight flashing Light
Emitting Diodes (LEDs), corresponding to each of the eight links, have been used
as annunciators.
Each annunciation also results in an audible alarm. Here only the faults persisting
for more than 20 milliseconds are considered as critical and faults persisting for
less than 20 milliseconds are rejected.

SOURCE from where the IDEA was taken:
The idea of the Project was proposed by Mr. S. N. Vijayvargiya, General
Manager, Rajasthan Electronics and Instruments Ltd. (REIL), Kanakpura
Industrial Area, Jaipur.
The design of the Block Diagram was suggested by Mr. Subhash Bansal,
Engineer, R & D, REIL.
The next job was to construct the circuit diagram, which required an intense
research from various fields like on the internet explorer and in various magazines.
After the concentrated study line, finally the circuit was found in the EFY issue
December 2002.




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                                   FLOW CHART
                                                   Start


                                                                                       SCAN TEST BUTTON
                                      RESET ALL THE OUTPUTS
                                                                                           CLOSED?
                                                                                                               YES
                                                     NO
                                                                                 NO

                                   SCAN LINK FOR FAULTS
                                         CLOSED?                                         BLINK ALL LEDS
                                                                                      WITH AUDIBLE SOUND


                                                    YES

                            BLINK THE CORRESPONDING LED
                             ALONG WITH AUDIBLE SOUND                         BLINK ALL LEDS EXCEPT
                                                                            THOSE WHICH CORRESPOND
                         1. IF NEW FAULT IS                                TO ALREADY DETECTED FAULTS
                            FOUND                                            LIT CONTINUOUSLY ALONG
                                                                                WITH AUDIBLE SOUND

                                                                                      3. IF TEST BUTTON IS CLOSED
                               1. CHECK LINKS FOR NEW FAULTS
                                   2. CHECK ACCEPT BUTTON
                               3. CHECK TEST BUTTON CLOSED?



                                                  2. IF ACCEPT BUTTON IS CLOSED


                           CONTINUOUSLY LIGHT THE CORRSPONDING
                                    LED WITH NO SOUND

                                                                          3. IF TEST BUTTON IS CLOSED
               1. IF ANOTHER FAULT IS FOUND
                                                                                                  BLINK ALL LEDS EXCEPT
 LED CORRESPONDING                                                                                       THE LEDS
  TO THE NEW FAULT                            1. CHECK LINKS FOR ANOTHER                             CORRESPONDING
         WILL                                 FAULTS.                                            TO THE FAULTS ALREADY
 BLINK & CONTINUOUS                           2.CHECK FOR CLEAR BUTTON.                           ACCEPTED WHICH WILL
     GLOW OF THE                              3CHECK TESTBUTTON CLOSED                             CONTINUOUSLY GLOW
       ALREADY                                                                                     WITH AUDIBLE SOUND
  ACCEPTED FAULTS
         LEDs                                                  2. IF CLEAR BUTTON IS CLOSED
 ALONG WITH AUDIBLE
        SOUND
                                         CLEAR ALL LEDS AND DISABLE
                                             THE AUDIBLE SOUND



                                                           GO TO START




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              BLOCK DIAGRAM




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                 PROGRAM CODE
Address Opcode      Label                    Mnemonics comments
ORG 0000H                                    ; initialize the reset vector
0000 020010         LJMP INT                 ; jump to the actual
                                             ; program
                                             ; address#30h        0003 22
RET at
ORG 0010h                               ; define the actual program
0010 758130         INT: MOV SP, #30h   ; preset the stack pointer
0013 D2B0           SETB P3.0           ; disable sound
0015 7B00           MOV R3, #00H        ; clear register
0017 7C00           MOV R4, #00H        ; clear register
0019 E4             CLR A               ; clear accumulator
001A 908000         START: MOV DPTR, ; data pointer is assigned with
                    #8000H              ; led port add
001D F0             MOVX @ DPTR, A      ; disable all leds
001E D2B3           SETB P3.3           ; set the i/p to read
0020 A2B3           MOV C, P3.3         ; read the test i/p
0022 400A           JC TEST             ; check for test i/p
0024 7590FF         MOV P1, #0FFH       ; set port1 to read the i/p fault
0027 E590           MOV A, P1           ; read the i/p fault
0029 B40013         CJNE A, #00H, SCAN  ; check for fault
002C 80E2           SJMP INT            ; jump to initial
002E 74FF           TEST: MOV A, #0FFH ; load the data to light all
                                        ; these
0030 F0             MOVX @DPTR, A       ; o/p at led port
0031 C2B0           CLR P3.0            ; enable sound
0033 1200E5         LCALL DELAY         ; delay for blink and beep
0036 E4             CLR A               ; load the data to put off
                                        ; leds
0037 F0             MOVX @DPTR, A       ; o/p at led port
0038 D2B0           SETB P3.0           ; disable sound
003A 1200E5         LCALL DELAY         ; delay for blink and beep
003D 80DB           SJMP START          ; jump to start
003F 7590FF         SCAN: MOV P1, #0FFH ; set port to read fault
0042 E590           MOV A, P1           ; read the fault
0044 FB             MOV R3, A           ; save for future use
0045 60C9           JZ INT              ; check for fault
0047 EB             SHOW: MOV A, R3     ; load detected fault
0048 F0             MOVX @DPTR, A       ; o/p at led port

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0049 C2B0           CLR P3.0             ; enable sound
004B 1200E5         LCALL DELAY          ; delay for blink and beep
004E E4             CLR A                ; data for led off
004F F0             MOVX @DPTR, A        ; o/p at led port
0050 D2B0           SETB P3.0            ; disable sound
0052 1200E5         LCALL DELAY          ; delay for blink and beep
0055 D2B4           CHKACP: SETB P3.4 ; set to read accept i/p
0057 A2B4           MOV C, P3.4          ; read accept i/p
0059 401A           JC ACCEPT            ; check for accept i/p
005B D2B3           CT1: SETB P3.3       ; set to read test i/p
005D A2B3           MOV C, P3.3          ; read test i/p
005F 4002           JC TEST1             ; check for test i/p
0061 80DC           SJMP SCAN            ; jump for scan routine
0063 74FF           TEST1: MOV A, #00FFH ; data for led lit
0065 F0             MOVX @DPTR, A        ; o/p at led port
0066 C2B0           CLR P3.0             ; enable sound
0068 1200E5         LCALL DELAY          ; delay for blink and beep
006B E4             CLR A                ; data for led off
006C 4B             ORL A, R3            ; combine with already found
                                         ; fault
006D F0             MOVX @DPTR, A        ; o/p at led port
006E D2B0           SETB P3.0            ; disable sound
0070 1200E5         LCALL DELAY          ; delay for blink and beep
0073 80CA           SJMP SCAN            ; jump to scan routine
0075 7590FF         ACCEPT: MOV PI,
                    #0FFH                ; set to read i/p fault
0078 E590           MOV A, PI            ; read the fault
007A 4B             ORL A, R3            ; combine with already found
                                         ; fault
007B 6B             XRL A, R3            ; set flag to find new faults
007C 603B           JZ CHKCLR2           ; there is no few fault, check
                                         ; for clear i/p
007E 7590FF         MOV PI, #0FFH        ; set to read i/p
0081 E590           MOV A, PI            ; read i/p
0083 FC             MOV R4, A            ; save for future use
0084 4B             ORL A, R3            ; combine with already found
                                         ; fault
0085 EB             MOVA, R3             ; load already found fault
0086 4C             ORL A, R4            ; combine with new fault
0087 F0             MOVX @ DPTR, A       ; o/p at led port
0088 C2B0           CLR P3.0             ; enable sound
008A 1200E5         LCALL DELAY          ; delay for blink and beep
008D E4             CLR A                ; data for led off
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008E 4B             ORL A, R3            ; combine with already found
                                         ; fault
008F F0             MOVX @ DPTR, A       ; o/p at led port
0090 D2B0           SETB P3.0            ; disable sound
0092 1200E5         LCALL DELAY          ; delay for blink and beep
0095 D2B4           CHKACP1: SETB P3.4 ; set to read accept i/p
0097 A2B4           MOV C, P3.4          ; read accept i/p
0099 401B           JC CHKCLR1           ; check for accept i/p
009B D2B3           CT2: SETB P3.3       ; set to read accept i/p
009D A2B3           MOV C, P3.3          ; read test i/p
009F 4002           JC TEST2             ; check the test i/p
00A1 80D2           SJMP ACCEPT          ; jump to accept routine
00A3 74FF           TEST2: MOV A, #0FFH ; data to lit leds
00A5 F0             MOVX @ DPTR, A       ; o/p at led port
00A6 C2B0           CLR P3.0             ; enable sound
00A8 1200E5         LCALL DELAY          ; delay for blink and beep
00AB E4             CLR A                ; data to off led
00AC EB             MOV A, R3            ; combine with already found
                                         ; fault
00AD 4C             ORL A, R4            ; combine with new fault
00AE F0             MOVX @ DPTR, A       ; o/p at led port
00AF D2B0           SETB P3.0            ; disable sound
00B1 1200EF         LCALL DELAY          ; delay for blink and beep
00B4 80BF           SJMP ACCEPT          ; jump to accept routine
00B6 EB             CHKCLR1: MOV A, R3 ; load the already found fault
00B7 4C             ORL A, R4            ; combine with new fault
00B8 FB             MOV R3, A            ; save for future use
00B9 EB             CHKCLR2: MOV A, R3 ; load already found fault
00BA F0             MOVX @DPTR, A        ; o/p at led port
00BB D2B0           SETB P3.0            ; disable sound
00BD D2B5           SETB P3.5            ; set to read clear i/p
00BF A2B5           MOV C, P3.5          ; read clear i/p
00C1 401B           JC CLEAR             ; check for clear i/p
00C3 D2B3           CT3: SETB P3.3       ; set to read test i/p
00C5 A2B3           MOV C, P3.3          ; read test i/p
00C7 4002           JC TEST3             ; check for test i/p
00C9 80AA           SJMP ACCEPT          ; jump to accept routine
00CB 74FF           TEST3: MOV A, #00FFH ; data to lit leds
00CD F0             MOVX @DPTR, A        ; o/p at led port
00CE C2B0           CLR P3.0             ; enable sound
00D0 1200EF         LCALL DELAY          ; delay for blink and beep
00D3 E4             CLR A                ; data led off

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00D4 4B             ORL A, R3            ; combine with fault found
00D5 F0             MOVX @DPTR, A        ; o/p at led port
00D6 D2B0           SETB P3.0            ; disable sound
00D8 1200E5         LCALL DELAY          ; delay for blink and beep
00DB 020075         LJMP ACCEPT          ; jump to accept routine
00DE E4             CLEAR: CLR A         ; data to led off
00DF F0             MOVX @DPTR, A        ; o/p at led port
00E0 D2B0           SETB P3.0            ; disable sound
00E2 020010         LJMP INT             ; jump to initial routine
00E5 7DFF           DELAY: MOV R5,
                    #00FFH               ; count for delay
00E7 7EFF           D1: MOV R6, #00FFH   ; count for delay
00E9 DEFE           D2: DJNZ R6, D2      ; decrement count
00EB DDFA           DJNZ R5, D1          ; decrement count
00ED 22             RET                  ; return from delay routine




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  WORKING OF ALARM ANNUNCIATOR
              SYSTEM
Basic requirements of an annunciator system: -
 I. A set of inputs (16 or 8 depending upon the requirement) to be scanned and
     controlled. The inputs may 9include contact switches, relays etc.
II. Input buffers and/or isolating devices to interface the actual inputs to the
     microcontroller.
III. A microprocessor/microcontroller to look after the entire fault-finding
     process, such as reading the inputs, interpreting the faults, outputting the
     corresponding fault condition with audible alarm, and self-testing of the
     system itself to ensure the overall functioning of the system.
IV. Output indication devices such as LEDs, relays and audible alarm along with
     their interfacing devices (like latches).

Circuit description
Figure shows the circuit diagram of the annunciator built around an 80C31
microcontroller. Since the 80C31 doesn’t have a program memory; an EPROM is
used to store the firmware of the system. Octal 3-state latch IC 74373 is used for
low order address (A0-A7) decoding. We may use any one of 2764, 27128 and
27256 EPROMs by setting jumpers J1 and J2.
The combination of R13 and capacitor C1 provides the necessary slow-rising
power-on-reset signal to the microcontroller’s reset input pin 9. The eight inputs to
be scanned are connected to the eight input pins (P1.0 through P1.7) of port1 of
the microcontroller via eight CMOS inverters (CD40106). Three additional inputs
(P3.3 through P3.5) of port3, which are controlled by the switches marked TEST
(S1), ACCEPT (S2), and CLEAR (S3), are interfaced to the controller’s input pins
13, 14 and 15 respectively, through three inverter buffer gates (CD40106).
Each output of the system is connected to the respective LED through latch 74373
and Darlington transistor driver ULN2803. The address decoding logic for the
output is performed by two OR gates (7402) using address signal A15 and write
signal WR of the 80C31. Here the address assigned to the LED output port is
8XXXh, where X means ‘don’t care’. The buzzer for generating the audible alarm
is connected to P3.0 (pin 10) of IC1 through inverter gate N14 and NPN transistor
driver CL100. The system clock is generated using the 12 MHz crystal connected
across oscillator pins 18 and 19 of the microcontroller.



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In this design the four ports available in the 8031 microcontroller are configured
as below:
PORT 0: For outputting the 8-bit low order address and data to the program
memory and outputting the input conditions read by the microcontroller.
PORT 1: For reading the status of eight input links.
PORT 2: For outputting the 8-bit higher order addresses.
PORT 3: Pin 3.0 is used to enable the audio output. Pins P3.3, P3.4 and P3.5 are
used to read inputs TEST, ACCEPT and CLEAR respectively and P3.6 (WR
signal) is used for address decoding of the output port (LEDs). The remaining pins
in this remain unused.
PSEN is used for reading the external program memory, while ALE is used for
latching the low-order address bits in IC2.
One terminal of the eight input links is connected to GND pin of connector CON2
and the other terminals of the links is connected to the respective input pin of
connector CON2. Similarly, one terminal of control pushbuttons TEST, ACCEPT
and CLEAR is connected to the respective input pin of the connector and the other
terminals of these pushbuttons are shorted and connected to GND. The 5V power
supply input (via 4.7 – kilo - ohm pull-up resistors) and GND are connected to
respective pins of connectors.
To interface this circuit with the actual control circuit of systems like elevator
control or centralized air-conditioned control, GND and signal inputs of the eight
links are removed and substituted with corresponding relay contacts of the actual
system. The relays operate off the power supply of the actual system that requires
detection/indication of faults.

Firmware
The firmware of the system is developed using the 8031 cross assembler .it
comprises the following routines:
   i. SELF-TEST ROUTINE: To check the reliable working of the system.
        Whenever TEST button is pressed, all the LEDs must blink with a beep
        sound.
   ii. SCANNING ROUTINE: To check the faulty conditions. In case a fault
        is found (link closed), the corresponding output LED blinks with an audible
        sound.
   iii. ACCEPT ROUTINE: To accept the faulty conditions. Whenever a fault
        is found, this routine checks and accepts the faulty condition. The
        continuous glowing of the LED corresponding to the fault found but no
        corresponding sound from the buzzer indicates that the given fault has been
        noted for action.

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   iv. CLEAR ROUTINE: To clear/reset the accepted fault conditions after
       rectifying the faults. Whenever the clear button is pressed, the controller
       resets all the fault conditions accepted earlier, and once again goes back to
       the scanning mode.
The entire program is written in Assembly language and its corresponding Hex
code is dumped in the EPROM.
Figure shows flow-chart of the program. After resetting the system, the firmware
clears all the outputs including the audible alarm sound. Then it scans for the
faulty inputs as well as the TEST input. If the program finds the TEST input
pressed, all the eight fault indicating LEDs blink with audible sound. Otherwise,
the program continues looping in the scanning routine.
If some fault occurs (resulting in closing of a link) during the scanning mode, the
corresponding LED in the output port (8000h) blinks with an audible sound.
Now the program in a loop looks for another fault or ACCEPT input or TEST
input. If another fault occurs, the same routine is repeated. If TEST input button is
pressed, all LEDs in the output port blink, except those corresponding to the fault
found earlier. The LEDs corresponding to the fault found earlier glow
continuously with the audible sound. However if ACCEPT input is pressed, the
output LEDs corresponding to the faulty (accepted) inputs continuously glow with
no sound.
Now the program enters the final phase, where it checks for CLEAR, TEST and
FAULT input button depressions. If another fault comes at this stage, the
corresponding LED blinks with audible sound and the LEDs corresponding to the
already accepted faults glow continuously. If TEST input comes at this phase, all
the LEDs blink with audible sound and the LEDs corresponding to the already
accepted faults glow continuously. If CLEAR input button is pressed, it clears all
the output LEDs and disables the audible sound. The program once again enters
the START mode, where it looks for fresh faults and TEST inputs.
In this circuit, as faulty conditions are simulated by closing of the eight links, the
links for the accepted faults must be removed before pressing the CLEAR push
button. Otherwise the program will once again detect the same fault because the
links are still simulating the same faulty conditions.




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                   DESCRIPTION OF ICs
                   1) 80C31 MICROCONTROLLER
The Philips 80C31 is a high-performance static 80C51 design fabricated with
Philips high-density CMOS technology with operation from 2.7 V to 5.5 V.

The 80C31 ROMless devices contain a 128 × 8 RAM, 32 I/O lines, three 16-bit
counter/timers, a six-source, four-priority level nested interrupt structure, a serial
I/O port for either multi-processor communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock circuits.

In addition, the device is a low power static design which offers a wide range of
operating frequencies down to zero. Two software selectable modes of power
reduction-idle mode and power-down mode are available. The idle mode freezes
the CPU while allowing the RAM, timers, serial port, and interrupt system to
continue functioning. The power-down mode saves the RAM contents but freezes
the oscillator, causing all other chip functions to be inoperative. Since the design
is static, the clock can be stopped without loss of user data and then the execution
resumed from the point the clock was stopped.
Features of 80C31 microcontroller

    8051 Central Processing Unit:
           o   128 × 8 RAM (80C31)
           o   Three 16-bit counter/timers
           o   Boolean processor
           o   Full static operation
           o   Low voltage (2.7 V to 5.5 V@ 16 MHz) operation
    Memory addressing capability:
           o 64k ROM and 64k RAM
    Power control modes:
           o Clock can be stopped and resumed
           o Idle mode
           o Power-down mode
    CMOS and TTL compatible
    TWO speed ranges at VCC = 5 V:
           o 0 to 16 MHz
           o 0 to 33 MHz
    Three package styles
    Extended temperature ranges

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      Dual Data Pointers
      4 level priority interrupt
      6 interrupt sources
      Four 8-bit I/O ports
      Full-duplex enhanced UART:
         o Framing error detection
         o Automatic address recognition
      Programmable clock out
      Asynchronous port reset
      Low EMI (inhibit ALE)
      Wake-up from Power Down by an external interrupt




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   6 interrupt sources
   Four 8-bit I/O ports
   Full-duplex enhanced UART:
       o Framing error detection
       o Automatic address recognition
   Programmable clock out
   Asynchronous port reset
   Low EMI (inhibit ALE)
        Wake-up from Power Down by an external interrupt




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                           2) 74373 OCTAL LATCH

   8-bit 3-state transparent latch

      +---+--+---+              +---+---+---*---+
/OE   |1 +--+ 20|    VCC        |/OE| LE| D | Q |
 Q1   |2       19|   Q8         +===+===+===*===+
 D1   |3       18|   D8         | 1 | X | X | Z |
 D2   |4       17|   D7         | 0 | 0 | X | - |
 Q2   |5   74 16|    Q7         | 0 | 1 | 0 | 0 |
 Q3   |6 373 15|     Q6         | 0 | 1 | 1 | 1 |
 D3   |7       14|   D6         +---+---+---*---+
 D4   |8       13|   D5
 Q4   |9       12|   Q5
GND   |10      11|   LE
      +----------+

The 8031 architecture allows for external program and data access through the use
of Port 0 and Port 2 as an external memory interface. The 8031 architecture
multiplexes the data and LSB of address on Port 0, requiring a 74373 latch for
demultiplexing. This means that Port 0 will be directly connected to at least two
devices. More devices may be placed on the bus if an external data SRAM or
memory-mapped peripherals are used.




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                                   3) ULN 2803
8-bit 50V 500mA TTL-input NPN Darlington driver

The drivers need no power supply; the VDD pin is the common cathode of the
eight integrated protection diodes.




The output section is controlled by an eight-line "Darlington Driver" integrated
circuit (IC) called a ULN2803. The digital state of each of the eight lines from the
printer port is used to control the IC's internal "drivers" which in turn control the
Relays and LEDs. Power for the Relays and LEDs is provided by the 12 volt
regulator (LM 7812) via a plug pack power supply of at least 15 volts and capable
of supplying at least 1 amp. In this interface, each of the eight output lines at the
printer port is connected via a 560ohm to a LED. Four of the output lines also
have relays attached.




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                  4) IC 7402 Quad 2- Input NOR gate

This device contains 4 independent 2-input NOR gate.




                                 INPUTS            OUTPUT
                            A             B            Y
                             L            L            H
                             L            H            L
                            H             L            L
                            H             H            L




All four NOR gates may be used independently.
On any one gate if either input is high the output is low.
Propagation delay – 10 nanoseconds.
Typical current per package – 12mA.




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                                5) EPROM 25276
EPROM (Erasable Programmable Read Only Memory) can be programmed and
erased enabling them to be re-used. Erasure is accomplished using an UV (Ultra
Violet) light source that shines through a quartz erasing window in the EPROM
package.

  There also are OTP (One Time Programmable) EPROMs, sometimes called
OTPROMs (One Time Programmable Read Only Memory) that are identical to an
erasable EPROM but lack an erasing window to reduce costs.

   In an EPROM, the cell at each intersection has two transistors. A thin oxide
layer separates the two transistors from each other. One of the transistors is known
as the floating gate and the other as the control gate. The floating gate's only link
to the row (word line) is through the control gate. As long as this link is in place,
the cell has a value of 1. To change the value to 0 requires a curious process called
Fowler-Nordheim tunneling. Tunneling is used to alter the placement of electrons
in the floating gate. An electrical charge, usually 10 to 13 volts, is applied to the
floating gate. The charge comes from the column (bit line), enters the floating gate
and drains to a ground.

  This charge causes the floating-gate transistor to act like an electron gun. The
  excited electrons are pushed through and trapped on the other side of the thin
oxide layer, giving it a negative charge. These negatively charged electrons act as
  a barrier between the control gate and the floating gate. A device called a cell
 sensor monitors the level of the charge passing through the floating gate. If the
flow through the gate is greater than 50 percent of the charge, it has a value of 1.
When the charge passing through drops below the 50-percent threshold, the value
 changes to 0. A blank EPROM has all of the gates fully open, giving each cell a
                                     value of 1.




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                       Testing Equipments
1. INTELLIGENT UNIVERSAL PROGRAMMER (IUP)
2. Bread Board
4. Personal Computer
5. Multimeter
7. Power supply




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                Test Procedure and Results
The Procedure started with a detailed observation of the circuit then collecting
details about the components and studying their specifications. Due attention to
diodes and electrolytic capacitors as they are polarity dependent. The first step
began by trying out the circuit on CAD software and visualizing the simulation
results. Then begin the voyage of physically testing the circuit at small scale by
testing independently minor parts of the circuit for example full wave rectifier or
sample hold circuit on bread board and when output was found appropriate, the
next step was to integrate all the minor independent units into a major unit and
test the output of the final unit. In this whole process the basic step was to test
the voltage and current at various pins of active and passive devices. All testing
was done by using ICs with the IC base to prevent ICs against electrostatic
damage.




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List of the components and their cost:
ICs
Microcontroller       IC 8031      01
Octal Latch           IC 74373     02
EPROM                 IC 27256     01
Octal Buffer Driver   IC ULN2803   01
Quad NOR Gate         IC 7402      02
Hex Schmidt Trigger
Inverter              IC CD40106   02
NPN Transistor        SL100        01

IC Base Socket DIL
40 pin                             01
20 pin                             02
28 pin                             01
18 pin                             01
14 pin                             03

Capacitors
Ceramic Disk          22 pf        02
Ceramic Disk          0.1 uf       08
Electrolytic          10 uf, 25V   01

Resistors
                      1.8 K        08
                      6.8 K        01
                      10 K         01
                      4.7 K        11
                      8.2 K        01

Diodes
                      IN 4007      04

Others
LEDs                  Red          08
Switch                Push to On   03
Crystal Oscillator    12MHz        01
Peizo Buzzer                       01

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General Purpose PCB                01




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