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Assignment

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									    SYSC3601                                COURSE ASSIGNMENT                                Winter 2011

               Design of a Microprocessor Security System
Instructions
1. This design exercise is to be completed in your lab groups, one submitted report per group.
2. Due Date: Friday April 8th at 4:30pm. Students are advised to retain a copy of their final report for
   their records and study purposes. Late reports will be accepted with a 5% penalty per day up until
   April 15th. No reports will be accepted after April 15th.
3. This assignment carries a weight of 15% towards the final grade. The marking scheme is as follows:

                                                Technical Correctness 7
                                                          Organization 3
                                  Presentation, neatness, grammar, etc 5
                                                                Total 15

4. It is the students’ responsibility to work effectively in the lab team, complete the design, organize the
   report and present the solution in a logical and neat submission that another engineer could
   understand. Not every wire connecting any pin to another pin must be shown. Collect common
   connections into buses to reduce drawing complexity, but clearly indicate the connections proposed by
   your group. Reports should be typed, well organized and presented neatly.
5. Do not attempt to include all interfaces on the same drawing; complete schematic diagrams for each
   task separately as outlined on the following pages.

Background
A small embedded 8086-based microprocessor system is needed for a security system that requires 128
digital binary sensors and 128 display LEDs. The general architecture is shown in Figure 1. The purpose
of this assignment is to design the microprocessor, memory, and I/O subsystems (to the left of the dashed
line). The system is based on an 8086 with 8284A clock generator, 32Kbytes of SRAM, and 128Kbytes
of EPROM. A number of peripheral I/O devices are required as follows:
     An 8255 PPI for controlling the fire exits via 3 parallel ports (one for each floor)
     An 8253 Timer for generating a real-time clock for data logging
     An 8279 Keypad/Display Controller to run the control panel
     An 8251A Serial Communications Interface for communicating with a central server via RS232.

Figure 1: System architecture



                                8284A                          Peripheral
                                              8086                I/O          Keypad
                               Clock         Buffered            8255          Display
                                Reset          and               8253           Serial
                              Wait States    Latched             8279          Parallel
                                                                8251A




                               SRAM          EPROM                             128 Sensors
                                                           Sensor/LED
                              32Kbyte        128Kbyte          I/O
                                16K            64K       8x16bit Input Ports
                                 x              x       8x16bit Output Ports
                               16 bit         16 bit
                                                                                128 LEDs
    SYSC3601                          COURSE ASSIGNMENT                                 Winter 2011


Procedure
Task 1: Buffer and latch the 8086 microprocessor using standard components (’244, ’245, ’373) as
covered in the lecture. Connect an 8284A clock generator to the 8086 for 5MHz operation and reset
capability. Design a wait state generator offering 0-to-7 wait states and connect this to the 8284A.
Describe the operation of the wait state generator and how it will be set and activated to insert two wait
states when the microprocessor reads from EPROM, and to insert one wait state when the microprocessor
accesses SRAM. No wait states should be generated for IO operations.

Task 2: Design an interface (i.e. address decoding, data and control bus connections) for 32Kbytes of
SRAM organized as 16K by 16 bits using 6116 SRAM chips (2K by 8 bit each). The SRAM chip must
use 32K addresses somewhere in the range 21000H-2FFFFH (i.e. you must select an appropriate starting
address). Each 6116 has 8 data lines, and three active low control lines labelled WR , RD , and CS . Any
standard logic gate or decoder (2-to-4 or 3-to-8) may be used in your design. The complete address bus
must be decoded. When a 6116 is accessed, one wait state must be inserted in the read or write cycle to
accommodate the slower response time of these devices.

Task 3: Design address decoding circuitry and data and control bus connections for 128Kbytes of
EPROM organized as 64K by 16 bits using 27256 EPROM chips (32K by 8 bit each) such that the highest
byte address of EPROM resides at FFFFFH. Each 27256 has 8 data lines and two active low control lines
labelled OE and CE . Any standard logic gate or decoder (2-to-4 or 3-to-8) may be used in your design.
The complete address bus must be decoded. When EPROM is accessed, two wait states must be inserted
in the read cycle to accommodate the slower response time of these devices. For additional security, the
EPROM chips should only respond to accesses within the code segment (CS).

NOTE: All addresses from the top of SRAM to the bottom of EPROM are to be left for future expansion.
      (i.e. no partial decoding)

Task 4: Design address decoding circuitry and data control bus connections for the peripheral I/O system
using I/O-mapped-I/O at the addresses given in Table 1. Additional I/O may be required at a later date, so
your design must only allow the specified devices to be activated at the addresses given. Any standard
logic gate or decoder (2-to-4 or 3-to-8) may be used in your design. The complete I/O port address bus
must be decoded.

Table 1: Register addresses for peripheral I/O

                         Peripheral         Register          I/O Address (H)
                            8255       Port A                       9951
                                       Port B                       9953
                                       Port C                       9955
                                       Command Reg                  9957
                            8253       Counter 0                    9928
                                       Counter 1                    992A
                                       Counter 2                    992C
                                       Control Word Reg             992E
                            8279       Data Reg                     99ED
                                       Command Reg                  99EF
                           8251A       Data Reg                     99B6
                                       Command Reg                  99B8
    SYSC3601                          COURSE ASSIGNMENT                                 Winter 2011



Procedure (cont.)
Task 5: Design address decoding circuitry and data/control bus connections for the sensor/LED I/O
system using I/O-mapped-I/O. Each sensor is used to measure an event (e.g. glass break, door contact
open, motion detector). Each sensor is digital and in one of two states (1=event or 0=no event). Each
display panel LED is turned on by providing a logic high level to that LED, and is turned off by providing
a logic low level to that LED.

Sensors and corresponding LEDs are arranged in groups of 8 forming one byte of data that is read from
(input port) a group of sensors or written to (output port) a group of LEDs. Each 8-bit input/output port
pair is to have the same address. For example, sensors 0-7 are connected to an 8-bit input port which has
the same port address as the output port which is connected to LEDs 0-7. The same is true for sensors 8-15
and LEDs 8-15, etc.

I/O-mapped-I/O is to be used with port addresses running sequentially from A160H through A16FH. That
is, the port for switches/LEDs 0-7 is A160H, 8-15 is A161H, 16-23 is A162H, etc., and 120-127 is
A16FH. Sensors/LEDs can be read/written byte-wise (8-bits at a time) or word-wise (16 bits at a time).
Byte-wise access can occur at even or odd addresses depending on the group of sensors/LEDs to be
accessed. Any standard logic gate or decoder (2-to-4 or 3-to-8) may be used in your design. The
complete I/O address bus must be decoded.




Lab Report
The report must be neatly prepared and logically presented. Reports that are too messy to decipher will be
returned with a mark of zero. Include a title page that clearly identifies the name and student number of
each member of your lab group. Give a short introduction and then document your designs under the Task
headings given above. Include a discussion of your design under each Task.

								
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