VADA Regulator by mikesanye

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									                                               SOC Design : Paper Reviews

                            “Minimizing Ohmic Loss and Supply Voltage Variation
                              Using a Novel Distributed Power Supply Network”
                                                                     by M. Budnik and K. Roy
SOC Paper Reviews …




                                                         SSIT Mixed Signal Lab.
                                                         김규열, 박상균, 박윤식




                      SSIT Mixed Signal Lab.   May. 30. 2006      1
                      1. Abstract


                           IR and di/dt events may cause ohmic losses
                            and large supply voltage variations due to system parasitics.

                           Parallelism in the power delivery path is used to reduce ohmic loss
                            while decoupling capacitance is used to minimize the supply voltage
                            variation.
SOC Paper Reviews …




                           A novel, distributed power delivery and decoupling network is
                            introduced reducing the supply voltage variation magnitude by 67%
                            and the future ohmic loss by 15.9W using conventional processing
                            and packaging techniques in a 130nm technology node.

                           Proposed of “distributed power supply network (DPSN)”
                              - Reduction of Supply Voltage Variations
                              - Reduction in IR Event Ohmic Loss



                       SSIT Mixed Signal Lab.   May. 30. 2006   2
                      2. Introduction


                           These Days‟ Circumstances…
                             - As the operating voltage decreases and integration density increases,
                               more current is required to meet the growing power requirements.

                           In an IR event,
                            ohmic losses occur as current flows through the parasitic resistance of
                            the external voltage regulator module (VRM), the system‟s board,
SOC Paper Reviews …




                            and the microprocessor's package.

                           The ohmic losses in the power delivery path can be reduced by
                            delivering a microprocessor‟s input power at a higher voltage
                            and lower current.




                       SSIT Mixed Signal Lab.   May. 30. 2006   3
                      2. Introduction
SOC Paper Reviews …




                                                                               * Regulation Node :
                                                                                  designed ‘transform’ input power
                                                                                  from high input voltages
                                                                                  to required operating voltage



                           Step-down power conversion architecture for the integrated circuit
                             - to deliver the required operating voltage in a distributed fashion,
                             - to reduce the supply voltage variations
                               caused by changes in the operating current (di/dt events).



                       SSIT Mixed Signal Lab.   May. 30. 2006   4
                      2. Introduction

                           Conventional power delivery and decoupling network (PDDN)
                            - modeled as three decoupled loops (with 2nd-order system)




                                                                                           Third Loop
SOC Paper Reviews …




                                                                Second Loop   First Loop




                       SSIT Mixed Signal Lab.   May. 30. 2006         5
                      2. Introduction

                           In conventional PDDNs,
                            the inductance and capacitance values increase further away
                            from the microprocessor die.
                                      ƒRESONANT3 < ƒRESONANT2 < ƒRESONANT1

                                                                      where ƒRESONANT = 1 / (2π√(LC))
SOC Paper Reviews …




                           These three resonant frequencies
                                            the three proposed DPSN is composed of
                            correspond to Because superimposed
                                          the in switched capacitor voltage regulator
                            droops observed2:1the supply voltage
                                                 and a di/dt event
                            variation in response to the linear voltage regulator.
                                      The one provides high efficiency power conversion,
                             → as operating currents increase,the switching noise
                                               the other filters
                                           and of di/dt a fast increase.
                                the magnitudeenablesevents response to di/dt events.
                             → exacerbate the supply voltage variation.

                           Proposed DPSN can rapidly respond to di/dt events
                           and minimize the three supply voltage variation droops.

                       SSIT Mixed Signal Lab.   May. 30. 2006   6
                      2. Introduction

                           By providing distributed voltage regulation in proposed DPSN,
                             - Reduction in the supply voltage variation
                             - Minimizing the ohmic losses associated with IR events.


                           In this paper, we present a novel power delivery network which:
SOC Paper Reviews …




                                    Reduces future IR event ohmic loss by over 15W
                                    Reduces di/dt event voltage droop magnitude by 67%
                                    Reduces di/dt event voltage droop over time by 98%

                                    Uses a standard silicon CMOS fabrication process
                                    Uses standard microprocessor packaging and package
                                    mounted (CLSC) decoupling capacitors




                       SSIT Mixed Signal Lab.   May. 30. 2006   7
                       2. Introduction
                       Increased Noise Problem at High Speed Digital Package and System

                                                                                   Supply Voltage [V]




                                                                                                                                                            Allowable Maximum Power [W]
                                                            1.1V        1.0V                  0.9V          0.8V    0.7V       0.6V      0.5V
                             Clock Frequency [GHz]

                                                     8                                                                                                210


                                                     6                                                                                                190


                                                     4                                                                                                170
SOC Paper Reviews …




                                                     2                                                 Ref. International Technology Roadmap
                                                                                                           for Semiconductor 2001 (ITRS)
                                                                                                                                                      150

                                                     2001           2003           2005              2007               2009                   2011
                                                                                          Year

                            Increase of Clock Frequency
                            Increase of Maximum Power (Current)
                            Decrease of Supply Voltage


                            Loss of Noise Margin
                            Loss of Timing Margin (Degradation of Signal Waveform)
                         SSIT Mixed Signal Lab.                    May. 30. 2006          8
                       2. Introduction
                       Simultaneous Switching Noise (SSN)
                                                                                              V=VCC+DV

                                                                                              DI=DI1+ DI2+ …DIn
                             Common Power Supply

                                         DI1                     DI2                    DIn     L
                                H                    H                     H                          Parasitic Inductance
                                     1                     2                        n
                                L                    L                     L                     (due to Pins, Bond-wire, etc.)
SOC Paper Reviews …




                                                                                                L

                             Common Ground
                                                                                Chip


                                                                               DI        Increase of Maximum Power (Current)
                        Simultaneous Switching Noise (SSN) : DV = L
                                                                               Dt        Increase of Clock Frequency


                        SSN caused by simultaneous switching output buffers



                        SSIT Mixed Signal Lab.   May. 30. 2006         9
                       2. Introduction
                       Noise Problems caused by SSN
                                                                                                               Loss of Noise Margin
                      Power Line Fluctuation [V]


                                                   5.4
                                                                                                               Loss of Timing Margin
                                                   5.2                              SSN
                                                    5                                                                                                Data Skew

                                                   4.8       840-mV                                                                                  Data Jitter
                                                   4.6                                                         Increased Radiated Emissions
SOC Paper Reviews …




                                                         0            50             100        150
                                                                           Time [nsec]




                                                                                                                  Radiated Emission [dBuV/m]
                                                              Jitter & Skew                                                                    30
                                                                                                                                                         32.1dBmV/m@55.11MHz

                      VDD                                                                                                                      20
                                                                                                NMH        DVDD
                      VIH
                                                                           Signal Eye Pattern                                                  10
                      VIL
                                                                                                NML
                      VSS
                                                                                                           DVSS                                0
                                                                         T/2                                                                        50   100   150   200   250   300
                                                                       1/2fCLK                                                                           Frequency [MHz]

                                                   SSIT Mixed Signal Lab.       May. 30. 2006         10
                       2. Introduction
                       Function of Decoupling Capacitor
                                                                                                         10 nsec
                                      VCC                                 Input Condition




                                                                                            current
                                     GND

                                                                                                                    100mA
                                    Burst Current Flows
                                                 H                                                                 time
                                                                     V
                                                 L                                                    1 nsec
SOC Paper Reviews …




                                      VCC

                                     GND


                                    Burst Current Flows
                                                 H                   V
                                                 L




                                  These Inductance were screened out


                        SSIT Mixed Signal Lab.       May. 30. 2006   11
                      2. Introduction
                       Noise Reduction Method of SSN
                            – Discrete Decoupling Capacitor
                      Discrete Decoupling Capacitor on PCB            Low Inductance Capacitor on Package

                                                       Chip            Ball Grid Array Package                      Bulk Capacitor
                                                                        Ball Bonding
                                                                                                               VRM                      Ground

                                                                                                                                        Power

                                                    Wire           Package    Ball                      PCB
SOC Paper Reviews …




                              Chip
                                         DI        Bonding       P/G Network Bonding                P/G Network                       VRM




                      Decoupling Capacitor                     Decoupling Capacitor          Decoupling Capacitor                Bulk Capacitor
                           On Chip                                 On Package                     On PCB                          Near VRM

                          Low impedance path of current-flow at high frequency.

                          Screen out large inductance.

                          SSIT Mixed Signal Lab.     May. 30. 2006          12
                       2. Introduction
                       Equivalent P/G Decoupling Circuit

                                                                  Power Pin
                                                                              De-Cap
                                        IC Package
                                                  Ground Pin
                                                                                                          VRM,
                                                                                                          Power
                                     Ground Layer
                                                                                                          Supply

                                     Power Layer
SOC Paper Reviews …




                                                  LviaGND Lplane Lplane LviaGND LpadTrace
                                                                                                          VRM,PS
                                       Probing
                                                           Cplane Cplane                    Ldeca
                                        Point                                               Cdecap
                                                                                            p

                                                  LviaPWR Lplane Lplane LviaPWR LpadTrace

                                          ㆍLcap       : Inductance of Decoupling-Capacitor (=ESL, Cost)
                                          ㆍCcap      : Capacitance of Decoupling-Capacitor
                                          ㆍLplane    : Inductance of Power & Ground Plane (Position Issue)
                                          ㆍCplane     : Capacitance of Plane (Process, Cost)
                                          ㆍLpadTrace: Inductance of Mounting Pad-Trace (Minimum)
                                          ㆍLvia       : Inductance of Via

                        SSIT Mixed Signal Lab.    May. 30. 2006             13
                       2. Introduction
                       Interpretation of Resonance on a Z-Profile

                                                 Power Pin
                                                        De-Cap
                         IC Package                                                                           1.5nF, 8nH
                                 Ground Pin                                              VRM,                 → 46 MHz
                                                                                         Power                         λ/4 short-open
                        Ground Layer            100                                      Supply
                                                                                                                         Resonance
                        Power Layer
                                                       80
                                                                                                                                   TM10 TM11 TM20
                                        Power
                                                       60
SOC Paper Reviews …




                                                                            Z=1/jωC (for capacitance)
                         VRM            Decap                 Plane
                                                       40                    =jωL (for inductance)
                                            dB(_1nF)




                      8nH             2nH                                                                                       Plane C
                                                       20
                                                        500pF
                      22uF            1nF
                                                        0
                                                                                                               Decap C      Decap ESL
                                       Ground -20                                                             (+Plane C)   (+ Via, Plane)

                                                  -40 VRM capacitance                     VRM inductance
                                                                                         + Plane inductance
                                                  -60
                                                                            22uF, 8nH
                                                                            → 380 kHz                              1.5nF, 2nH
                                                  -80                                                              → 92 MHz
                                                                      1E5                1E6            1E7            1E8              1E9 freq, Hz
                         SSIT Mixed Signal Lab.             May. 30. 2006           14
                                   2. Introduction
                              Control P/G Impedance

                                                   10
                                                        3        What can we change to control P/G impedance?
                                                                                                                                 P/G Plane Resonance Effects
                                                        2
                                                   10


                                                        1
                                                   10                                                 Lcap(+ Lvia+ LpadTrace)
                      Impedance (Z11) [Ohm]




                                                                     Cdecap(+ Cplane )
SOC Paper Reviews …




                                                                                                                                 CPlane
                                                                                                                                          Lvia, Lplane
                                                        0
                                                   10


                                                        -1
                                                   10


                                                        -2
                                                   10


                                                        -3
                                                   10
                                                                 6                            7                              8                       9
                                                            10                           10       Frequency [Hz]        10                      10



                                              SSIT Mixed Signal Lab.         May. 30. 2006              15
                      2. Introduction
                       Decoupling-Cap Design


                                                             Power Pin
                                                                         De-Cap
                                     IC Package
                                                Ground Pin
                                                                                                   VRM,
                                                                                                   Power
                                  Ground Layer
                                                                                                   Supply
SOC Paper Reviews …




                                  Power Layer

                                                LviaGND Lplane Lplane LviaGND LpadTrace
                                                                                                   VRM,PS
                                    Probing
                                                        Cplane Cplane                     Ldeca
                                     Point                                                Cdecap
                                                                                          p

                                                LviaPWR Lplane Lplane LviaPWR LpadTrace


                                    Increase # of Via, Multiple Vias with Polarity

                                    Reduce the Height of Power/Ground Planes, Add Area Fill with Opposite Voltage
                                                                 Minimize pad-Trace Length
                                                                      Use low inductance Decoupling capacitor
                       SSIT Mixed Signal Lab.    May. 30. 2006            16
                           2. Introduction
                            Limitation of Decoupling Capacitor on PCB
                                                              nF            mF                                            Capacitance
                                                           Decoupling        VRM
                                       Chip
                                                            Capacitor


                      kHz             Ground                                                                    j                   j
                                                                                                  jLVRM            jLDECAP 
                                       Power                                                                  CVRM              CDECAP


                                                                                                                j                     j
                                                                                                jLDECAP               jLVRM 
                                                                                                             CDECAP                CVRM
                      MHz
                                      Ground
SOC Paper Reviews …




                                                                                                                j                        j
                                                                                                jLDECAP               jLPLANE 
                                       Power                                                                 CDECAP                  CPLANE

                                                                                                Limitation of Discrete Decoupling Capacitor

                                                                                                                j                        j
                                                                                                jLPLANE               jLDECAP 
                      GHz             Ground                                                                 CPLANE                  CDECAP
                      Frequency




                                       Power



                                                            1nH             10nH                                           Inductance

                                   Inherent large parasitic inductance of discrete capacitor
                                   Inductance given by power/ground plane.
                                   Large inductance given by “Via” and “Mount Pad”
                                  SSIT Mixed Signal Lab.   May. 30. 2006    17
                      3. Conventional Power Delivery and Decoupling Network



                           The maximum supply voltage variation
                            magnitude increases as the duration of
                            the 100A di/dt event decreases.
SOC Paper Reviews …




                           Inverse relationship
                            between decoupling capacitor die area
                            and supply voltage variation



                                                                     * The maximum first droop magnitude
                                                                       for several values of CDIE



                       SSIT Mixed Signal Lab.   May. 30. 2006   18
                      3. Conventional Power Delivery and Decoupling Network

                           To quantify the amount of voltage droop over time,
                            we propose a new metric, VNS (Volt-ns).

                           The VNS value of the supply voltage
                            variation is found by integrating
                            the negative area of the voltage droops.
SOC Paper Reviews …




                           If repeated operating current transients
                            occur near the first loop resonant
                            frequency, larger supply voltage
                            variations can arise.

                           It will continue as long as the periodic
                           operating current transients persist,
                           if this variation is occurring
                           faster than a VRM can respond

                       SSIT Mixed Signal Lab.   May. 30. 2006   19
                      3. Conventional Power Delivery and Decoupling Network

                           Between di/dt events,
                            ohmic loss occurs in all the elements of a PDDN power delivery path.
SOC Paper Reviews …




                           Sum of Ohmic Loss in Conventional PDDN is 13.6W

                           In 2016, We predicted that it results in 49.5W.
                             - based on microprocessor operating current to 248A
                             - delivered at 0.8V
                             - conventional PDDNs efficiency is near 80%

                                       PLOSS = PD * (1-η)/η = 49.5W


                       SSIT Mixed Signal Lab.   May. 30. 2006   20
4.Distributed Power Supply Network
 Why Power-Supply ICs? “to regulate”
     If a regulator isn‟t used

     varying battery voltage                    varying current


               RBAT




                Battery                         Portable equipment

  SSIT Mixed Signal Lab.   May. 30. 2006   21
4.Distributed Power Supply Network
 Why Power-Supply ICs? “to regulate”
      If a regulator is used

varying battery voltage                                 RREG        varying current

                                     VIN                 VOUT

        RBAT



                                            RREG≪RBAT




          Battery                           Regulator           Portable equipment

   SSIT Mixed Signal Lab.   May. 30. 2006      22
4.Distributed Power Supply Network
  What Type of Power-Supply ICs?
   1. Linear Regulator




 Steps down and regulates
 Small size in Potable design, but may be larger w/ heat-sinking
 Contain no switching elements and then, little noise


   SSIT Mixed Signal Lab.   May. 30. 2006   23
4.Distributed Power Supply Network
   What Type of Power-Supply ICs?
    2. Switching Regulator


a) Step down




b) Step up




c) Inverting



    SSIT Mixed Signal Lab.   May. 30. 2006   24
4.Distributed Power Supply Network
 What Type of Power-Supply ICs?
  2. Switching Regulator
        The Charge-Transfer Process




 How can we transfer a finite amount of charge efficiently
 without loss, from Ci to Cf, and from Cf to Co ?
  SSIT Mixed Signal Lab.   May. 30. 2006   25
4.Distributed Power Supply Network
 Comparison between Linear and Switch-mode Regulators
                                      Linear                             Switching

      Function                Only steps down                 Steps up, down, or inverts

     Efficiency                Low to medium                                 High

    Waste heat                         High                                  Low

    Complexity                         Low                           Medium to high

         Size                 Small to medium                               Large*

         Cost                          Low                           Medium to high

   Ripple/Noise                        Low                           Medium to high

 * Larger than linear at low power, but smaller at power levels for which linear requires a heat sink

  SSIT Mixed Signal Lab.   May. 30. 2006         26
4.Distributed Power Supply Network

 In this paper, proposing the DPSN methodology
 How the voltage regulation of each distributed
 nodes implemented?
 2:1 Switched Capacitor Linear Voltage Regulator
 (SCLVR)
     Providing high efficiency power conversion
     Filtering the switching noise
     Fast response to di/dt events



  SSIT Mixed Signal Lab.   May. 30. 2006   27
4.Distributed Power Supply Network

 Proposed 2:1 Switched Capacitor Linear Voltage
 Regulator (SCLVR)
                                                1.0V          1.0V
  2.0V

                                                       1.5V




                                                       2.0V
            2.5V




  SSIT Mixed Signal Lab.   May. 30. 2006   28
4.Distributed Power Supply Network

 Differences between Conventional regulator and
 SCLVR
  1. Use a single, external reference voltage to all the
     distributed regulator nodes on the die
      Eliminating a consistent vref replica
  2. Use an external “high” gate voltage to the control block
     to increase the linear voltage regulator current drive




  SSIT Mixed Signal Lab.   May. 30. 2006   29
4.Distributed Power Supply Network

 Implementation of a simple DPSN in this paper
   130nm technology
   23 SCLVR nodes capable of each sourcing 4.39A
   M1~M4 transistor „w/ 2.5V, thick oxide MOSFET‟
   M5 transistor „w/ 1.5V, thin oxide MOSFET‟
        Dielectric breakdown due to gate leakage w/ high gate biasing
        SiO2 thickness > 1.5nm
        Dielectric failure rate<100PPM@over 10 years,125C,2.5 V
   M1~M5 area O/H ~ 0.27cm2 but, Compensated by a CDIE
     reduction and External power network is same with the
     conventional PDDN

  SSIT Mixed Signal Lab.   May. 30. 2006   30
 4.Distributed Power Supply Network
    Limitations to oxide thickness reduction
       As tox is reduced, the gate current is exponentially increased
                                                 Bulk resistivity ~ 1015Ω
                                                 dielectric breakdown strength ~ 107
                                                V/cm ( ~1V/nm)
                                                 Si-to-SiO2 Eg ~ 3.1eV
Tunneling electron
                            3.1eV     4.05eV
                                                cf) Si-to-Vacuum Eg ~4.05eV
                                                 And the gate leakage current is
                                                controlled by Quantum mechanical
                                                Tunneling(FN tunneling, direct tunn-
                                                eling)
                                                 tox<4nm, the direct tunneling current
                                                increases exponentially by about one
                                                order of magnitude for every 0.2~0.3nm
           * NMOS w/ P-type substrate
                                                reduction
                                                       Performance decreases!!
                                                     Power consumption increases!!
       SSIT Mixed Signal Lab.   May. 30. 2006   31
4.Distributed Power Supply Network
 DPSN Test chip

                                                      VIN


                                           Reduced CDIE?




                                                           VOUT




  SSIT Mixed Signal Lab.   May. 30. 2006   32
5.Reduction of Supply Voltage Variation
 VNS(Volts-ns)Comparison between PDDN and DPSN



                                   -3.53VNS
                                                      -9.99VNS




                    Fig. DPSN w/ VMID=1.05V vs. Conventional PDDN



  SSIT Mixed Signal Lab.   May. 30. 2006      33
5.Reduction of Supply Voltage Variation
 Performance of DPSN w/ VIN=2.5V, 10MHz switching clock




                                             -0.174VNS

                                           62mV
                                                          -9.99VNS


                                              Voltage variation 67% improved!!
                                           186mV    VNS 98% improved!!



                               Fig. DPSN vs. Conventional PDDN

  SSIT Mixed Signal Lab.   May. 30. 2006      34
5.Reduction of Supply Voltage Variation
 How reducing VMID damages the DPSN‟s ability?




                                           Unable to regulate Op voltage w/ VMID=1.1V




                     Fig. DPSN Supply Voltage Variation vs. VMID
  SSIT Mixed Signal Lab.   May. 30. 2006       35
 6.Reduction in IR Event Ohmic Loss
   Power Supply and Power Dissipation – term years




                                                        *
* In 2016, microprocessors are expected to consume 198W of power (248A at 0.8V).

     SSIT Mixed Signal Lab.   May. 30. 2006   36
6.Reduction in IR Event Ohmic Loss
 Power Dissipation @ Dynamic
     Ohmic Loss
                            PLoss  PD (1   ) / 
     Conventional PDDN Ohmic Loss( Efficiency 80%)
                  PLoss , PDDN  198W (1  0.8) / 0.8  49 .5W
     Proposed DPSN Ohmic Loss( Efficiency 90%)
             PLoss , DPSN  198W (1  0.9) / 0.9  22 .0W
        Additional switching Loss at DPSN 11.6W
     Power Savings
            PSavings  ( PLoss , PDDN  PLoss , External, DPSN )  PLoss , DPSN
            PSavings  (49 .5W  11 .6W )  22 .0W  15 .9W


  SSIT Mixed Signal Lab.   May. 30. 2006     37
6.Reduction in IR Event Ohmic Loss
 Additional Leakage Power Loss Reduction
     The reduction of oxide thickness in advanced nano-
     technology, however, also significantly increases the
     tunneling current and leakage power of thin-oxide
     capacitors
     10W/175nF(1.5nm „thin‟ Tr. + 2.5nm „thick‟ Tr.)
        PDDN : CDIE=1μF, 57.1W, DPSN : CDIE=500nF,
           28.6W  ∴28.6W Savings
 Die area
     CDIE from 1μF to 500nF  0.451cm2 reduction
     Offset the 0.27cm2 area added by M1-M5 transistors

  SSIT Mixed Signal Lab.   May. 30. 2006   38
7.Conclusion


    Purpose of
   “distributed power supply network (DPSN)”

         Reduction of Supply Voltage Variations
         Reduction in IR Event Ohmic Loss




  SSIT Mixed Signal Lab.   May. 30. 2006   39

								
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