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Title: Electrostatic discharge (ESD) technology benchmarking strategy for
evaluating ESD robustness of CMOS technologies
Author: Voldman, S.
Anderson, W.
Ashton, R.
Chaine, M..
Duvvury, C..
Maloney, T.
Worley, E.
Conference Name: Integrated Reliability Workshop Final Report, 1998 IEEE
International
Year:1998
Abstract: This paper describes an ESD technology benchmarking strategy for
evaluating the ESD robustness of a semiconductor technology. The strategy
consists of a set of CMOS “building block” test structures, a
matrix of these test structures, electrical characterization parameters, ESD
metrics, a standardized failure criteria, and an extraction and testing procedure

Title: Design methodology and optimization of gate-driven NMOS ESD
protection circuits in submicron CMOS processes
Author: Chen, J. Z.
Amerasekera, E. A.
Duvvury, C.
Journal: Electron Devices, IEEE Transactions on
Year:1998
Abstract: This paper describes the design methodology for gate driven NMOS
ESD protection in submicron CMOS processes. A new PNP Driven NMOS
(PDNMOS)-protection scheme is presented. Without requiring any additional
process steps or introducing any additional impedance in signal path, the
PDN-MOS is effective even for small analog/mixed-signal designs. SPICE
simulations are used to optimize the design. High ESD performance of the
PDNMOS protection in both nonsilicided and silicided submicron processes is
demonstrated in this work

Title: Modeling MOS snapback and parasitic bipolar action for circuit-level ESD
and high-current simulations
Author: Amerasekera, A.
Mi-Chang, Chang
Duvvury, C.
Ramaswamy, S. A. Ramaswamy S..
Journal: Circuits and Devices Magazine, IEEE
Year:1997
Abstract: The design and optimization of ESD protection circuits is greatly
enhanced by the ability to perform circuit-level simulations of the protection
circuits and the I/O buffers. Most available simulators do not cover the high
current region of the circuit operation, but still enable an approximate analysis
to be made of the behaviour under ESD conditions. In this article, a description
of the behaviour of the MOS device in the high current regime is presented
together with the model equations governing that behaviour. The equations
have been implemented into a SPICE circuit simulator, and the experimental
and simulation results are given. A simple parameter extraction methodology
is presented that uses the terminal currents from a single MOS DC I-V curve to
obtain all the MOS and bipolar parameters required for the model

Title: Device integration for ESD robustness of high voltage power MOSFETs
Author: Duvvury, C.
Rodriguez, J.
Jones, C.
Smayling, M. A. Smayling M..
Conference Name: Electron Devices Meeting, 1994. Technical Digest.,
International
Year:1994
Abstract: The ESD robustness of a power MOSFET device is addressed in this
paper. It is shown that by a novel device integration of the power output
transistor with SCR, the ESD performance can be improved from less than 2
kV to greater than 6 kV. This is accomplished with no impact on the transistor
performance or its application in circuit design

Title: Circuit-level electrothermal simulation of electrical overstress failures in
advanced MOS I/O protection devices
Author: Diaz, C. H.
Sung-Mo, Kang
Duvvury, C.
Journal: Computer-Aided Design of Integrated Circuits and Systems, IEEE
Transactions on
Year:1994
Abstract: Previous work on electrothermal simulation using network analysis
techniques has been of limited use due to the lack of avalanche breakdown
modeling capability and the models to efficiently describe the temperature
dynamics. Particularly, simulation of electrical overstress (EOS) and
electrostatic discharge (ESD), which are important threats to

Title: ESD: a pervasive reliability concern for IC technologies
Author: Duvvury, C.
Amerasekera, A..
Journal: Proceedings of the IEEE
Year:1993
Abstract: Several aspects of ESD are described from the point of view of the
test, design, product, and reliability engineering. A review of the ESD
phenomena along with the test methods, the appropriate on-chip protection
techniques, and the impact of process technology advances from CMOS to
BiCMOS on the ESD sensitivity of IC protection circuits are presented. The
status of understanding in the field of ESD failure physics and the current
approaches for modeling are discussed

Title: TCAD Methodology for Design of SCR Devices for Electrostatic
Discharge (ESD) Applications
Author: Salcedo, J. A.
Liou, J. J.
Zhiwei, Liu
Vinson, J. E.
Journal: Electron Devices, IEEE Transactions on
Year:2007
Abstract: Realization of on-chip electrostatic discharge (ESD) protection
requires extensive technical experience and know-how. A technology
computer-aided design (TCAD) methodology aimed to assist in the design and
implementation of robust ESD devices is developed and presented. The
methodology provides a systematic and practical means for the evaluation and
optimization of ESD devices in a simulation environment. Advanced
silicon-controlled-rectifier devices are considered to illustrate the approach,
and experimental data measured from these devices are also included in
support of the TCAD development

Title: Capacitance investigation of diodes and SCRs for ESD protection of high
frequency circuits in sub-100nm bulk CMOS technologies
Author: Li, Junjun
Gauthier, Robert
Chatty, Kiran
Mitra, Souvick A. Mitra Souvick
Hongmei Li, A. Hongmei Li
Xingle Wang, A. Xingle Wang
Halbach, Ralph A. Halbach Ralph
Seguin, Christopher A. Seguin Christopher
Conference Name: 29th Electrical Overstress/Electrostatic Discharge
Symposium (EOS/ESD), 2007. EOS/ESD
Year:2007
Abstract: S-parameter test structures show total capacitances per perimeter of
ESD diodes increased from ∼0.42fF/μm in 90nm
technologies to ∼0.7fF/μm in 65nm and 45nm technologies.
To achieve lower capacitances for high frequency circuits, layout and process
optimization are needed. SCR devices from a 45nm technology show
∼0.32fF/μm and can be used for circuit applications with
stringent capacitance requirement. Two different BEOL wiring schemes are
investigated for optimized metal coupling capacitance.

Title: Frequency-Domain Measurement Method for the Analysis of ESD
Generators and Coupling
Author: Jayong, Koo
Qing, Cai
Muchaidze, G.
Martwick, A. A. Martwick A.
Kai Wang, A. Kai Wang
Pommerenke, D. A. Pommerenke D..
Journal: Electromagnetic Compatibility, IEEE Transactions on
Year:2007
Abstract: A method for analyzing electrostatic discharge (ESD) generators and
coupling to equipment under test in the frequency domain is proposed. In ESD
generators, the pulses are excited by the voltage collapse across relay
contacts. The voltage collapse is replaced by one port of a vector network
analyer (VNA). All the discrete and structural elements that form the ESD
current pulse and the transient fields are excited by the VNA as if they were
excited by the voltage collapse. In such a way, the method allows analyzing
the current and field-driven linear coupling without having to discharge an ESD
generator, eliminating the risk to the circuit and allowing the use of the wider
dynamic range of a network analyzer relative to a real-time oscilloscope. The
method is applicable to other voltage-collapse-driven tests, such as electrical
fast transient, ultrawideband susceptibility testing but requires a linear coupling
path.

Title: Analysis of HBM-ESD current rise time and its deciding factors
Author: Zhou, Feng
Huang, Jiusheng
Gao, Yougang
Liu Sulin, A. Liu Sulin
Wang Xiqing, A. Wang Xiqing
Wang Langfeng, A. Wang Langfeng..
Confernce Name: Environmental Electromagnetics, The 2006 4th Asia-Pacific
Conference on
Year:2007
Abstract: Circuit model of ESD test circumstance is established. By Inverse
Laplace transform, analytical expression of current is got. Then we obtain
simulation of current rise time (tr) under different combination of circuit
parameters. A few fitted polynomials that describe the relationship of tr to
these parameters are got, whose accuracy is also analyzed.
Title: ESD Generator Analyzed by Transmission Line Theory
Author: Liu, Suling
Huang, Jiusheng
Gao, Yougang
Wangxiqin, A. Wangxiqin
Zhou Feng, A. Zhou Feng
Wang Langfeng, A. Wang Langfeng
Confernce Name: Environmental Electromagnetics, The 2006 4th Asia-Pacific
Conference on
Year: 2006
Abstract: In this paper, the transmission line theory was used to analyze the
electrostatic discharge (ESD) transient process. Finite-difference time-domain
(FDTD) method is used to simulate the discharge current being prescribed in
the IEC 61000-4-2. The factors influencing the current parameters were
examined, the suggestion for designing ESD generator was put forward.

Title: A new low-parasitic polysilicon SCR ESD protection structure for RF ICs
Author: Haolu, Xie
Haigang, Feng
Rouying, Zhan
Wang, A. A. Wang A.
Rodriguez, D. A. Rodriguez D.
Rice, D. A. Rice D.
Journal: Electron Device Letters, IEEE
Year: 2005
Abstract: Robust low-parasitic electrostatic discharge (ESD) protection is
highly desirable for RF ICs. This letter reports design of a new low-parasitic
polysilicon silicon controlled rectifier (SCR) ESD protection structure designed
and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology.
The concept was verified by simulation and experiment with the results
showing that the new structure has much lower parasitic capacitance (C/sub
ESD/) and higher F-factor than that of other ESD protection devices. A small
polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high
human body model ESD protection of 3.2 kV while featuring a high F-factor of
/spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR
ESD protection structure seems to be an attractive solution to high-GHz RF
ICs.

Title: Electrostatic discharge (ESD)
Author: Sadiku, M. N. O.
Sadiku, M. N. O.
Akujuobi, C. M.
Journal: Potentials, IEEE
Year: 2004
Abstract: Electrostatic discharge (ESD) refers to the sudden transfer
(discharge) of static charge between objects at different electrostatic potentials.
ESD belongs to a family of electrical problems known as electrical overstress
(EOS). ESD poses a serious threat to electronic devices, such as microcircuits,
transistors, and diodes, and affects the operation of the systems that contain
those devices. Most electronic companies regard all semiconductor devices as
ESD sensitive because of the damage ESD can cause. For this reason, ESD is
a major concern in the microelectronic and electronic industry in manufacture
and testing. ESD concerns also exist in nonelectronic components such as
disk drives, magnetic recording heads, and sensors. The article describes the
causes of ESD, its damaging effects and how the effects can be prevented or
minimized.

Title: Using device simulations to optimize ESD protection circuits
Author: Fankhauser, B.
Fankhauser, B.
Deutschmann, B.
Conference Name: Electromagnetic Compatibility, 2004. EMC 2004. 2004
InternationalSymposium on
Year: 2004
Abstract: As integrated circuits are getting more and more complex, they are
becoming increasingly vulnerable to transient disturbances (e.g. to
electrostatic discharges, ESD). The development approaches for on-chip ESD
protection devices often have a very experimental character: ESD designers
make use of trial-and-error procedures to evaluate many variations of
protection structures. This methodology is very time-consuming, as it can
require several redesigns to find proper ESD protection devices for a given
process technology. Also, from one process generation to the next, already
well-established ESD structures may completely change their ESD behavior.
Now, more sophisticated design approaches make use of TCAD-based
techniques. Simulations of ESD circuits provide a deeper understanding of the
functionality of their protection behavior. In this paper we show how such
simulation techniques have been successfully used to design an efficient
trigger-circuit for SCR, a specific class of very powerful ESD protection
devices.

Title: An express diagnostic method for ESD simulators and standardized ESD
test stations
Author: Kocharyan, V.
Kocharyan, V.
Tolman, D.
Conference Name: Electromagnetic Compatibility, 2003 IEEE International
Symposium on
Year: 2003
Abstract: The management of ESD simulators and standardized ESD test
stations to assure quality test results continues to be a major concern for test
houses. Early detection of malfunctioning ESD equipment is possible if a
day-to-day check is performed. The standard system for verification of ESD
simulators is large, expensive and not practical for an everyday check. This
paper describes the express diagnostic method aimed to locate the problems
with either the ESD simulator or the test station. A 100MHz....500MHz
bandwidth oscilloscope can be used to measure the quasi-electrostatic field of
the horizontal coupling plane after the package of discharges has been applied.
The malfunction of an ESD simulator and/or test station is discovered as a
deviation from the baseline measurements, which are taken immediately after
calibration. This method exposes any changes of the indicated discharge
voltage or the horizontal coupling plane bleeder resistor impedance as well as
changes in the discharge networks of ESD simulators. The oscillograms and
the statistical analysis of data are presented in this paper, which support the
claims that this method can assists in detection of potential problems of ESD
equipment.

Title: A systematic study of ESD protection structures for RF ICs
Author: Guang, Chen
Haigang, Feng
Wang, A.
Conference Name: Radio Frequency Integrated Circuits (RFIC) Symposium,
2003 IEEE
Year: 2003
Abstract: We report the first systematic investigation of various ESD protection
structures, e.g., diodes, ggNMOS, gcNMOS, ggPMOS, SCR and multi-mode
SCR's in a 0.35 /spl mu/m production BiCMOS technology, for RF ICs up to
100 GHz by mixed-mode ESD simulation. Typical circuit parameters for RF
ICs, e.g., parasitic resistances, capacitances, noise figures and S-parameters
were studied. The comparison study suggests that compact SCR-type
structures and diode strings may be solutions to RF ESD protection.

Title: Bonding-pad-oriented on-chip ESD protection structures for ICs
Author: Feng, H.
Zhan, R.
Chen, G.
Wu, Q. A. Wu Q.
Guang, X. A. Guang X.
Xie, H. A. Xie H.
Wang, A. A. Wang A.
Conference Name: Circuits and Systems, 2003. ISCAS '03. Proceedings of the
2003 International Symposium on
Year: 2003
Abstract: Several bonding-pad-oriented ESD protection structures, including a
ggCMOS, an LVSCR and an all-direction ESD structures are reported,
implemented in commercial 0.35 /spl mu/m CMOS and 0.6 /spl mu/m BiCMOS.
Measurements agree with simulations well. HBM ESD zapping tests passed 2
kV, 4.4 kV and 14 kV, respectively. The structures are suitable ESD protection
solutions for RF, mixed-signal and high-pin-count ICs.

Title: Test structures and test methodology for developing high voltage ESD
protection
Author: Concannon, A.
Concannon, A.
Vashchenko, V.
ter Beek, M.
Hopper, P. A. Hopper P..
Conference Name: Microelectronic Test Structures, 2003. International
Conference on
Year: 2003
Abstract: In this work, test structures and a test methodology is developed to
evaluate proposed silicon controlled rectifier based ESD clamps in all modes
of operation. TCAD analysis is used to identify possible ESD clamp structures.
Standard ESD testing on the stand-alone test structures is used to screen the
ESD capability of the candidate clamps. The transmission line pulse technique,
with variation in pulse rise time, is used to evaluate the dynamic triggering
characteristics of a snapback based clamp and select an appropriate clamp for
fast switching applications. Finally, a very efficient local ESD clamp based on a
bipolar-silicon controlled rectifier in a 24 V complementary power BiCMOS
smart power process is presented.

Title: RC-SCR: very-low-voltage ESD protection circuit in plain CMOS
Author: Feng, H.
Zhan, R.
Wu, Q.
Chen, G. A. Chen G.
Wang, A. Z. A. Wang A. Z...
Journal: Electronics Letters
Year: 2002
Abstract: A simple, novel RC-coupled very-low-voltage silicon controlled
rectifier, electrostatic discharge protection circuit is reported, implemented in
0.35 μm CMOS, which is confirmed by transient electrostatic discharge
simulation and measurement, and results in a very low triggering of 7 V, a 60%
reduction over traditional silicon controlled rectifiers
Title: RC-SCR: a novel low-voltage ESD protection circuit with new triggering
mechanism
Author: Feng, H.
Zhan, R.
Wu, Q.
Chen, G. A. Chen G.
Wang, A. Z. A. Wang A. Z...
Conference Name: Circuits and Systems, 2002. APCCAS '02. 2002
Asia-Pacific Conference on
Year: 2002
Abstract: Several techniques exist to realize low triggering of SCR
(Si-controlled rectifier) ESD (electrostatic discharging) protection structures in
CMOS technologies. This paper reports a novel RC-SCR (RC-coupled SCR)
ESD protection circuit using a new RC-coupling-based triggering mechanism
to further reduce triggering voltage. Implementation in a commercial 0.35/spl
mu/m CMOS process results in a very low triggering of 7V, representing a 28%
further reduction from existing low-triggering-voltage SCR ESD protection
designs.

Title: Simulation models of ESD event in ICs
Author: Jiang, Lei
Yang, Xing
Wang, Jiaji
Conference Name: Solid-State and Integrated-Circuit Technology, 2001.
Proceedings. 6th International Conference on
Year: 2001
Abstract: ESD protection becomes more and more prevalent with the
development of deep sub-micron technology. ESD simulation with right models
can reduce the design and test cycle of ESD protection circuit, and optimize for
ESD robustness as well as device performance. Several simulation models
and practical examples are described to show the application of ESD
simulation in this article. Integrated models that combine process, circuit and
device simulation are the trends of development.

Title: In-situ spin stand ESD testing of giant magnetoresistive (GMR) recording
heads
Author: Wallash, A.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings 2000
Year: 2000
Abstract: An experimental set-up for automated in-situ ESD testing of giant
magnetoresistive (GMR) heads flying on a spin stand is described. The effects
of human body model (HBM) ESD current transients on three different GMR
head designs are reported. Results show that exposure to HBM ESD can
seriously degrade the quality and shape of the cross-track profiles. Magnetic
instability was also seen to increase with increasing ESD damage. It is
concluded that ESD damage results in serious and undesirable changes in the
micromagnetic response of GMR sensors and can result in increased
magnetic instability

Title: HDA-level ESD testing of giant magnetoresistive (GMR) recording heads
Author: Nordin, D.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings 2000
Year: 2000
Abstract: The drive-level electrostatic discharge (ESD) behavior of a recent
model of a desktop disk drive is discussed. ESD events are simulated up to 30
kV using an ESD gun (IEC-801). The drives were evaluated at the final
assembly level. The head disk assemblies (HDAs) were equipped with GMR
heads and single ended preamplifiers. In a manner similar to evaluations of
head stack assemblies (Wallash, 1999), the head disk assemblies were
stressed using an ESD gun at various strategic points of the drive. The printed
circuit boards were in place when directing ESD events to the base and
removed to address the motor pins. A quasi-static tester (QST) was employed
to evaluate the GMR head condition as described by the signal amplitude,
resistance and pinned layer orientation. The QST was able to evaluate the
GMR condition without any disassembly of the drive. Analyses of the GMR
condition before and after ESD stress are discussed

Title: TLP measurements for verification of ESD protection device response
Author: Hyatt, H.
Harris, J.
Alanzo, A.
Bellew, P. A. Bellew P.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings 2000
Year: 2000
Abstract: Transmission line pulsers, commonly known as TLPs, have been
used for many years to calibrate diagnostics, and provide precise high-voltage
and high-current waveforms. The pulsers have been used to qualify the ESD
response of many ESD protection circuits and devices (Rector and Hyatt, 1998;
Gieser and Egger, 1996; Maloney and Khurana, 1985). TLP applications cover
a wider range of uses beyond estimating the ESD susceptibility of device level
protection circuits. TLPs have been used to certify many ESD suppression
devices including: device level ESD protection circuits, metal oxide varistors
(MOV), Transorbs, composite voltage variable materials (VVM), diodes, spark
gaps, and occasionally, even capacitors and resistors. This paper describes a
simplified, yet general, TLP circuit and method called time domain
transmission (TDT) mode testing. The method differs from and is compared to
time domain reflection (TDR) mode measurement techniques

Title: TLP measurements for verification of ESD protection device response
Author: Wang, Ying
Chemerys, V.
Xiao, Dongsheng
Conference Name: Pulsed Power Conference, 1999. Digest of Technical
Papers. 12th IEEE International
Year: 1999
Abstract: In accordance with the characteristics of the basic existing
electromagnetic pulse (EMP) sources, such as the lightning electromagnetic
pulse (LEMP), nuclear electromagnetic pulse (NEMP) and electrostatic
discharge electromagnetic pulse (ESD EMP), a new type of EMP simulator,
the multi-function EMP simulator is presented. It consists of three fundamental
parts which can be moved along the rails on the ground. These parts can be
combined together or divided each other according to need. It is possible to
simulate every mentioned kind of EMP in separate or simultaneously. The
EMP simulator described here was tested experimentally. It has such
advantages as multifunction performance, low cost and simple configuration

Title: A study of diode protection for giant magnetoresistive recording heads
Author: Wallash, A.
Wenwei, Wang
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings, 1999
Year: 1999
Abstract: ESD testing of giant magnetoresistive (GMR) heads with diodes is
described. While the use of diodes did increase the magnetic and resistance
failure voltages of the GMR head, the magnetic failure voltage was increased
much less than the resistance failure voltage. This results in an unfortunate
side effect, which is to dramatically increase the range over which magnetic
damage occurs without a resistance change. This problem was especially
clear for the case of two diodes in series. The current flow through the GMR
head and diode were measured and agreed with SPICE circuit simulation
results. The difference between magnetic and resistance protection is due to
the nonlinear clamping behavior of the diode. It is concluded that serious
magnetic damage will be the predominant failure signature for GMR heads
with ESD protect diodes

Title: Design methodology and optimization of gate-driven NMOS ESD
protection circuits in submicron CMOS processes
Author: Chen, J. Z.
Amerasekera, E. A.
Duvvury, C.
Journal: Electron Devices, IEEE Transactions on
Year: 1998
Abstract: This paper describes the design methodology for gate driven NMOS
ESD protection in submicron CMOS processes. A new PNP Driven NMOS
(PDNMOS)-protection scheme is presented. Without requiring any additional
process steps or introducing any additional impedance in signal path, the
PDN-MOS is effective even for small analog/mixed-signal designs. SPICE
simulations are used to optimize the design. High ESD performance of the
PDNMOS protection in both nonsilicided and silicided submicron processes is
demonstrated in this work

Title: Modeling MOS snapback and parasitic bipolar action for circuit-level ESD
and high-current simulations
Author: Amerasekera, A.
Mi-Chang, Chang
Duvvury, C.
Ramaswamy, S.
Journal: Circuits and Devices Magazine, IEEE
Year: 1997
Abstract: The design and optimization of ESD protection circuits is greatly
enhanced by the ability to perform circuit-level simulations of the protection
circuits and the I/O buffers. Most available simulators do not cover the high
current region of the circuit operation, but still enable an approximate analysis
to be made of the behaviour under ESD conditions. In this article, a description
of the behaviour of the MOS device in the high current regime is presented
together with the model equations governing that behaviour. The equations
have been implemented into a SPICE circuit simulator, and the experimental
and simulation results are given. A simple parameter extraction methodology
is presented that uses the terminal currents from a single MOS DC I-V curve to
obtain all the MOS and bipolar parameters required for the model

Title: A tutorial and an experimental demonstration of how ESD is generated
and its impact on electronic devices
Author: Issa, M.
Conference Name Southcon/94. Conference Record
Year: 1994
Abstract: Summary form only given, as follows. It has been recognized since
the 1960s that many devices such as metal oxide semiconductors,
microprocessors, bipolar devices, operational amplifiers, and even discrete
components are susceptible to electrostatic discharge (ESD). Thus, ESD has
become a hazard to the electronic industry. This tutorial paper presents the
concept of ESD as a special topic in the overall subject of electromagnetic
compatibility (EMC). It presents the fundamental aspects of ESD and answers
questions such as: what is ESD, how is ESD generated, and how is the human
body modeled for ESD? This tutorial paper also presents an engineering
example to calculate the damaging effects of ESD on electronic components.
The experimental demonstration is an integral part of this tutorial paper. The
experiment illustrates the following: a) how an electrically conductive surface
could be charged to very high voltages when in close proximity to a charged
dielectric material; b) how various factors could impact the occurrence of ESD;
c) how failure or electrical overstress on electronic components could result

Title: Using Coupled Transmission Lines to Generate Impedance-Matched
Pulses Resembling Charged Device Model ESD
Author: Maloney, T. J.
Poon, S. S.
Journal: Electronics Packaging Manufacturing, IEEE Transactions on
Year: 2006
Abstract: A quarter-wave directional coupler plus ordinary transmission line
pulsing (TLP) can create short pulses resembling charged device model (CDM)
electrostatic discharge (ESD). Pulse rise time often relates to the coupler's
center frequency and can thereby be stabilized. It is shown that for a voltage
step of a given size, yet with arbitrary waveform, the net amount of coupled
charge (the charge packet) is constant and depends only on fixed coupler
parameters. This property of Z-matched coupled lines has wider implications.
High-voltage couplers can be made from coaxial cable or from stripline. Some
of these designs are described, tested, and compared to computer simulations
of coupled lines.

Title: Holding voltage investigation of advanced SCR-based protection
structures for CMOS technology
Author: Tazzoli, A.
Marino, F. A.
Cordoni, M.
Benvenuti, A.
Colombo, P.
Zanoni, E.
Meneghesso, G.
Journal: Microelectronics Reliability
Year: 2007
Abstract: A new silicon-controlled rectifier low voltage triggered (SCR-LVT), to
be adopted as protection structure against electrostatic discharge (ESD)
events, has been developed and characterized. A high holding voltage has
been obtained thanks to the insertion of two parasitic bipolar transistors,
achieved adding a n-buried region to a conventional SCR structure. These two
parasitic transistors partially destroy the loop feedback gain of the two main
npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage
during the ESD event. A strong dependence of the holding voltage with the
ESD pulse width has also been observed, caused by self-heating effects.
2D-device simulations (DESSIS Synopsys) have been performed obtaining
results that perfectly fit the measurements over a wide temperature range (25
[degree sign]C - 125 [degree sign]C). Using device simulation results, the
factors that influence the holding voltage, in terms of temperature dependence,
but also in the behavior of the parasitic BJTs, are explained. A guideline to
change the SCR holding voltage, related to the SCR design layout without any
change to process parameters, is also proposed.

Title: Selecting an appropriate ESD protection for discrete RF power
LDMOSTs
Author: Smedes, T.
de Boet, J.
Rodle, T.
Journal: Microelectronics Reliability
Year: 2007
Abstract: For ESD protections of RF Power MOSTs, Vt1 lowering by the RF
signal - due to the dV/dt effect - can seriously degrade the RF performance.
The use of a cascoded protection solves this problem. A new failure
mechanism, related to the discharge of on-chip RF matching capacitors is
presented. Adding a current limiting resistor in the protection solves this issue.
Combining these solutions yields an appropriate protection for discrete RF
power LDMOSTs.

Title: SCR-based ESD protection in nanometer SOI technologies
Author Marichal, Olivier
Wybo, Geert
Van Camp, Benjamin
Vanysacker, Pieter
Keppens, Bart
Journal: Microelectronics Reliability
Year: 2007
Abstract: This paper introduces an SCR-based ESD protection design for
silicon-on-insulator (SOI) technologies. SCR devices or thyristors, as they are
sometimes better known, have long since been used in Bulk CMOS to provide
very area efficient, high performance ESD protection for a wide variety of
circuit applications. The special physical properties and design of an SOI
technology however, renders straightforward implementation of an SCR in
such technologies impossible. This paper discusses these difficulties and
presents an approach to construct efficient SCR devices in SOI. These
devices outperform MOS-based ESD protection devices by about four times,
attaining roughly the same performance as diodes. Experimental data from
two 65 nm and one 130 nm SOI technologies is presented to support this.

Title: SCR-based ESD protection in nanometer SOI technologies
Author Glaser, Ulrich
Esmark, Kai
Streibl, Martin
Russ, Christian
Domanski, Krzysztof
Ciappa, Mauro
Fichtner, Wolfgang
Journal: Microelectronics Reliability
Year: 2007
Abstract: Diodes and diode strings in 90 nm and beyond technologies are
investigated by measurement and device simulation. After a thorough
calibration, the device simulator is utilised to achieve a better understanding
and an enhanced device performance of diode strings under static and
transient ESD conditions. Thereto, parasitic transistors and a so far neglected
parasitic thyristor (SCR) in the diode string are regarded, exploited and
optimised.
.
Title: Implementation of diode and bipolar triggered SCRs for CDM robust ESD
protection in 90 nm CMOS ASICs
Author Brennan, Ciaran J.
Chang, Shunhua
Woo, Min
Chatty, Kiran
Gauthier, Robert
Journal: Microelectronics Reliability
Year: 2007
Abstract: We report the characterization of diode and bipolar triggered SCRs
with VFTLP measurements and product ESD testing. A dual base Darlington
bipolar triggered SCR (DbtSCR) in a triple well structure is demonstrated to
provide 4 kV HBM, 300 V MM, and 1000 V CDM protection for 90 nm ASIC
I/Os. A very fast turn-on time of 460 ps was measured for the DbtSCR,
compared to 8 ns for a diode triggered SCR.

Title: Determining factors affecting ESD failure voltage using DOE
Author Whitman, Charles
Gilbert, Terri M.
Rahn, Ann M.
Antonell, Jennifer A.
Journal: Microelectronics Reliability
Year: 2006
Abstract: Factors influencing machine model (MM) ESD failure voltage are
investigated in two statistically designed experiments. Several variables (or
factors), namely wafer lot, type of ESD handling procedure, pulse polarity
order and assembly house are studied. The results are examined using three
methods: survival analysis, logistic regression and an empirical approach.
Each method can be used to predict the cumulative distribution function (cdf)
which is the probability of failure on or before a particular voltage. Survival
analysis treats the failure voltage as a response to the settings of the various
factors. The failure voltage is analogous to the "failure time". This method
predicts the cdf given the settings of the different variables. In contrast, logistic
regression treats voltage as a factor, along with the other variables and will
similarly predict the cdf given the settings of all the factors. The empirical
approach is used to estimate the cdf using only the distribution of failure
voltages for each run in a designed experiment and is not derived from the
factor settings. This third approach can be used as a check on the first two. In
the first DOE, the factors wafer lot, level of ESD-safe handling, pulse polarity
order and their interactions are found to change the predicted median failure
voltage from ~19 to ~34 V, a swing of +/-30% from the overall median ~26 V.
The effect of wafer lot along with the interaction between the level of ESD
protection and pulse polarity order are found to be statistically significant. In
the second DOE, only the effects of wafer and assembly house are studied.
Here, just wafer has a significant effect. The range of ESD failure voltages is
much smaller in round 2 (~30 to ~36 V). Although the failure voltages reported
here are relatively low, the methods described herein are general. Thus, the
approaches described can be applied to circuits with much higher ESD failure
voltages.

Title: Novel gate and substrate triggering techniques for deep sub-micron ESD
protection devices
Author Semenov, O.
Sarbishaei, H.
Axelrad, V.
Sachdev, M.
Journal: Microelectronics Reliability
Year: 2006
Abstract: As technology feature size is reduced, ESD becomes the dominant
failure mode due to lower gate oxide breakdown voltage. In this paper, the
effectiveness of new gate and substrate triggering techniques has been
investigated to lower the trigger voltage of the LVTSCR and MOSFET based
ESD protection circuits using 2D simulations and HBM/TLP measurements.
The simulation results show that the using these techniques reduces the ESD
triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based
ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness
of proposed gate and substrate triggering techniques is also confirmed by the
HBM and TLP measurements.
Title: Comprehensive ESD protection approach in advanced CMOS SOI
technologies
Author Khazhinsky, Michael G.
Stockinger, Michael
Miller, James W.
Weldon, James C.
Journal: Journal of Electrostatics
Year: 2006
Abstract: In this paper we describe a 90 nm SOI ESD protection network and
design methodology including both device and circuit level characterization
data. We compare TLP results of SOI MOSFETs and diodes to bulk devices.
We present a new response surface method to optimize device sizes in the
ESD networks and show circuit level data comparing TLP test results and
SPICE simulation results of an I/O test circuit. We also present product test
data for standard ESD stress models.

Title: ESD protection solutions for high voltage technologies
Author Keppens, Bart
Mergens, Markus P. J.
Trinh, Cong Son
Russ, Christian C.
Van Camp, Benjamin
Verhaege, Koen G.
Journal: Microelectronics Reliability
Year: 2006
Abstract: There is a trend to revive mature technologies while including high
voltage options. ESD protection in those technologies is challenging due to
narrow ESD design windows, NMOS degradation problems and the creation of
unexpectedly weak parasitic devices. Different case studies are presented for
ESD protection based on latch-up immune SCR devices.

Title: Analysis of triggering behaviour of high voltage CMOS LDMOS clamps
and SCRs during ESD induced latch-up
Author Heer, M.
Dubec, V.
Bychikhin, S.
Pogany, D.
Gornik, E.
Frank, M.
Konrad, A.
Schulz, J.
Journal: Microelectronics Reliability
Year: 2006
Abstract: Current flow uniformity during ESD induced latch-up event is
investigated in multi-finger LDMOS clamps and SCR ESD protection devices
fabricated in a 0.6 [mu]m high voltage CMOS process. Current flow, excess
free carrier and hot spot distribution are analyzed by transient interferometric
mapping technique combined with a latch-up pulse system consisting of a solid
state pulser and a clear pulse unit. During latch-up, the current in the LDMOS
clamps flows just in a single spot and the failure position is random and
independent on device type. The position of the failure site correlates with the
trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in
the current flow.

Title: ESD design automation & methodology to prevent CDM failures in 130 &
90 nm ASIC design systems
Author Brennan, Ciaran J.
Kozhaya, Joseph
Proctor, Robert
Sloan, Jeffrey
Chang, Shunhua
Sundquist, James
Lowe, Terry
Picozzi, David
Journal: Journal of Electrostatics
Year: 2006
Abstract: Design automation tools for ESD are described that ensure robust
protection at both the cell and chip level in a high-volume, highly automated
ASIC design system. The Charged Device Model (CDM) failure modes
discovered in the 130 nm technology are described, and the design
automation tools that were implemented to prevent these failures are
presented. There are three primary components: Design rule checking for ESD;
transient CDM simulations on extracted net lists; and analysis of chip-level
power supply net resistances.

Title: Capacitively coupled transmission line pulsing cc-TLP--a traceable and
reproducible stress method in the CDM-domain
Author Wolf, Heinrich
Gieser, Horst
Stadler, Wolfgang
Wilkening, Wolfgang
Journal: Microelectronics and Reliability
Year: 2005
Abstract: This paper describes a new test method called capacitively coupled
transmission line pulsing cc-TLP. It is applied to different test circuits which
were mounted on specially designed package emulators with a defined
background capacitance. The test results are compared with the ESD
thresholds obtained by CDM tests. The cc-TLP results correlate well with the
CDM data.

Title: ESD circuit model based protection network optimisation for
extended-voltage NMOS drivers
Author Vassilev, V.
Vashchenko, V.
Jansen, Ph
Groeseneken, G.
Terbeek, M.
Journal: Microelectronics and Reliability
Year: 2005
Abstract: New snapback circuit models for drain extended MOS (DEMOS) and
complementary DEMOS-SCR structures used for ESD protection in
high-voltage tolerant applications have been developed. The models were
experimentally validated in a standard 0.35 [mu]m CMOS process which
requires 20 V compatible structures. It is shown that the new ESD models
provide accurate representation of the structure breakdown, turn-on behaviour
into conductivity modulation mode and dV/dt triggering effect, both in static and
ESD transient conditions. A major application of this model is for initial ESD
optimisation of complex mixed voltage analog circuits.

Title: ESD-RF co-design methodology for the state of the art RF-CMOS blocks
Author Vassilev, V.
Thijs, S.
Segura, P. L.
Wambacq, P.
Leroux, P.
Groeseneken, G.
Natarajan, M. I.
Maes, H. E.
Steyaert, M.
Journal: Microelectronics and Reliability
Year: 2005
Abstract: This paper describes an approach to design ESD protection for
integrated low noise amplifier (LNA) circuits used in narrowband transceiver
front-ends. The RF constraints on the implementation of ESD protection
devices are relaxed by co-designing the RF and the ESD blocks, considering
them as one single circuit to optimise. The method is applied for the design of
0.25 [mu]m CMOS LNA. Circuit protection levels higher than 3 kV HBM stress
are achieved using conventional highly capacitive ggNMOS snapback devices.
The methodology can be extended to other RF-CMOS circuits requiring ESD
protection by merging the ESD devices in the functionality of the
corresponding matching blocks.
Title: High abstraction level permutational ESD concept analysis
Author Streibl, M.
Zangl, F.
Esmark, K.
Schwencker, R.
Stadler, W.
Gossner, H.
Druen, S.
Schmitt-Landsiedel, D.
Journal: Microelectronics and Reliability
Year: 2005
Abstract: A simulation approach is presented that allows handling ESD
simulation and analysis on a chip-level complexity. In a Monte-Carlo like
permutational simulation approach, worst case ESD paths are identified. The
simulator is embedded in an ESD analysis framework spanning from the chip
protection description to an automated virtual HBM test routine with a
respective fail reporting interface. The tools capabilities are demonstrated in
the ESD analysis of a complex mixed-signal design.

Title: Electrostatic discharge directly to the chip surface, caused by automatic
post-wafer processing
Author Jacob, Peter
Thiemann, Uwe
Reiner, Joachim C.
Journal: Microelectronics and Reliability
Year: 2005
Abstract: Up to now, ESD damage is understood to be induced via device pads
and to be avoided by means of appropriate protection structures located at
these pads. The ESD susceptibility is classified by means of standardized
stress tests. This paper shows, that with increasing importance a variety of
post-wafer manufacturing and packaging processes may create a new type of
evident and latent ESD damage in the device. We define this phenomenon as
ESD-from-outside-to-surface (ESDFOS), as charged handlers cause
discharges directly from outside into the device surface. Classical ESD tests
do not cover this mechanism. The paper describes the phenomenon, its root
causes, and gives practical hints for analysis and prevention.

Title: A new multi-finger SCR-based structure for efficient on-chip ESD
protection
Author Azais, F.
Caillard, B.
Dournelle, S.
Salome, P.
Nouet, P.
Journal: Microelectronics and Reliability
Year: 2005
Abstract: This paper introduces a new SCR-based (silicon controlled rectifier)
structure for on-chip ESD protection. The STMSCR (smart triggered
multi-finger SCR) relies on the bimodal operation of a LSCR (lateral SCR)
using an external triggering circuitry that permits switching from a transparency
mode to a protection mode as soon as an ESD event is detected. The trigger
voltage can be adjusted by design without any impact on the ESD
performance. The STMSCR is multi-finger compliant, thus allowing
area-efficient design of pad-located ESD protection. The STMSCR is
demonstrated in a 0.18 [mu]m CMOS technology without any process
customization; an HBM failure threshold over 115 V/[mu]m is reached while
always ensuring current uniformity in multi-finger structures.

Title: Methods for designing low-leakage ESD power supply clamps
Author Maloney, Timothy J.
Poon, Steven S.
Clark, Lawrence T.
Journal: Journal of Electrostatics
Year: 2004
Abstract: Low-power semiconductor components require minimizing leakage
currents including those from ESD protection circuits. Here, MOSFET ESD
power clamps with substantial leakage reduction over previous approaches
are presented. Designs are described for core logic circuits and for I/O
applications where supply voltages exceed what single gate oxides can
reliably sustain.

Title: ESD protection design challenges for a high pin-count alpha
microprocessor in a 0.13 [mu]m CMOS SOI technology
Author Juliano, Patrick A.
Anderson, Warren R.
Journal: Journal of Electrostatics
Year: 2004
Abstract: We illustrate the complexity of designing ESD protection for a 64-bit
microprocessor employing 140 million transistors. This IC contains 901 I/O
signals, most operating at >l Gbit/s/pin, and 10 power supplies split into 27
domains. An extensive set of CAD tools used to expedite ESD-related chip
assembly and to analyze finished layout is described.

Title: High frequency characterization and modelling of the parasitic RC
performance of two terminal ESD CMOS protection devices
Author Vassilev, V.
Jenei, S.
Groeseneken, G.
Venegas, R.
Thijs, S.
De Heyn, V.
Natarajan, M.
Steyaert, M.
Maes, H. E.
Journal: Microelectronics Reliability
Year: 2003
Abstract: This paper describes a simplified high frequency characterization
approach to extract the parasitic RC figures of merit of two terminal CMOS
electrostatic discharge (ESD) protection devices. Basic RC small signal
equivalent models and corresponding parameter extraction procedures,
applicable for the most typical structures--grounded gate NMOS, diodes and
SCR's are presented. The model application to study the impact of the ESD
failures on the HF device and circuit characteristics is demonstrated.

Title: Quasi-3D simulation approach for comparative evaluation of triggering
ESD protection structures
Author Vashchenko, V. A.
Concannon, A.
ter Beek, M.
Hopper, P.
Journal: Microelectronics Reliability
Year: 2003
Abstract: A 2D simulation approach that takes into account the 3D effects of
electro-thermal instability during electrostatic discharge (ESD) operation, is
presented. The method is used to provide physical evaluation of a safe
operation regime for BiCMOS ESD protection structures and circuits. The
methodology is demonstrated through the application to Si-Ge NPN bipolar
transistors, snapback NMOS and LVTSCR structures.

Title: LVTSCR structures for latch-up free ESD protection of BiCMOS RF
circuits
Author Vashchenko, V. A.
Concannon, A.
ter Beek, M.
Hopper, P.
Journal: Microelectronics Reliability
Year: 2003
Abstract: The results of a numerical and experimental study aimed at
increasing the holding on-state voltage of a low-voltage triggered silicon
controlled rectifier are presented. Using TCAD numerical simulations two
solutions are presented that are based on emitter injection control by the
modification of the emitter-drain area ratio and by the addition of internal
diodes in the emitter line. Experimental data generated in a 0.18 [mu]m CMOS
technology demonstrate the effectiveness of the new low-voltage triggered
silicon controlled rectifier (LVTSCR) structures and validates the simulation
results. It has been demonstrated that for the LVTSCR structures with high
holding voltage the electrostatic discharge efficiency is 3-5 times higher than
that of a conventional grounded gate snapback NMOS and simultaneously has
50% lower RF load capacitance.

Title: High holding current SCRs (HHI-SCR) for ESD protection and latch-up
immune IC operation
Author Mergens, Markus P. J.
Russ, Christian C.
Verhaege, Koen G.
Armer, John
Jozwiak, Phillip C.
Mohn, Russ
Journal: Microelectronics Reliability
Year: 2003
Abstract: This paper presents a novel Silicon Controlled Rectifier (SCR) for
power line and local I/O ESD protection. The High holding current SCRs
(HHI-SCR) exhibits a dual ESD clamp characteristic: low-current high-voltage
clamping and high-current low-voltage clamping. These operation modes
enable latch-up immune normal operation as well as superior full chip ESD
protection. The minimum latch current can be controlled by specific SCR
design. The HHI-SCR is demonstrated in a 0.10 [mu]m-CMOS and in a 0.4
[mu]m-BiCMOS technology. The design is area efficient.

Title: Process influence on product CDM ESD performance
Author Lisenker, Boris
Journal: Microelectronics Reliability
Year: 2003
Abstract: Effective ESD protection circuit design has become challenging due
to rapid advances in process technology. This study was launched to address
those concerns in deep sub-micron technologies and to look for a process
windows that preserve CDM ESD robustness for a given ESD protection
designs. Experimental results for 0.18 [mu]m integrated CPU's together with
process window effects on CDM robustness are presented and discussed. The
correlation between electrical characteristics and some of the common failure
modes are described. It is shown that transistor off current lower than critical
value can lead to degradation in time and an eventual secondary breakdown in
a parasitic NPN transistor that results in unexpected CDM sensitivity.

Title: Process influence on product CDM ESD performance
Author Lisenker, Boris
Journal: Microelectronics Reliability
Year: 2003
Abstract: Effective ESD protection circuit design has become challenging due
to rapid advances in process technology. This study was launched to address
those concerns in deep sub-micron technologies and to look for a process
windows that preserve CDM ESD robustness for a given ESD protection
designs. Experimental results for 0.18 [mu]m integrated CPU's together with
process window effects on CDM robustness are presented and discussed. The
correlation between electrical characteristics and some of the common failure
modes are described. It is shown that transistor off current lower than critical
value can lead to degradation in time and an eventual secondary breakdown in
a parasitic NPN transistor that results in unexpected CDM sensitivity.

Title: High ESD performance, low power CMOS LNA for GPS applications
Author Leroux, Paul
Vassilev, Vesselin
Steyaert, Michiel
Maes, Herman
Journal: Journal of Electrostatics
Year: 2003
Abstract: This paper describes the design of a high performance 0.25 [mu]m
CMOS low noise amplifier (LNA) for the global positioning system (GPS)
operating at 1.57 GHz. The LNA features a 1.5 dB noise figure. The input
ESD-protection is in the order of 3 kV HBM and the power consumption is only
6 mW.

Title: ESD evaluation of a low voltage triggering SCR (LVTSCR) device
submitted to transmission line pulse (TLP) test
Author Guilhaume, A.
Galy, P.
Chante, J. P.
Foucher, B.
Bardy, S.
Blanc, F.
Journal: Journal of Electrostatics
Year: 2002
Abstract: For a deeper understanding of protection structures during ESD
events, transmission line pulse events are applied and simulated with a
two-dimensional (2D) device simulator on the particular case of a 1.2 [mu]m
low voltage triggering silicon controlled rectifier. Thanks to measurements and
simulated results, we were able to evaluate the robustness of the structure in
terms of ESD. This article also focuses on the different behavior modes of
such a device depending on the current level applied to the electrodes.
Title: Dynamic triggering characteristics of SCR-type electrostatic discharge
protection circuits
Author Jang, Sheng-Lyang
Lin, Lien-Sheng
Li, Shao-Hua
Chen, Hwan-Mei
Journal: Solid-State Electronics
Year: 2001
Abstract:

Title: Temperature-dependent dynamic triggering characteristics of SCR-type
ESD protection circuits
Author J Jang, Sheng-Lyang
Lin, Lien-Sheng
Li, Shao-Hua
Journal: Solid-State Electronics
Year: 2001
Abstract:

Title: MOSFET triggering silicon controlled rectifiers for electrostatic discharge
protection circuits
Author Jang, Sheng-Lyang
Li, Shao-Hua
Journal: Solid-State Electronics
Year: 2001
Abstract:

Title: Analyzing the switching behavior of ESD-protection transistors by very
fast transmission line pulsing
Author Wolf, Heinrich
Gieser, Horst
Wilkening, Wolfgang
Journal: Journal of Electrostatics
Year: 2000
Abstract:: This work describes, how the very fast transmission line pulsing
(VFTLP)-technique can be used to characterize the switching behavior of ESD
protection elements. In a first application we investigate the behavior of a
protection element consisting of a lateral and vertical transistor part. This
element shows a good ESD performance under 100 ns-TLP and HBM
conditions. Under CDM relevant conditions, however, we could identify by
means of VFTLP a delayed triggering of the vertical transistor part, which
leads to an increased maximum voltage and thus to a low-failure threshold. In
the second application we propose a methodology for the extraction of the
base transit time parameter which improves the accuracy of a compact
transistor model during turn on.

Title: A study of diode protection for giant magnetoresistive recording heads
Author Wallash, A.
Wang, Wenwei
Journal: Journal of Electrostatics
Year: 2000
Abstract:: ESD testing of giant magnetoresistive (GMR) heads with diode
protection is described. While the use of diodes did increase the magnetic and
failure voltages of the GMR head, the magnetic failure voltage was increased
much less than the resistance failure voltage. This results in an unfortunate
side effect, which is to dramatically increase the range over which magnetic
damage occurs without a corresponding resistance change. This problem was
especially clear for the case of two diodes in series. The current flow through
the GMR head and diode were measured and agreed with SPICE circuit
simulation results. The difference between magnetic and resistance protection
is due to the nonlinear clamping behavior of the diode. We conclude that
serious magnetic damage will be the predominant failure signature for GMR
heads with ESD protect diodes.

Title: Temperature-dependence of steady-state characteristics of SCR-type
ESD protection circuits
Author Jang, Sheng-Lyang
Lin, Jeng-Kuan
Journal: Solid-State Electronics
Year: 2000
Abstract::

Title: Novel diode-chain triggering SCR circuits for ESD protection
Author Jang, Sheng-Lyang
Gau, Ming-Shung
Lin, Jeng-Kuan
Journal: Solid-State Electronics
Year: 2000
Abstract::

Title: Characterization and optimization of a bipolar ESD-device by
measurements and simulations
Author Stricker, Andreas D.
Mettler, Stephan
Wolf, Heinrich
Mergens, Markus
Wilkening, Wolfgang
Gieser, Horst
Fichtner, Wolfgang
Journal: Solid-State Electronics
Year: 1999
Abstract:: The design of ESD (electro-static discharge) protection structures
can be significantly shortened by using thermo-electrical device simulations. In
many cases simulation results predict the performance of new designs enough
accurate which makes it unnecessary to go through the whole manufacturing
process of test chips. More important, however, they allow the designer to gain
additional insight into a problem by examining device-internal parameters that
are not obtainable through measurements, such as current densities, the
electric field and the lattice temperature. In this article we investigate and
optimize a p-base type npn-transistor with a vertical and a lateral operation
mode. Based on the TCAD tool chain, we develop a methodology to simulate
the transient switching behavior, the avalanche breakdown and the snapback
holding voltages of the device. To validate our design methodology we
implemented the evaluated devices on a real test chip which has also been
used to gain the needed data for the calibration of the simulators. Thus we are
able to compare simulation and measurements and found the simulated
voltages to closely match values obtained in measurements. In addition we
extracted a set of parameters for a compact circuit model describing the device
under various ESD stress types.


Title: Electrostatic discharges (ESD), latch-up and pad design constraints
Author Salome, Pascal
Richier, Corinne
Journal: Microelectronic Engineering
Year: 1999
Abstract::This paper is tailored to beginners in the field of electrostatic
discharges. After a brief introduction, the basics of ESD are first reviewed and
followed by a description of the standards devoted to the protection of
intregrated circuits. Then, the behavior and modeling of elementary devices
under ESD are discussed.


Title: ESD protection in thin film silicon on insulator technologies
Author Smith, J. C.
Journal: Microelectronics and Reliability
Year: 1998
Abstract: This paper reviews some of the devices and circuits which have been
used to implement ESD protection networks for thin film silicon on insulator
(TFSOI) technologies. The high current behavior of TFSOI MOSFETS and
diodes is described for both positive and negative discharges. Next, several
representative pin-protection network designs are reviewed which have all
been shown to provide industry-standard levels of ESD protection. A
discussion of power-supply protection networks follows, which must be used in
conjunction with the pin protection schemes.

Title: ESD laboratory simulations and signature analysis of a CMOS
programmable logic product
Author Henry, L. G.
Raymond, T.
Mahanpour, M.
Morgan, I.Journal: Microelectronics and Reliability
Year: 1998
Abstract: It is well established in the semiconductor I/C industry that the
proportion of customer field returns attributed to damage resulting from
electrical over-stress (EOS) and electro-static discharge (ESD) can amount to
40% to 50% (Cook C, Daniel S. Characteristics and failure analysis of
advanced CMOS submicron ESD protection structures. EOS/ESD symposium
proceedings #14, Dallas, TX, 1992. p. 147; Denson WK, Green TJ. A review of
EOS/ESD field failures in military equipment. EOS/ESO symposium
proceedings-10, 1988. p. 7. Straub RJ. Automotive Electronics IC Reliability.
CICC Proceedings, 1990; Euzent BL, Maloney TJ, Donner II R. Reducing field
failure rate within proven EOS/ESO design. EOS/ESO Symposium
Proceedings #13, Los Vegas, NV, 1991. p. 59). ESD events are the subset of
EOS events caused by high voltages that are associated with electrostatic
charge. Although additional hard and soft failures can occur in the factory,
these are normally screened by effective test programs. It is therefore
necessary to determine the probable cause of failure before cost effective
corrective action can be initiated. Distinguishing between EOS and ESD
failures and differentiating the subtle differences between damage due to the
several distinct ESD models continues to challenge failure analysis capabilities
as dimensions shrink and critical defect sizes are reduced. Many of the
damage sites are not visible with optical microscopy. De-processing together
with very high magnification examination using the scanning electron
microscope (SEM) is most often necessary. However, the use of test model
simulators to replicate the ESD events can most often replicate a failure
signature, i.e. a unique die location and morphology associated with the
specific model (Morgan IH. ESO Failure Analysis Signatures. Proceedings of
the 3rd ESO Forum, Grain, Germany, 1993. p. 275). This paper summarizes
the evaluation performed on a standard programmable logic complimentary
metal-oxide silican (CMOS) product to ascertain the ESD immunity. The study
entailed ESD simulation using a variety of ESD models, conducting detailed
physical failure analysis and then comparing the results with documented
analyses performed on customer field returns and factory failures. As a result
of the differences in current stress magnitude and over-stress time domain, the
location, type and severity of damage at the failure site is known to show
considerable variation (Morgan IH. A Handbook of ESO models. AMD Internal
Publication, 1992 (available from AMD literature department upon request)).
The purpose of the study was to develop a catalogue of failure signatures, and
to determine to what extent this catalogue could be used to relate a signature
to electrical failure for a particular die and pin function.

Title: ESD protection methodology for deep-sub-micron CMOS
Author Bock, K.
Groeseneken, G.
Maes, H. E.
Journal: Microelectronics Reliability
Year: 1998
Abstract: Electrostatic discharge is considered to be a serious treat of
integrated CMOS circuits since the feature size reached about 1.5-1.0[mu]m.
Since then the scaling of CMOS technologies led to an increase of their ESD
susceptibility based on geometrical, physical and technological limitations. The
paper describes the change in methodology in order to assure a reasonably
high target value of ESD protection with newly to be developed deep
sub-micron feature size technologies. The backward adaptive conservative
methodology is step by step replaced by a methodology considering the ESD
issue already during process development and involving more predictive
ESD-TCAD into the development cycle. It is concluded that the scaling based
limitations might grow to a significant problem in the near future requiring
significant effort to assure a reasonable ESD protection level for CMOS
technologies, in particular if the high-frequency properties of such technologies
should not be affected.

Title: Using an SCR as ESD protection without latch-up danger
Author Notermans, Guido
Kuper, Fred
Luchies, Jan-Marc
Journal: Microelectronics and Reliability
Year: 1997
Abstract: A properly designed Low-Voltage Triggering SCR has a four times
better ESD performance than a conventional grounded-gate NMOST of the
same width. But it does present a latch-up risk due to its low holding voltage.
The holding voltage can be increased by using a larger anode-to-cathode
spacing, but at very large spacings the ESD performance decreases. It is
shown that a window in SCR anode-to-cathode spacing exists, for which the
holding voltage is sufficiently large, while the excellent ESD protection
properties are preserved.

Title: Analysis of snubber-clamped diode-string mixed voltage interface ESD
protection network for advanced microprocessors
Author Voldman, Steven H.
Gerosa, Gianfranco
Gross, Vaughn P.
Dickson, Nicholas
Furkay, Stephen
Slinkman, James
Journal: Journal of Electrostatics
Year: 1996
Abstract: A novel snubber-clamped diode-string ESD protection circuit for
mixed voltage interface microprocessor applications is described. Analytical
models, circuit simulation, electrical characterization, ESD electrothermal
simulation, and ESD test data, will be shown for shallow trench isolation (STI)
and LOCOS CMOS technologies.

Title: Bi-modal triggering for LVSCR ESD protection devices
Author Diaz, Carlos
Motley, Gordon
Journal: Journal of Electrostatics
Year: 1995
Abstract: This paper addresses three aspects of LVSCR protection devices
namely, LVSCR layout optimization, triggering techniques, and the impact of
stress signal slew-rate on ESD performance. Circuit techniques to achieve
bi-modal triggering for LVSCR ESD protection schemes are presented. The
low voltage trigger mode operates when the chip is in packaging and assembly
while the high voltage mode operates when the chip is in the final product
board with the power supplies applied. The triggering techniques discussed
here are particularly useful in conjuction with high speed I/Os and interface ICs.
The paper also reports the impact of stress slew rates on the failure thresholds.
In particular, it is shown that when the slew rate is increased from 0.2 to 0.4
A/ns, the SCR failure threshold decreases from that given by a second
breakdown failure mode to the one dictated by an early oxide failure. The
paper concludes with an analysis of the LVSCR layout parameters on its
trigger and ESD clamping effectiveness.

Title: ESD protection using a variable voltage supply clamp
Author Croft, Gregg D.
Journal: Journal of Electrostatics
Year: 1995
Abstract: This paper discusses the advantages and limitations of using supply
clamping networks for electrostatic discharge (ESD) protection of integrated
circuits (ICs). In addition, this paper presents an innovative supply clamp
circuit that attempts to address some of the limitations of the more traditional
supply clamping methods. This new circuit varies its clamp voltage depending
upon whether or not the IC is mounted in a printed circuit board. If the IC is not
mounted the clamp voltage is set at a very low value for maximum ESD
protection. However, once the IC is mounted, the clamp voltage is increased to
a value greater than the supply voltage to avoid interfering in the normal
operation of the IC. Voltage versus current (V/I) characteristics of this supply
clamp circuit are compared for the mounted versus unmounted cases. In
addition, human body model (HBM) ESD threshold levels are compared for
protected versus unprotected ICs. HBM ESD thresholds were seen to increase
from as low as 500 V to greater than 4000 V due to the addition of a protection
network incorporating this clamp circuit.

Title: On chip ESD protection using SCR pairs
Author Croft, Gregg D.
Journal: Journal of Electrostatics
Year: 1993
Abstract: T A theoretical ideal ESD protection circuit is discussed, and a novel
protection network modeled after the ideal circuit is presented. This novel
protection network provides discharge paths between all possible pin
combinations on an integrated circuit (IC) by employing complementary pairs
of SCR's connecting all I/O pin and intermediate supply pins to the most
negative and the most positive supply rails. The configuration of these SCR
pairs allows the network to maximize its ability to protect by adjusting its dv/dt
[2] threshold as the integrated circuit is powered up and powered down. During
the powered down state the dv/dt threshold of the protection network is set
very low to provide maximum protection for the IC. However, once the IC is
powered up, the dv/dt threshold of the protection network is increased
significantly to prevent it from being triggered by the normal voltage transitions
of the input and output signals. The configuration of these SCR pairs also
serves to minimize the parasitic capacitance and leakage currents that this
protection network adds to all of the I/O pins. This characteristics allows this
network to be used with certain classes of integrated circuits, such as op amps,
that were previously very difficult to protect without greatly degrading thei
operating characteristics. ESD thresholds and electrical performance for
devices both with and without this network are compared. Human body model
ESD thresholds were seen to improve from below 500 volts to as high as 6000
volts with only slight degradation seen in device performance.

Title: A successful HBM ESD protection circuit for micron and sub-micron level
CMOS
Author Carbajal, Bernard G.
Cline, Roger A.
Andersen, Bernhard H.
Journal: Journal of Electrostatics
Year: 1993
Abstract: A successful ESD protection circuit depends on a clear
understanding of the process parameters and design rules of a given
fabrication process. This work will show an ESD protection scheme that
protects CMOS well as minimum feature sizes ranging from micron to
sub-micron scales. The primary protection device utilizes an SCR structure
available from a N-Well CMOS process in conjunction with a series N-Well
resistor. ESD immunity of > 2 kV has been demonstrated on state of the art
ASIC arrays using these structures.

Title: On-chip electrostatic discharge protections in advanced CMOS
technologies
Author Maene, N.
Vandenbroeck, J.
Allaert, K.
Journal: Microelectronics and Reliability
Year: 1992
Abstract: In this paper several on-chip electrostatic discharge (ESD)
protections for inputs, outputs and supply pins are discussed. By comparing
different structures, insight has been attained in the most important
parameters determining the ESD sensitivity, and optimal protections for the
Human Body Model (HBM) which could be selected. In addition the test
method as prescribed by the Mil-Std 883C Method 3015.7 is discussed more
into detail, leading to the concept of using a supply protection for improving the
ESD performance of inputs/outputs (I/Os). For input protections the
performance of the lateral silicon controlled rectifier (SCR) structure is found to
be superior to the behaviour of the classical thick oxide protection, the
minimum failure voltage of the former being 6000 V. Several alternatives for
CMOS outputs are also presented. A comparison between the "waffle" layout
and the more classical ladder layout concerning the ESD performance is made.
A minimum failure voltage of 1750 V for stressing the output vs the ground for
both polarities has been seen on one of our output structures. However, the
output failure voltage can be increased by using a good supply protection,
providing a parallel discharge path. The concept of using a supply protection
for achieving a better ESD hardness is highlighted in this paper. An output of a
ring oscillator with a thick oxide supply protection did not fail up to 2000 V for a
worst case stress, and using a SCR supply protection with an optimised output
layout still should result in a better ESD hardness.

Title: A synthesis of ESD input protection scheme
Author Duvvury, Charvaka
Rountree, Robert
Journal: Journal of Electrostatics
Year: 1992
Abstract: A synthesis of total effective input protection, consisting of primary
and secondary protection devices, is presented here for advanced CMOS
technologies. In particular, it is shown that for efficient protection the primary
circuit needs to be a low trigger SCR and the secondary circuit needs to be
either a diffusion resistor with avalanche suppression or even a polysilicon
resistor. The latter scheme with the poly resistor is shown to give greater than
6 kV of reliable performance, which can be particularly attractive for analog
circuit applications.

Title: The use of varistor composite materials as an additional level of clamping
for ESD-sensitive devices
Author Malinaric, Paul J.
Journal: Journal of Electrostatics
Year: 1990
Abstract: This paper describes a two-stage clamping technique for ESD
protection to circuitboards and other devices; one at the local level and the
other at the terminal strip interfacing the board to the outside world. Generally
the terminal strip connects low-impedance leads, such as for power input and
output, and relatively high-impedance leads, such as for data input and output
and which are usually connected to highly ESD-sensitive MOS devices and
which are the subject of this paper. A primary heavy duty clamp of the order of
100 V is incorporated into the terminal strip via a varistor paint, and a
secondary clamp of the order of a few volts is incorporated into the circuit at
the local level, with a decoupling resistor inbetween. With this technique the
primary clamp dissipates over 99% of the ESD current and power, leaving only
a small portion of the energy to be dissipated by the local clamp.

Title:The use of varistor composite materials as an additional level of clamping
for ESD-sensitive devices
Author Pee-Ya, Tan
Indrajit, M.
Pian-Hong, Li
Voldman, S. H. A. Voldman S. H.
Conference Name: Physical and Failure Analysis of Integrated Circuits, 2005.
IPFA 2005. Proceedings of the 12th International Symposium on the
Year: 2005
Abstract: Silicon controlled rectifiers (SCRs) have superior ESD performance
and are expected to play a major role in sub-/spl mu/m technologies replacing
MOSFET-based ESD networks due to MOSFET dielectric scaling. In this
paper, novel polysilicon-bound SCR-based clamp circuit is explored that
provide simultaneous triggering of NPN and PNP bipolar transistors by means
of RC discriminator network and a triggering circuit stages coupled into the
regenerative feedback loop of the SCR. This network demonstrates good ESD
performance, low on-resistance, high I/sub t2/ and low holding voltage.
Title: Transmission line pulse picosecond imaging circuit analysis methodology
for evaluation of ESD and latchup
Author Weger, A.
Voldman, S.
Stellari, F.
Peilin Song, A. Peilin Song
Pia Sanda, A. Pia Sanda
McManus, M. A. McManus M.
Conference Name: Reliability Physics Symposium Proceedings, 2003. 41st
Annual. 2003 IEEE International
Year: 2003
Abstract: This paper will demonstrate the synthesis of the high current pulse
source method (e.g. used in transmission line pulse (TLP) systems) and the
Picosecond Imaging Circuit Analysis (PICA) tool for the evaluation. of
electrostatic discharge (ESD) and latchup phenomenon. In this fashion, the
evolution of ESD and latchup can be evaluated in semiconductor devices, and
in peripheral circuits at a wafer level or product level. The methodology
described in this publication allows for visualization of ESD and latchup, events
(e.g. animation in a picosecond time regime). The synthesis of the
transmission line pulse (TLP) method and the PICA method allows for the
extension of the ESD TLP methodology to terminal currents and spatial and
time domain analysis for electrical characterization and reliability analysis, and
the high current pulsed source extends the utilization of the PICA methodology
for failure analysis on wafer and chip levels.

Title: Electrostatic discharge (ESD) technology benchmarking strategy for
evaluating ESD robustness of CMOS technologies
Author Voldman, S.
Anderson, W.
Ashton, R.
Chaine, M. A. Chaine M.
Duvvury, C. A. Duvvury C.
Maloney, T. A. Maloney T.
Worley, E. A. Worley E.
Conference Name: Integrated Reliability Workshop Final Report, 1998 IEEE
International
Year: 1998
Abstract:This paper describes an ESD technology benchmarking strategy for
evaluating the ESD robustness of a semiconductor technology. The strategy
consists of a set of CMOS “building block” test structures, a
matrix of these test structures, electrical characterization parameters, ESD
metrics, a standardized failure criteria, and an extraction and testing procedure

Title: Analysis of snubber-clamped diode-string mixed voltage interface ESD
protection network for advanced microprocessors
Author Voldman, S. H.
Gerosa, G.
Gross, V. P.
Dickson, N. A. Dickson N.
Furkay, S. A. Furkay S.
Slinkman, J. A. Slinkman J.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings, 1995
Year: 1995
Abstract: A novel snubber-clamped diode-string ESD protection circuit for
mixed voltage interface microprocessor applications is described. Analytical
models, circuit simulation, electrical characterization, ESD electrothermal
simulation, ESD test data, and an ESD analytical failure model are shown for
shallow trench isolation (STI) and LOCOS CMOS technologies

				
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