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Title: Understanding the optimization of sub-45nm FinFET devices for ESD
applications
Author: Tremouilles, D.
Thijs, S.
Russ, C.
Schneider, J. A. Schneider J.
Duvvury, C. A. Duvvury C.
Collaert, N. A. Collaert N.
Linten, D. A. Linten D.
Scholz, M. A. Scholz M.
Jurczak, M. A. Jurczak M.
Gossner, H. A. Gossner H.
Groeseneken, G. A. Groeseneken G.
Conference Name: 29th Electrical Overstress/Electrostatic Discharge
Symposium (EOS/ESD), 2007. EOS/ESD
Year:2007
Abstract: ESD performance of advanced FinFETs shows a delicate sensitivity
to device layout and to processing. Thermal issues are experimentally
correlated to gate length, fin width, electrical operation mode and are
investigated by TCAD simulation. S/D implant conditions, silicide blocking, and
selective epitaxial growth are studied. Reasonable ESD performance is
demonstrated while margins between success and failure seem to be very
narrow.

Title: ESD Evaluation of the Emerging MuGFET Technology
Author: Russ, C.
Gossner, H.
Schulz, T.
Chaudhary, N. A. Chaudhary N.
Weize Xiong, A. Weize Xiong
Marshall, A. A. Marshall A.
Duvvury, C. A. Duvvury C.
Schrufer, K. A. Schrufer K.
Rinn Cleavelin, C. R. A. Rinn Cleavelin C. R.
Jounal: Device and Materials Reliability, IEEE Transactions on
Year:2007
Abstract: Electrostatic discharge (ESD) characteristics of fully depleted FinFET
devices are presented and compared to planar structures manufactured in the
same multiple-gate FET Technology. FinFET-type MOS devices in breakdown
mode are found to show an unprecedented sensitivity to ESD stress, while
planar devices and FinFET gated diodes perform reasonably and with -
characteristics beneficial for ESD protection.
Title: CDM peak current variations and impact upon CDM performance
thresholds
Author: Jahanzeb, Agha
Yen-Yi, Lin
Marum, Steve
Schichl, Joe A. Schichl Joe
Charvaka Duvvury, A. Charvaka Duvvury
Conference Name: 29th Electrical Overstress/Electrostatic Discharge
Symposium (EOS/ESD), 2007. EOS/ESD
Year:2007
Abstract: Effect of device size on the peak CDM current is discussed. The
current increases monotonically for small packages and then saturates for
sizes larger than 1000 mm<sup>2</sup>. Size of the charge plate of the CDM
tester contributed to this behavior. The current was not found to be constant
across the package. Instead, it showed maximum value in the middle and
minimum at the outer edge. An unexpected variation in CDM current is also
reported for long pulse sequences.

Title: Impact of scaling on the high current behavior of RF CMOS technology
Author: Boselli, G.
Reddy, V.
Duvvury, C.
Journal: Device and Materials Reliability, IEEE Transactions on
Year:2004
Abstract: In this paper, the impact of the starting material resistivity on the
electrostatic discharge (ESD), latch-up, and injection induced breakdown
voltage (BVii) sensitivity will be investigated for a sub-100-nm fully silicided
CMOS technology for low-power and RF applications. The mechanisms
through which the increase of the substrate spreading resistance enhances
the uniformity of the ESD current in nMOS-based protection methods will be
investigated in detail. Tradeoffs between ESD, latch-up, and BVii will be
addressed as well.

Title: Impact of gate-to-contact spacing on ESD performance of salicided deep
submicron NMOS transistors
Author: Kwang-Hoon, Oh
Duvvury, C.
Banerjee, K.
Dutton, R. W. A. Dutton R. W.
Journal: Device and Materials Reliability, IEEE Transactions on
Year:2002
Abstract: Electrostatic discharge (ESD) failure threshold of NMOS transistors
is known to degrade with the use of silicided diffusions owing to insufficient
ballast resistance, making them susceptible to current localization, which leads
to early ESD failure. In general, the gate-to-contact spacing of salicided
devices is known to have little impact on their ESD strength. However,
experimental results presented in this paper show that the ESD strength
depends on the gate-to-contact spacing independent of the silicided process.
Subsequently, a detailed investigation of the influence of gate-to-source and
gate-to-drain contact spacings is carried out for a salicided 0.13-/spl mu/m
technology which provides new insight into the behavior of deep submicron
ESD protection devices. It is shown that the reduction in current localization
and increase in the power dissipating volume with increase in the
gate-to-contact spacings are the primary causes of this improvement, which
implies that even for silicided processes, the gate-to-contact spacing should be
carefully engineered for efficient and robust ESD protection designs.

Title: Electrostatic discharge (ESD) technology benchmarking strategy for
evaluating ESD robustness of CMOS technologies
Author: Voldman, S.
Anderson, W.
Ashton, R.
Chaine, M. A. Chaine M.
Duvvury, C. A. Duvvury C.
Maloney, T. A. Maloney T.
Worley, E. A. Worley E.
Conference Name: Integrated Reliability Workshop Final Report, 1998 IEEE
International
Year:1998
Abstract: This paper describes an ESD technology benchmarking strategy for
evaluating the ESD robustness of a semiconductor technology. The strategy
consists of a set of CMOS &ldquo;building block&rdquo; test structures, a
matrix of these test structures, electrical characterization parameters, ESD
metrics, a standardized failure criteria, and an extraction and testing procedure

Title: A simulation study of HBM failure in an internal clock buffer and the
design issues for efficient power pin protection strategy
Author: Puvvada, V.
Duvvury, C.
Conference Name: Int Electrical Overstress/Electrostatic Discharge
Symposium Proceedings, 1998
Year:1998
Abstract: This paper presents the use of circuit simulations in understanding of
the internal ESD (electrostatic discharge) failure observed in a 0.6 &mu;m
CMOS technology product chip. Simulation of the ESD current paths near the
V<sub>dd</sub> pin are performed and the cause of ESD failure is identified
using a circuit simulator that includes the MOS snapback models. These
simulations are used to suggest issues to be considered in design of protection
circuits to avoid this type of internal ESD failure

Title: Design methodology and optimization of gate-driven NMOS ESD
protection circuits in submicron CMOS processes
Author: Chen, J. Z.
Amerasekera, E. A.
Duvvury, C.
Journal: Electron Devices, IEEE Transactions on
Year:1998
Abstract: This paper describes the design methodology for gate driven NMOS
ESD protection in submicron CMOS processes. A new PNP Driven NMOS
(PDNMOS)-protection scheme is presented. Without requiring any additional
process steps or introducing any additional impedance in signal path, the
PDN-MOS is effective even for small analog/mixed-signal designs. SPICE
simulations are used to optimize the design. High ESD performance of the
PDNMOS protection in both nonsilicided and silicided submicron processes is
demonstrated in this work

Title Modeling MOS snapback and parasitic bipolar action for circuit-level ESD
and high-current simulations
Author: Amerasekera, A.
Mi-Chang, Chang
Duvvury, C.
Ramaswamy, S. A. Ramaswamy S.
Journal: Circuits and Devices Magazine, IEEE
Year:1997
Abstract:The design and optimization of ESD protection circuits is greatly
enhanced by the ability to perform circuit-level simulations of the protection
circuits and the I/O buffers. Most available simulators do not cover the high
current region of the circuit operation, but still enable an approximate analysis
to be made of the behaviour under ESD conditions. In this article, a description
of the behaviour of the MOS device in the high current regime is presented
together with the model equations governing that behaviour. The equations
have been implemented into a SPICE circuit simulator, and the experimental
and simulation results are given. A simple parameter extraction methodology
is presented that uses the terminal currents from a single MOS DC I-V curve to
obtain all the MOS and bipolar parameters required for the model

Title ESD design for deep submicron SOI technology [NMOS transistor]
Author: Duvvury, C.
Amerasekera, A.
Joyner, K.
Ramaswamy, S. A. Ramaswamy S.
Young, S. A. Young S.
Conference Name: VLSI Technology, 1996. Digest of Technical Papers. 1996
Symposium on
Year:1996
Abstract: This paper establishes the critical ESD design issues for a partially
depleted 0.35 &mu;m SOI process. Through device analysis we show for the
first time that the gate bias of an NMOS during ESD plays a critical role in
reducing channel heating and in achieving good protection levels for both
positive and negative stress polarities. With an optimum design window, we
demonstrate greater than &plusmn;2 kV ESD performance with no additional
process steps

Title: Advanced CMOS protection device trigger mechanisms during CDM
Author: Duvvury, C.
Amerasekera, A.
Journal: Components, Packaging, and Manufacturing Technology, Part C,
IEEE Transactions on [see also Components, Hybrids, and Manufacturing
Technology, IEEE Transactions on]
Year:1996
Abstract: T The charged device model (CDM) is now considered to be an
important stress model for defining electrostatic discharge (ESD) reliability of
integrated circuit (IC) chips. This paper examines the CDM performance for
three different advanced protection devices in an 0.35-&mu;m LDD
complementary metal-oxide semiconductor (CMOS) technology. Through
failure analysis and device simulations, the behavior of these protection
devices during the CDM event is investigated. The results will enable devices
to be designed for improved CDM protection levels

Title EOS/ESD reliability of deep sub-micron NMOS protection devices
Author: Ramaswamy, S.
Duvvury, C.
Sung-Mo, Kang
Conference Name: Reliability Physics Symposium, 1995. 33rd Annual
Proceedings., IEEE International
Year:1995
Abstract: We have identified new failure mechanisms in EOS/ESD protection
circuits for a 0.35 &mu;m technology and investigated the effect of process
variations on these circuits. We present strategies to improve the performance
of these circuits and prevent premature failure of the devices

Title Substrate triggering and salicide effects on ESD performance and
protection circuit design in deep submicron CMOS processes
Author: Amerasekera, A.
Duvvury, C.
Reddy, V.
Rodder, M. A. Rodder M.
Conference Name: Electron Devices Meeting, 1995., International
Year:1995
Abstract: The effect of salicides and the influence of the local substrate
potential on ESD performance of deep submicron nMOS transistors have been
studied. It is shown that salicidation causes a strong dependence of ESD
performance on effective channel length in these devices. Salicides also
impact the behavior of the lateral npn parasitic bipolar transistor by affecting
the emitter efficiency. A higher local substrate potential has been shown to
have a positive impact on ESD performance. Based on these results we have
designed and demonstrated a substrate triggered nMOS protection circuit
which provides &gt;2 kV ESD performance in a fully salicided process

Title The impact of technology scaling on ESD robustness and protection
circuit design
Author: Amerasekera, A.
Duvvury, C.
Journal: Components, Packaging, and Manufacturing Technology, Part A,
IEEE Transactions on [see also Components, Hybrids, and Manufacturing
Technology, IEEE Transactions on]
Year:1995
Abstract: The trends in ESD robustness as a function of technology scaling, for
feature sizes down to 0.25 &mu;m, have been experimentally determined
using single finger nMOS transistors and full ESD protection circuits. It is
shown that as feature sizes are reduced, good ESD performance can be
obtained provided the negative effects of the shallower junctions are offset by
the positive effects of the reduction in the effective channel lengths. Hence,
processes and protection circuits with feature sizes as small as 0.25 &mu;m
can be developed without degrading ESD robustness

Title Device integration for ESD robustness of high voltage power MOSFETs
Author: Duvvury, C.
Rodriguez, J.
Jones, C.
Smayling, M. A. Smayling M.
Conference Name: Electron Devices Meeting, 1994. Technical Digest.,
International
Year:1994
Abstract: The ESD robustness of a power MOSFET device is addressed in this
paper. It is shown that by a novel device integration of the power output
transistor with SCR, the ESD performance can be improved from less than 2
kV to greater than 6 kV. This is accomplished with no impact on the transistor
performance or its application in circuit design
Title Reliability design of <e1>p</e1><sup>+</sup>-pocket implant LDD
transistors
Author: Duvvury, C.
Holloway, T. C.
Paradis, D.
Duong, A. K. A. Duong A. K.
Conference Name: Electron Devices Meeting, 1990. Technical Digest.,
International
Year:1990
Abstract: It is shown that the reliability design of p<sup>+</sup>-pocket LDD
(lightly doped drain) transistors is dependent on the pocket implant energy,
which controls the positions of the peak field and breakdown regions. A
optimum of 60 keV implant in this example gives fairly good ESD (electrostatic
discharge) reliability and excellent hot carrier immunity, while preventing
transistor punchthrough effects. It is also shown that it is the electric field
gradient at the surface rather than the substrate current level that can have a
major impact on hot carrier degradation. In fact, for future VLSI transistors this
technique can be used to improve the hot carrier reliability. Finally, further
insight into the poor ESD performance of LDD transistors is obtained which
indicates that the junction breakdown design is important for the ESD
performance of LDD or DDD (double diffused drain) transistors

Title ESD phenomena in graded junction devices
Author: Duvvury, C.
Rountree, R. N.
Stiegler, H. J.
Polgreen, T. A. Polgreen T.
Corum, D. A. Corum D.
Conference Name: Electron Devices Meeting, 1990. Technical Digest.,
International
Year:1989
Abstract: The current very large-scale integration (VLSI) chips for
sub-2-&mu;m processes use some form of graded junction devices for process
reliability. Electrostatic discharge (ESD) performance for these graded junction
processes is examined by studying the process variations. The results show
that the ESD protection level can be optimized without significantly
compromising the hot carrier reliability or the circuit drive current. The unique
failure modes in these devices are also discussed. The results are supported
by transient thermal analysis simulations

Title Internal chip ESD phenomena beyond the protection circuit
Author Duvvury, C.
Rountree, R. N.
Adams, O.
Journal: Electron Devices, IEEE Transactions on
Year:1988
Abstract: Input/output electrostatic discharge (ESD) circuit requirements call
for good protection of the pin with respect to both the ground and the power
bus pins. Although effective protection can be designed at the pin many cases
of damage phenomena are known to occur internal to the chip beyond the
protection circuit. Here, the issues of protection between
<e1>V</e1><sub>DD</sub> and <e1>V</e1><sub>SS</sub> are discussed
first. This is followed by examples of how protection circuit performance can be
sensitive to internal chip layout, independent of its effective design. Several
illustrative actual case studies are reported to emphasize the internal chip ESD
phenomena and their adverse effects

Title Leakage current degradation in n-MOSFETs due to hot-electron stress
Author Duvvury, C.
Redwine, D. J.
Stiegler, H. J.
Journal: Electron Devices, IEEE Transactions on
Year:1988
Abstract: Input/output electrostatic discharge (ESD) circuit requirements call
for good protection of the pin with respect to both the ground and the power
bus pins. Although effective protection can be designed at the pin many cases
of damage phenomena are known to occur internal to the chip beyond the
protection circuit. Here, the issues of protection between
<e1>V</e1><sub>DD</sub> and <e1>V</e1><sub>SS</sub> are discussed
first. This is followed by examples of how protection circuit performance can be
sensitive to internal chip layout, independent of its effective design. Several
illustrative actual case studies are reported to emphasize the internal chip ESD
phenomena and their adverse effects

Title A High Gain and Low Supply Voltage LNA for the Direct Conversion
Application With 4-KV HBM ESD Protection in 90-nm RF CMOS
Author Chang, C. P.
Hou, J. A.
Su, J.
Chen, C. W. A. Chen C. W.
Liou, T. S. A. Liou T. S.
Wong, S. C. A. Wong S. C.
Wang, Y. H. A. Wang Y. H.
Journal: Microwave and Wireless Components Letters, IEEE
Year:2006
Abstract: A 2.4-GHz low noise amplifier (LNA) for the direct conversion
application with high power gain, low supply voltage and plusmn4 KV human
body model (HBM) electrostatic discharge (ESD) protection level implemented
by a 90-nm RF CMOS technology is demonstrated. At 12.9 mA of current
consumption with a supply voltage of 1.0 V, the LNA delivers a power gain of
21.9 dB and the noise figure (NF) of 3.2 dB, while maintaining the input and
output return losses below -11 dB and -18.3 dB, respectively. The power gain
and NF are only 0.2 dB lower and 0.64 dB higher than those of LNA without
ESD protection

Title Full Parasitic Capacitance Model of Diode-Class ESD Protection
Structures for Mix-Signal and RF ICs
Author Wang, Yuan
Jia, Song
Chen, Zhongjian
Ji Lijiu, A. Ji Lijiu
Conference Name: Electron Devices and Solid-State Circuits, 2005 IEEE
Conference on
Year:2005
Abstract: A full parasitic capacitance model of diode-class ESD structures is
presented in this paper, including not only the reversed-bias capacitance
model in the circuit normal operation but the forward-bias capacitance model
under the ESD stress. This model successfully calculates the ESD-induced
capacitances which degrade the high-speed mix-signal and RF IC
performances, and also deals with the puzzle why diode-class structures have
a low discharge level with a small turn-on resistance. And a novel parameter
CESDV, which is named as the parasitic capacitance unit kV ESD level for the
ESD device, is also proposed. The experimental results imply that the
MOS-bounded diode has a CESDV about 15fF/kV, far smaller than the normal
diode about 30fF/kV. It is shown that the MOS-bounded diode is an
appropriate choice for the high-speed mix-signal and RF ICs ESD protection.

Title A review on RF ESD protection design
Author Wang, A. Z. H.
Haigang, Feng
Rouying, Zhan
Haolu Xie, A. Haolu Xie
Guang Chen, A. Guang Chen
Qiong Wu, A. Qiong Wu
Guan, X. A. Guan X.
Zhihua Wang, A. Zhihua Wang
Chun Zhang, A. Chun Zhang
Journal: Electron Devices, IEEE Transactions on
Year:2005
Abstract: Radio frequency (RF) electrostatic discharge (ESD) protection
design emerges as a new challenge to RF integrated circuits (IC) design,
where the main problem is associated with the complex interactions between
the ESD protection network and the core RFIC circuit being protected. This
paper reviews recent development in RF ESD protection circuit design,
including mis-triggering of RF ESD protection structures, ESD-induced
parasitic effects on RFIC performance, RF ESD protection solutions, as well as
characterization of RF ESD protection circuits.

Title RFCMOS ESD protection and reliability
Author Natarajan, M. I.
Natarajan, M. I.
Thijs, S.
Jansen, P.
Tremouilles, D. A. Tremouilles D.
Jeamsaksiri, W. A. Jeamsaksiri W.
Decoutere, S. A. Decoutere S.
Linten, D. A. Linten D.
Nakaie, T. A. Nakaie T.
Sawada, M. A. Sawada M.
Hasebe, T. A. Hasebe T.
Groeseneken, G. A. Groeseneken G.
Conference Name: Physical and Failure Analysis of Integrated Circuits, 2005.
IPFA 2005. Proceedings of the 12th International Symposium on the
Year:2005
Abstract: This paper addresses the ESD reliability issues in RFICs, focusing
on the technology impact on the device and design. We also present the basic
RF ESD protection methods used in industry. Presents the general topology of
a 5 GHz LNA, which is protected using several ESD protection methodologies,
and describes the 90 nm CMOS process technology used for the fabrication of
the LNA. The measurement procedures used for the evaluation of stand-alone
devices and LNAs are described. The ESD performance of standard ESD
protection devices is reviewed and presents results and discussions on the
ESD reliability of various ESD protection methods employed from the device
point of view, followed by an outlook on the future RF ESD challenges, and
conclusions.

Title ESD protection design considerations for InGaP/GaAs HBT RF power
amplifiers
Author Ma, Y.
Ma, Y.
Li, G. P.
Journal: Microwave Theory and Techniques, IEEE Transactions on
Year:2005
Abstract: In order to design a robust electrostatic discharge (ESD) protected
RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device
vulnerability to ESD events in both active transistors and passive components
of the HBT technology is presented in this paper. The results include not only
the intrinsic HBT's ESD robustness performance, but also its dependence on
device layout, ballast resistor, and process. Acknowledging the ESD
constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power
amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip
ESD protection circuit that has a low loading capacitance of less than 0.1 pF
and that does not degrade RF and output power performance is developed for
wireless local area network application. A diode triggered Darlington pair is
implemented as the ESD protection circuit instead of the traditional diode
string. Its operation principle, ESD protection performance, and PA
performance are also illustrated in this paper.

Title A new low-parasitic polysilicon SCR ESD protection structure for RF ICs
Author Haolu, Xie
Haigang, Feng
Rouying, Zhan
Wang, A. A. Wang A.
Rodriguez, D. A. Rodriguez D.
Rice, D. A. Rice D.
Journal: Electron Device Letters, IEEE
Year:2005
Abstract: Robust low-parasitic electrostatic discharge (ESD) protection is
highly desirable for RF ICs. This letter reports design of a new low-parasitic
polysilicon silicon controlled rectifier (SCR) ESD protection structure designed
and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology.
The concept was verified by simulation and experiment with the results
showing that the new structure has much lower parasitic capacitance (C/sub
ESD/) and higher F-factor than that of other ESD protection devices. A small
polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high
human body model ESD protection of 3.2 kV while featuring a high F-factor of
/spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR
ESD protection structure seems to be an attractive solution to high-GHz RF
ICs.

Title Noise analysis of ESD structures and impacts on a fully-integrated
5.5GHz LNA in 0.18/spl mu/m SiGe BiCMOS
Author Guang, Chen
Haigang, Feng
Wang, A.
Yuhua Cheng, A. Yuhua Cheng
Conference Name: Microwave Conference, 2005 European
Year:2005
Abstract: ESD-induced parasitics are critical to RF ICs. This paper reports the
first quantitative study of noises of ESD protection structures and their
influences on RF ICs. Noise figures (NF) of typical ESD structures were
characterized and their impact on a single-chip 5.5GHz LNA circuit was
investigated. The design was implemented in a 0.18/spl mu/m SiGe BiCMOS.
Measurement shows substantial degradation in NF of LNA due to ESD noises
and a practical selection criterion in designing RF IC with ESD structures is
provided.

Title Protecting RF ICs: a new reliability challenge
Author Wang, A.
Conference Name: Radio Science Conference, 2004. Proceedings. 2004
Asia-Pacific
Year:2004
Abstract: The paper reviews current developments in designing and
characterizing on-chip ESD (electrostatic discharge) protection circuits for RF
ICs. ESD protection basics, key issues in RF ESD protection, design methods,
RF ESD protection evaluation techniques and RF ESD protection solutions are
discussed.

Title A review of RF ESD protection design [RF IC applications]
Author Wang, A.
Conference Name: Microelectronics and Electron Devices, 2004 IEEE
Workshop on
Year:2004
Abstract: This paper reviews design and analysis of on-chip ESD (electrostatic
discharge) protection circuits for RF ICs. ESD protection basics, key issues in
RF ESD protection, design methods, RF ESD protection evaluation techniques
and RF ESD protection solutions are discussed.

Title A review of RF ESD protection design [RF IC applications]
Author Wang, A.
Conference Name: Microelectronics and Electron Devices, 2004 IEEE
Workshop on
Year:2004
Abstract: This paper reviews design and analysis of on-chip ESD (electrostatic
discharge) protection circuits for RF ICs. ESD protection basics, key issues in
RF ESD protection, design methods, RF ESD protection evaluation techniques
and RF ESD protection solutions are discussed.

Title Title A review of RF ESD protection design [RF IC applications]
Author Wang, A.
Conference Name: Microelectronics and Electron Devices, 2004 IEEE
Workshop on
Year:2004
Abstract: This paper reviews design and analysis of on-chip ESD (electrostatic
discharge) protection circuits for RF ICs. ESD protection basics, key issues in
RF ESD protection, design methods, RF ESD protection evaluation techniques
and RF ESD protection solutions are discussed.
Author Natarajan, M. I.
Thijs, S.
Jansen, P.
Tremouilles, D. A. Tremouilles D.
Jeamsaksiri, W. A. Jeamsaksiri W.
Decoutere, S. A. Decoutere S.
Linten, D. A. Linten D.
Nakaie, T. A. Nakaie T.
Sawada, M. A. Sawada M.
Hasebe, T. A. Hasebe T.
Groeseneken, G. A. Groeseneken G.
Conference Name: Physical and Failure Analysis of Integrated Circuits, 2005.
IPFA 2005. Proceedings of the 12th International Symposium on the
Year:2005
Abstract: This paper addresses the ESD reliability issues in RFICs, focusing
on the technology impact on the device and design. We also present the basic
RF ESD protection methods used in industry. Presents the general topology of
a 5 GHz LNA, which is protected using several ESD protection methodologies,
and describes the 90 nm CMOS process technology used for the fabrication of
the LNA. The measurement procedures used for the evaluation of stand-alone
devices and LNAs are described. The ESD performance of standard ESD
protection devices is reviewed and presents results and discussions on the
ESD reliability of various ESD protection methods employed from the device
point of view, followed by an outlook on the future RF ESD challenges, and
conclusions.

Title Modeling ESD protection
Author Mohan, N.
Kumar, A.
Journal: Potentials, IEEE
Abstract: This work presents the modeling and simulation of ESD circuit design
protection. The electrostatic discharge (ESD) is a charge rebalancing process
between two adjacent ICs. The ESD can cause IC failure during the
manufacturing, the testing, the handling and the assembly of integrated circuits
(ICs). ESD protection design methodology needs to be as systematic and
transferable as possible. The empirical, trial and error method for creating ESD
protection schemes is based on fabricating several test protection structures,
gradually applying increasing voltage pulses and then measuring the
functionality of the protection structures. This method is time consuming and
destructive in nature. The model could be used to optimize the ESD circuit's
design and predict its protection performance. A combination of bias
conditions and layout parameters could maximize the ESD robustness device.
This optimization can be achieved by developing simulation tools for ESD
circuits. ESD is a phenomenon that causes reliability problems and even
permanent damages to the IC since the goal is to find the voltage and the
current limits before the device fails permanently.

Title ESD protection design considerations for InGaP/GaAs HBT RF power
amplifiers
Author Ma, Y.
Li, G. P.
Journal: Microwave Theory and Techniques, IEEE Transactions on
Year:2005
Abstract: In order to design a robust electrostatic discharge (ESD) protected
RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device
vulnerability to ESD events in both active transistors and passive components
of the HBT technology is presented in this paper. The results include not only
the intrinsic HBT's ESD robustness performance, but also its dependence on
device layout, ballast resistor, and process. Acknowledging the ESD
constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power
amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip
ESD protection circuit that has a low loading capacitance of less than 0.1 pF
and that does not degrade RF and output power performance is developed for
wireless local area network application. A diode triggered Darlington pair is
implemented as the ESD protection circuit instead of the traditional diode
string. Its operation principle, ESD protection performance, and PA
performance are also illustrated in this paper.

Title A new low-parasitic polysilicon SCR ESD protection structure for RF ICs
Author Haolu, Xie
Haigang, Feng
Rouying, Zhan
Wang, A..
Rodriguez, D.
Rice, D.
Journal: Electron Device Letters, IEEE
Year:2005
Abstract: Robust low-parasitic electrostatic discharge (ESD) protection is
highly desirable for RF ICs. This letter reports design of a new low-parasitic
polysilicon silicon controlled rectifier (SCR) ESD protection structure designed
and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology.
The concept was verified by simulation and experiment with the results
showing that the new structure has much lower parasitic capacitance (C/sub
ESD/) and higher F-factor than that of other ESD protection devices. A small
polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high
human body model ESD protection of 3.2 kV while featuring a high F-factor of
/spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR
ESD protection structure seems to be an attractive solution to high-GHz RF
ICs.

Title Noise analysis of ESD structures and impacts on a fully-integrated
5.5GHz LNA in 0.18/spl mu/m SiGe BiCMOS
Author Guang, Chen
Haigang, Feng
Wang, A.
Yuhua Cheng, A. Yuhua Cheng
Conference Name: Microwave Conference, 2005 European
Year:2005
Abstract: ESD-induced parasitics are critical to RF ICs. This paper reports the
first quantitative study of noises of ESD protection structures and their
influences on RF ICs. Noise figures (NF) of typical ESD structures were
characterized and their impact on a single-chip 5.5GHz LNA circuit was
investigated. The design was implemented in a 0.18/spl mu/m SiGe BiCMOS.
Measurement shows substantial degradation in NF of LNA due to ESD noises
and a practical selection criterion in designing RF IC with ESD structures is
provided.

Title Using device simulations to optimize ESD protection circuits
Author Fankhauser, B.
Deutschmann, B.
Conference Name: Electromagnetic Compatibility, 2004. EMC 2004. 2004
InternationalSymposium on
Year:2004
Abstract: As integrated circuits are getting more and more complex, they are
becoming increasingly vulnerable to transient disturbances (e.g. to
electrostatic discharges, ESD). The development approaches for on-chip ESD
protection devices often have a very experimental character: ESD designers
make use of trial-and-error procedures to evaluate many variations of
protection structures. This methodology is very time-consuming, as it can
require several redesigns to find proper ESD protection devices for a given
process technology. Also, from one process generation to the next, already
well-established ESD structures may completely change their ESD behavior.
Now, more sophisticated design approaches make use of TCAD-based
techniques. Simulations of ESD circuits provide a deeper understanding of the
functionality of their protection behavior. In this paper we show how such
simulation techniques have been successfully used to design an efficient
trigger-circuit for SCR, a specific class of very powerful ESD protection
devices.
Title Study on two types of commercial ESD simulators
Author Ruan, Xiaofen
Zhang, Xijun
Wu, Zhancheng
Wang Shuping, A. Wang Shuping
Conference Name: Environmental Electromagnetics, 2003. CEEM 2003.
Proceedings. Asia-Pacific Conference on
Year:2003
Abstract: In this paper, the performances of two types of ESD simulators
(ESS-200AX made in Noiseken and NSG435 made in Schaffner) are studied,
and ESD immunity experiments of a single chip microcomputer (SCM) system
are made. The experimental results show that the differences between two
simulators yield inconsistent test results though they both comply with the
IEC61000-4-2 ESD standard. Therefore, besides the ESD current waveform,
the relevant IEC61000-4-2 ESD standard should specify the discharge current
derivative, related electromagnetic field in detail, and give unified
specifications for the construction and configuration of ESD simulators.

Title Electron cloud diagnostics in use at the Los Alamos PSR
Author Macek, R. J.
Browman, A.
Borden, M.
Fitzgerald, D. A. Fitzgerald D.
Wang, T. S. A. Wang T. S.
Zaugg, T. A. Zaugg T.
Harkay, K. A. Harkay K.
Rosenberg, R. A. Rosenberg R.
Conference Name: Particle Accelerator Conference, 2003. PAC 2003.
Proceedings of the
Year:2003
Abstract: A variety of electron cloud diagnostics have been deployed at the
Los Alamos Proton Storage Ring (PSR) to detect, measure, and characterize
the electron cloud generated in this high intensity, long bunch accumulator ring.
These include a version of the ANL-developed retarding field analyzers (RFA)
augmented with LANL-developed electronics, a variant of the RFA denoted as
the electron sweeping diagnostic (ESD), biased collection plates, and gas
pulse measuring devices. The designs and experience with the performance
and applicability to PSR are discussed.

Title Electron cloud diagnostics in use at the Los Alamos PSR
Author Macek, R. J.
Browman, A.
Borden, M.
Fitzgerald, D. A. Fitzgerald D.
Wang, T. S. A. Wang T. S.
Zaugg, T. A. Zaugg T.
Harkay, K. A. Harkay K.
Rosenberg, R. A. Rosenberg R.
Conference Name: Particle Accelerator Conference, 2003. PAC 2003.
Proceedings of the
Year:2003
Abstract: A variety of electron cloud diagnostics have been deployed at the
Los Alamos Proton Storage Ring (PSR) to detect, measure, and characterize
the electron cloud generated in this high intensity, long bunch accumulator ring.
These include a version of the ANL-developed retarding field analyzers (RFA)
augmented with LANL-developed electronics, a variant of the RFA denoted as
the electron sweeping diagnostic (ESD), biased collection plates, and gas
pulse measuring devices. The designs and experience with the performance
and applicability to PSR are discussed.

Title An express diagnostic method for ESD simulators and standardized ESD
test stations
Author Kocharyan, V.
Tolman, D.
Conference Name: Electromagnetic Compatibility, 2003 IEEE International
Symposium on
Year:2003
Abstract: The management of ESD simulators and standardized ESD test
stations to assure quality test results continues to be a major concern for test
houses. Early detection of malfunctioning ESD equipment is possible if a
day-to-day check is performed. The standard system for verification of ESD
simulators is large, expensive and not practical for an everyday check. This
paper describes the express diagnostic method aimed to locate the problems
with either the ESD simulator or the test station. A 100MHz....500MHz
bandwidth oscilloscope can be used to measure the quasi-electrostatic field of
the horizontal coupling plane after the package of discharges has been applied.
The malfunction of an ESD simulator and/or test station is discovered as a
deviation from the baseline measurements, which are taken immediately after
calibration. This method exposes any changes of the indicated discharge
voltage or the horizontal coupling plane bleeder resistor impedance as well as
changes in the discharge networks of ESD simulators. The oscillograms and
the statistical analysis of data are presented in this paper, which support the
claims that this method can assists in detection of potential problems of ESD
equipment.

Title A systematic study of ESD protection structures for RF ICs
Author Guang, Chen
Haigang, Feng
Wang, A.
Conference Name: Radio Frequency Integrated Circuits (RFIC) Symposium,
2003 IEEE
Year:2003
Abstract: We report the first systematic investigation of various ESD protection
structures, e.g., diodes, ggNMOS, gcNMOS, ggPMOS, SCR and multi-mode
SCR's in a 0.35 /spl mu/m production BiCMOS technology, for RF ICs up to
100 GHz by mixed-mode ESD simulation. Typical circuit parameters for RF
ICs, e.g., parasitic resistances, capacitances, noise figures and S-parameters
were studied. The comparison study suggests that compact SCR-type
structures and diode strings may be solutions to RF ESD protection.

Title A systematic study of ESD protection structures for RF ICs
Author Guang, Chen
Haigang, Feng
Wang, A.
Conference Name: Radio Frequency Integrated Circuits (RFIC) Symposium,
2003 IEEE
Year:2003
Abstract: We report the first systematic investigation of various ESD protection
structures, e.g., diodes, ggNMOS, gcNMOS, ggPMOS, SCR and multi-mode
SCR's in a 0.35 /spl mu/m production BiCMOS technology, for RF ICs up to
100 GHz by mixed-mode ESD simulation. Typical circuit parameters for RF
ICs, e.g., parasitic resistances, capacitances, noise figures and S-parameters
were studied. The comparison study suggests that compact SCR-type
structures and diode strings may be solutions to RF ESD protection.

Title A study of parasitic effects of ESD protection on RF ICs
Author Ke, Gong
Haigang, Feng
Rouying, Zhan
Wang, A. Z. H. A. Wang A. Z. H.
Conference Name: Microwave Theory and Techniques, IEEE Transactions on
Year:2003
Abstract: This paper presents a comprehensive study on influences of on-chip
electro-static discharge (ESD) protection structures on performance of the
circuits being protected. Two novel compact low-parasitic ESD structures were
designed for RF and mixed-signal (MS) integrated circuits. Parasitic models of
the ESD structures are extracted. RF building-block circuits, including a
low-power high-speed op amp and a fully integrated 2.4-GHz low-noise
amplifier were designed in 0.18/0.35-&mu;m technologies. Investigation of
performance of these circuits under influences of the two new ESD protection
structures and traditional MOS ESD protection device, in both copper and
aluminum interconnects, demonstrated that significant circuit performance
degradation (~30%) occur when using NMOS ESD protection in Al technology,
which recovered substantially (~80%) when using low-parasitic ESD protection
in Cu technology. This work indicates that the ESD-to-circuit influence is
inevitable and substantial. Therefore, novel low-parasitic ESD protection
solution is essential to maintaining both circuit functionality and ESD
robustness in RF and MS applications

Title Circular under-pad multiple-mode ESD protection structure for ICs
Author Feng, H. G.
Zhan, R. Y.
Wu, Q.
Chen, G. .
Wang, A. Z.
Journal: Electronics Letters
Year:2002
Abstract: A novel circular pad-oriented low-parasitic all-mode electrostatic
discharge (ESD) protection structure is designed in BiCMOS for RF and
mixed-signal (MS) ICs, featuring tunable triggering, low voltage clamping (~2
V), low discharge impedance (~&Omega;) and low leakage current (~pA). It
consumes limited silicon and achieves 14 kV ESD protection

Title Simulation models of ESD event in ICs
Author Jiang, Lei
Yang, Xing
Wang, Jiaji
Conference Name: Solid-State and Integrated-Circuit Technology, 2001.
Proceedings. 6th International Conference on
Year:2001
Abstract: ESD protection becomes more and more prevalent with the
development of deep sub-micron technology. ESD simulation with right models
can reduce the design and test cycle of ESD protection circuit, and optimize for
ESD robustness as well as device performance. Several simulation models
and practical examples are described to show the application of ESD
simulation in this article. Integrated models that combine process, circuit and
device simulation are the trends of development.

Title Noise-constrained design of reliable power networks for mixed-power
supply systems
Author Jaesik, Lee
Sung-Mo, Kang
Conference Name: Solid-State Circuits Conference, 2001. ESSCIRC 2001.
Proceedings of the 27th European
Year:2001
Abstract: Electrostatic discharge (ESD) accounts for over 30% chip failure that
occurs during VLSI chip manufacturing. On-chip ESD network should be able
to withstand the heating effects, sink the large currents during the ESD event
and not be damaged by the ensuing high electric fields. The ways focused on
ESD reliability may cause noise isolation concern among multiple power
supplies. Our experimental results show that the noise coupled through ESD
networks significantly degrades the performance of mixed-signal systems.
This coupling noise cannot be easily suppressed because reducing the noise
usually leads to the degradation of ESD performance. This paper presents a
new method for designing noise-constrained ESD networks while improving
the reliability. This idea features a common electrostatic discharge line (CEDL)
with utilizing the estimation of maximum power/ground (PG) noise in digital
circuits in the ESD network design. Experimental results demonstrate the
potential for alleviating a tradeoff between ESD robustness and noise isolation
in mixed-power supply networks.

Title An ESD protection circuit for mixed-signal ICs
Author Haigang, Feng
Ke, Gong
Wang, A. Z.
Conference Name: Custom Integrated Circuits, 2001, IEEE Conference on.
Year:2001
Abstract: A new ESD (electrostatic discharge) protection circuit was designed
and implemented in commercial BiCMOS. One such ESD unit is adequate for
each I/O pin to survive ESD stressing of all modes. This novel ESD circuit
features adjustable low-trigger-voltage, symmetric active discharge channels
in all directions, fast response, and high ESD performance/area ratio. It passed
14 kV HBM and 15 kV airgap IEC ESD zapping. This compact ESD structure
minimizes parasitic effects, which is desired for mixed-signal and RF ICs

Title Investigation on different ESD protection strategies devoted to 3.3 V RF
applications (2 GHz) in a 0.18 &mu;m CMOS process
Author Pichier, C.
Salome, P.
Mabboux, G.
Zaza, I. A. Zaza I.
Juge, A. A. Juge A.
Mortini, P. A. Mortini P.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings 2000
Year:2000
Abstract: ESD protection for RF applications must deal with good ESD
performance, minimum capacitance, zero series resistance and good
capacitance linearity. In order to fulfil these requirements, different ESD
protection strategies for RF applications have been investigated in a 0.18
&mu;m CMOS process. This paper compares different ESD protection devices
and shows that a suitable ESD performance target for RF applications (200 fF
max, 2 kV HBM) can be reached with a diode network scheme. The
optimization of the diodes is then a key point which is detailed. A trade-off must
be found between the ESD performance, the voltage drop during ESD and the
parasitic capacitance. Poly as well as STI bounded diodes have been studied
and it appears clearly that a solution based on poly bounded diodes is the best
choice

Title Detecting ESD events using a loop antenna
Author Munoz, J. L.
Tan, J.
Adriano, C.
Roldan, E. A. Roldan E.
Sadie, J. A. Sadie J.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings
Year:2000
Abstract: Electrostatic discharge (ESD) is the rapid transfer of electrostatic
charge between bodies at different electrostatic potentials. In an ESD event, a
short burst of radiated energy in the form of an electromagnetic pulse or
electromagnetic interference (EMI) is created. In this paper, we discuss the
use of a homemade loop to detect the EMI generated by an ESD event. We
also report the observed correlation between three industry defined ESD
stress models and the radiated EMI signal as detected by the loop antenna. A
Zapmaster Keytek 512 zapper is used to simulate the ESD events and a
high-speed oscilloscope is used to capture the EMI detected by the loop
antenna. In the paper, we also report use of the loop antenna in solving an
ESD issue that affected the 32M Boot Block flash memory device

Title A comparison of quasi-static characteristics and failure signatures of
GMR heads subjected to CDM and HBM ESD events
Author Moore, C.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings
Year:2000
Abstract: The effects of the human body model (HBM) electrostatic discharge
(ESD) waveform on giant magnetoresistive (GMR) heads is fairly well
characterized. This information provides a baseline against which a
comparison can be made for other ESD models. The goal of this work is to
compare and contrast the effects that are seen in GMR sensors when they are
subjected to the charged-device model (CDM) versus HBM ESD events. This
study compares the effects of CDM waveforms versus HBM waveforms on a
single design of MR head. Although the HBM waveform has provided a
starting point for understanding ESD damage to GMR heads, it is believed that
the CDM model has a more useful basis in the reality of head manufacturing.
This makes study of the effects of CDM ESD events on GMR heads both
important and interesting. Detailed characterization of head response as a
function of the ESD waveform was realized using a new system combining
quasi-static (QST) analysis with in-situ CDM and HBM ESD simulation
capabilities. A SEM was used to perform failure analysis on damaged heads in
an attempt to characterize differences in the &ldquo;failure signature&rdquo; of
the sensor

Title A comparison study of ESD protection for RFICs: performance vs.
parasitics
AuthorHaigang, Feng
Ke, Gong
Wang, A. Z.
Conference Name: Radio Frequency Integrated Circuits (RFIC) Symposium,
2000. Digest of Papers. 2000 IEEE
Year:2000
Abstract: This paper reports two advanced Electro-Static Discharge (ESD)
protection structures suitable for RFICs and a comparison study of influences
of ESD parasitic capacitance (C<sub>ESD</sub>) on high-speed circuits. For
a 4 GHz ring-oscillator and a low-power high-speed op-amp circuits, it was
observed that C<sub>ESD</sub> may corrupt high-speed performance
significantly and new ESD structures can recover the corruption by 80%

Title Investigation of GMR sensor microstructural changes induced by HBM
ESD using advanced microscopy approach
Author: Bordeos, R.
Zhang, Lianzhu
Hung, S. T. F.
Wong, C. Y. A. Wong C. Y.
Conference Name: Electrical Overstress/Electrostatic Discharge Symposium
Proceedings 2000
Year:2000
Abstract: In theory, the microstructure of any material dictates its macroscopic
properties. This study explores the microstructure of the GMR reader
characterized during gradual ESD stressing and with the aid of the advanced
analytical tools of AFM/MFM after enhanced imaging of GMR sensors by
surface ion milling. It is known that ESD events can occur and manifest
themselves exclusively either physically (melting of sensor element) or
magnetically (sudden drop in electrical parameters when plotted against stress
voltage) in GMR heads. A simulation study was directed using commercial
HBM and dynamic electrical test machines to produce different types of ESD
failure events. Preliminary results showed that ESD stressed and ESD-free
GMR heads can be characterized and differentiated from one another using
the simple surface technique of MFM. By using the combined analytical
techniques which are particular to AFM and MFM coupled with methodical and
systematic failure analysis, we are able to observe in-situ the previously
unknown ESD phenomena unique to GMR heads

Title A comparison study of ESD protection for RFICs: performance vs.
parasitics
AuthorHaigang, Feng
Ke, Gong
Wang, A. Z.
Conference Name: Radio Frequency Integrated Circuits (RFIC) Symposium,
2000. Digest of Papers. 2000 IEEE
Year:2000
Abstract: This paper reports two advanced Electro-Static Discharge (ESD)
protection structures suitable for RFICs and a comparison study of influences
of ESD parasitic capacitance (C<sub>ESD</sub>) on high-speed circuits. For
a 4 GHz ring-oscillator and a low-power high-speed op-amp circuits, it was
observed that C<sub>ESD</sub> may corrupt high-speed performance
significantly and new ESD structures can recover the corruption by 80%

Title Design methodology and optimization of gate-driven NMOS ESD
protection circuits in submicron CMOS processes
Author :Chen, J. Z.
Amerasekera, E. A.
Duvvury, C.
Journal: Electron Devices, IEEE Transactions on
Year:1998
Abstract: This paper describes the design methodology for gate driven NMOS
ESD protection in submicron CMOS processes. A new PNP Driven NMOS
(PDNMOS)-protection scheme is presented. Without requiring any additional
process steps or introducing any additional impedance in signal path, the
PDN-MOS is effective even for small analog/mixed-signal designs. SPICE
simulations are used to optimize the design. High ESD performance of the
PDNMOS protection in both nonsilicided and silicided submicron processes is
demonstrated in this work

Title Modeling MOS snapback and parasitic bipolar action for circuit-level ESD
and high-current simulations
Author : Amerasekera, A.
Mi-Chang, Chang
Duvvury, C.
Ramaswamy, S.
Journal: Circuits and Devices Magazine, IEEE
Year:1997
Abstract: The design and optimization of ESD protection circuits is greatly
enhanced by the ability to perform circuit-level simulations of the protection
circuits and the I/O buffers. Most available simulators do not cover the high
current region of the circuit operation, but still enable an approximate analysis
to be made of the behaviour under ESD conditions. In this article, a description
of the behaviour of the MOS device in the high current regime is presented
together with the model equations governing that behaviour. The equations
have been implemented into a SPICE circuit simulator, and the experimental
and simulation results are given. A simple parameter extraction methodology
is presented that uses the terminal currents from a single MOS DC I-V curve to
obtain all the MOS and bipolar parameters required for the model

Title Simulation of the response of external ESD protection circuits for CMOS
ICs
Author : Renuka, R.
Rajesh, J.
Hariharan, V. K.
Shastry, S. V. K.
Conference Name: Electromagnetic Interference and Compatibility, 1995.,
International Conference on
Year:1995
Abstract: CMOS ICs are highly susceptible to electrostatic discharge (ESD)
induced voltage/current stresses. The IC manufacturer provides an on-chip
protection circuit for improving the ESD susceptibility threshold of CMOS
devices. However, device failures continue to occur due to electrical
overstress (EOS) or due to ESD. For example, the CD4050B device has a built
in immunity level of 2 kV for the human body model (HBM) ESD waveform.
Hence the EOS/ESD failures noticed in these devices may be either due to a
HBM-ESD stress level which is higher than 2 kV or due to other types of work
practice/area related ESD stress waveform. Thus, there appears to be a need
for providing external ESD protection circuits such that the device performance
is not affected adversely. This paper gives an account of studies made using
SPICE and MC4 circuit simulation software, to determine the effectiveness of
some of the HBM-ESD external protection circuits

Title ESD reliability and protection schemes in SOI CMOS output buffers
Author : Mansun, Chan
Yuen, S. S.
Zhi-Jian, Ma
Hui, K. Y.
Ko, P. K.
Chenming, Hu
Journal: Electron Devices, IEEE Transactions on
Year:1995
Abstract: The electrostatic discharge (ESD) protection capability of SOI CMOS
output buffers has been studied with Human Body Model (HBM) stresses.
Experimental results show that the ESD voltage sustained by SOI CMOS
buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD
discharge current in a SOI CMOS buffer is found to be absorbed by the
NMOSFET alone. Also, SOI circuits display more serious reliability problem in
handling negative ESD discharge current during bi-directional stresses. Most
of the methods developed for bulk technology to improve ESD performance
have minimal effects on SOI. A new Through Oxide Buffer ESD protection
scheme is proposed as an alternative for SOI ESD protection. In order to
improve ESD reliability, ESD protection circuitries can be fabricated on the SOI
substrate instead of the top silicon thin film, after selectively etching through
the buried oxide. This scheme also allows ESD protection strategies
developed for bulk technology to be directly transferred to SOI substrate.

Title VLSI circuits degradation due to ESD stress below ESD rating voltage
Author : Lisenker-Touber, B.
Journal: Electrical and Electronics Engineers in Israel, 1995., Eighteenth
Convention of
Year:1995
Abstract: This paper examines low level damage due to ESD stress below
ESD rating on one-micron n-well CMOS VLSI circuits and on an NMOSFET.
Different VLSI products with different ESD protection circuits were tested using
a new method, proposed for latency phenomenon investigation. It is clearly
ascertained that ESD stress below ESD rating causes latency damage in VLSI
circuits independent of the ESD protection circuit performance. The results
obtained on an NMOSFET allow to explain many in-circuits degradations
caused by low-level ESD events

Title Analysis of soft breakdown failure with ESD on output buffer nMOSFETs
and its improvement
Author : Kurachi, I.
Fukuda, Y.
Miura, N.
Ichikawa, F.
Year:1994
Abstract: The leakage increase of the off-state MOSFETs after an ESD event
has been studied for output transistors with the thin gate oxide and LDD
structures. Leakage increase called &ldquo;soft breakdown&rdquo; has been
found at relatively low ESD testing voltages (200-300 V). This soft breakdown
is caused by the creation of interface traps due to the snap-back stressing
during the ESD event. The creation of interface traps has enhanced the
interface trap to band tunneling current at the drain side of the MOSFETs. The
improvement of the ESD threshold has also been proposed with an additional
arsenic implantation into the n<sup>$ </sup>region. It has been confirmed that
the arsenic implantation improved the HBM ESD threshold to more than 2000
V

Title A tutorial and an experimental demonstration of how ESD is generated
and its impact on electronic devices
Author : Issa, M.
Conference Name: Southcon/94. Conference Record
Year:1994
Abstract: Summary form only given, as follows. It has been recognized since
the 1960s that many devices such as metal oxide semiconductors,
microprocessors, bipolar devices, operational amplifiers, and even discrete
components are susceptible to electrostatic discharge (ESD). Thus, ESD has
become a hazard to the electronic industry. This tutorial paper presents the
concept of ESD as a special topic in the overall subject of electromagnetic
compatibility (EMC). It presents the fundamental aspects of ESD and answers
questions such as: what is ESD, how is ESD generated, and how is the human
body modeled for ESD? This tutorial paper also presents an engineering
example to calculate the damaging effects of ESD on electronic components.
The experimental demonstration is an integral part of this tutorial paper. The
experiment illustrates the following: a) how an electrically conductive surface
could be charged to very high voltages when in close proximity to a charged
dielectric material; b) how various factors could impact the occurrence of ESD;
c) how failure or electrical overstress on electronic components could result

Title Technology design for high current and ESD robustness in a deep
submicron CMOS process
Author : Amerasekera, A.
Chapman, R. A.
Journal: Electron Device Letters, IEEE
Year:1994
Abstract: The intrinsic ESD/EOS robustness of a technology is determined by
the sensitivity to thermal initiated second breakdown. We show, for the first
time, high current and ESD robustness results for a deep submicron CMOS
technology with drawn poly gate lengths of 0.35 &mu;m and oxide thicknesses
down to 4.5 nm. It is shown that a transistor design window can be determined
for optimized drive current and good robustness, while maintaining low off
currents. An important observation is that robustness increases for smaller
channel lengths and is directly proportional to the transistor drive current.
Hence, robust deep submicron technologies can be designed with optimized
transistor performance without using additional masks or increasing process
complexity
Title An optimal silicidation technique for electrostatic discharge protection
sub-100 nm CMOS devices in VLSI circuit
Author : Yu, Shao-Ming
Lee, Jam-Wen
Li, Yiming
Journal: Microelectronic Engineering
Year:2007
Abstract: In this paper we propose a silicide design consideration for
electrostatic discharge (ESD) protection in nanoscale CMOS devices.
According to our practical implementation, it is found that a comprehensive
silicide optimization can be achieved on the gate, drain, and source sides with
very few testkey designs. Our study shows that there is a high characteristic
efficiency for various conditions; in particular, for optimizing the performance of
sub-100 nm complementary metal-oxide-semiconductor devices in
system-on-a-chip era.

Title Holding voltage investigation of advanced SCR-based protection
structures for CMOS technology
Author : Tazzoli, A.
Marino, F. A.
Cordoni, M.
Benvenuti, A.
Colombo, P.
Zanoni, E.
Meneghesso, G.
Journal: Microelectronics Reliability
Year:2007
Abstract: A new silicon-controlled rectifier low voltage triggered (SCR-LVT), to
be adopted as protection structure against electrostatic discharge (ESD)
events, has been developed and characterized. A high holding voltage has
been obtained thanks to the insertion of two parasitic bipolar transistors,
achieved adding a n-buried region to a conventional SCR structure. These two
parasitic transistors partially destroy the loop feedback gain of the two main
npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage
during the ESD event. A strong dependence of the holding voltage with the
ESD pulse width has also been observed, caused by self-heating effects.
2D-device simulations (DESSIS Synopsys) have been performed obtaining
results that perfectly fit the measurements over a wide temperature range (25
[degree sign]C - 125 [degree sign]C). Using device simulation results, the
factors that influence the holding voltage, in terms of temperature dependence,
but also in the behavior of the parasitic BJTs, are explained. A guideline to
change the SCR holding voltage, related to the SCR design layout without any
change to process parameters, is also proposed.
Title Low capacitance ESD protection circuits for GaAs RF ICs
Author : Sun, Maoyou
Lu, Yicheng
Huai, Yongjin
Journal: Journal of Electrostatics
Year:2007
Abstract: We present a novel electrostatic discharge (ESD) protection circuit
for GaAs radio frequency (RF) integrated circuits (ICs), which are targeted for
10 Gb/s fiber-optic communication applications. The robustness, parasitic
impedance, and loading effect of the new ESD protection circuit are studied
and compared with the conventional diode-based ESD protection technique.
Two versions of this type of ESD protection circuit were fabricated with a
60-GHz InGaP heterojunction bipolar transistor (HBT) technology. These two
circuits can withstand, respectively, 2700 and 5000 V human body model
(HBM) ESD stress and provide a similar level of ESD protection to RF ICs. The
corresponding impedances of the off state are represented by an equivalent
shunt capacitance and shunt resistance of 0.22 pF and 500 [Omega], and 0.5
pF and 250 [Omega], at 10 GHz. This ESD protection circuit can protect the 10
Gb/s RF ICs against much higher level ESD stress than conventional
diode-based ESD protection circuits even with smaller size.

Title RF ESD protection strategies: Codesign vs. low-C protection
Author : Soldner, W.
Streibl, M.
Hodel, U.
Tiebout, M.
Gossner, H.
Schmitt-Landsiedel, D.
Chun, J. H.
Ito, C.
Dutton, R. W.
Journal: Microelectronics Reliability
Year:2007
Abstract: The present work is focussed on the trade-off between conventional
RF ESD protection concepts optimized in terms of capacitive load and the
frequently discussed RF ESD codesign idea with ESD protection skilfully
integrated into RF circuit design. A narrow and a broadband RF test circuit
were developed to put the benchmark on a firm basis. RF and ESD
experiments are discussed, showing where the higher effort for the codesign
approach starts to pay off.

Title Selecting an appropriate ESD protection for discrete RF power LDMOSTs
Author : Smedes, T.
de Boet, J.
Rodle, T.
Journal: Microelectronics Reliability
Year:2007
Abstract: For ESD protections of RF Power MOSTs, Vt1 lowering by the RF
signal - due to the dV/dt effect - can seriously degrade the RF performance.
The use of a cascoded protection solves this problem. A new failure
mechanism, related to the discharge of on-chip RF matching capacitors is
presented. Adding a current limiting resistor in the protection solves this issue.
Combining these solutions yields an appropriate protection for discrete RF
power LDMOSTs.

Title Effects of background doping concentration on electrostatic discharge
protection of high voltage operating extended drain N-type MOS device
Author : Seo, Yong-Jin
Kim, Kil-Ho
Journal: Microelectronic Engineering
Year:2007
Abstract: In this study, the effects of background doping concentration (BDC)
of a high voltage operating extended drain N-type MOSFET (EDNMOS) device
on electrostatic discharge (ESD) protection performances were evaluated. The
EDNMOS device with low BDC suffers from strong snapback in the high
current region, which results in poor ESD protection performance and high
latchup risk. However, the strong snapback can be avoided in the EDNMOS
device with high BDC. This implies that both the good ESD protection
performance and the latchup immunity can be realized in terms of the
EDNMOS by properly controlling its BDC.

Title SCR-based ESD protection in nanometer SOI technologies
Author : Marichal, Olivier
Wybo, Geert
Van Camp, Benjamin
Vanysacker, Pieter
Keppens, Bart
Journal: Microelectronics Reliability
Year:2007
Abstract: This paper introduces an SCR-based ESD protection design for
silicon-on-insulator (SOI) technologies. SCR devices or thyristors, as they are
sometimes better known, have long since been used in Bulk CMOS to provide
very area efficient, high performance ESD protection for a wide variety of
circuit applications. The special physical properties and design of an SOI
technology however, renders straightforward implementation of an SCR in
such technologies impossible. This paper discusses these difficulties and
presents an approach to construct efficient SCR devices in SOI. These
devices outperform MOS-based ESD protection devices by about four times,
attaining roughly the same performance as diodes. Experimental data from
two 65 nm and one 130 nm SOI technologies is presented to support this.

Title SCR-based ESD protection in nanometer SOI technologies
Author : Marichal, Olivier
Wybo, Geert
Van Camp, Benjamin
Vanysacker, Pieter
Keppens, Bart
Journal: Microelectronics Reliability
Year:2007
Abstract: This paper introduces an SCR-based ESD protection design for
silicon-on-insulator (SOI) technologies. SCR devices or thyristors, as they are
sometimes better known, have long since been used in Bulk CMOS to provide
very area efficient, high performance ESD protection for a wide variety of
circuit applications. The special physical properties and design of an SOI
technology however, renders straightforward implementation of an SCR in
such technologies impossible. This paper discusses these difficulties and
presents an approach to construct efficient SCR devices in SOI. These
devices outperform MOS-based ESD protection devices by about four times,
attaining roughly the same performance as diodes. Experimental data from
two 65 nm and one 130 nm SOI technologies is presented to support this.

Title Experimental and numerical analysis of current flow homogeneity in low
voltage SOI multi-finger gg-NMOS and NPN ESD protection devices
Author : Heer, M.
Bychikhin, S.
Mamanee, W.
Pogany, D.
Heid, A.
Grombach, P.
Klaussner, M.
Soppa, W.
Ramler, B.
Journal: Microelectronics Reliability
Year:2007
Abstract: Triggering uniformity and current sharing under TLP stress is
investigated in low voltage multi-finger gg-NMOS and NPN ESD protection
devices fabricated in smart-power SOI technology. Inhomogeneous current
distribution over the fingers and within a single finger is detected by the
backside transient interferometric mapping (TIM) technique. 2D TCAD device
simulations of the multi-finger devices are used to explain the experimental
TIM results. Changes in differential resistance in the pulsed IV characteristics
of the NPN ESD protection devices are also explained by TIM experiments.
Title Implementation of plug-and-play ESD protection in 5.5 GHz 90 nm RF
CMOS LNAs--Concepts, constraints and solutions
Author : Thijs, S.
Natarajan, M. I.
Linten, D.
Jeamsaksiri, W.
Daenen, T.
Degraeve, R.
Scholten, Andries
Decoutere, S.
Groeseneken, G.
Journal: Microelectronics Reliability
Year:2006
Abstract: Design and implementation of ESD protection for a 5.5 GHz low
noise amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented.
An on-chip inductor, added as "plug-and-play", is used as ESD protection for
the RF pins. The consequences of design and process, as well as, the limited
freedom on the ESD protection implementation for all pins to be protected are
presented in detail. Enhancement in the ESD robustness using additional
core-clamp diodes is proposed.

Title InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD
protection circuits
Author : Ma, Yintat
Li, G. P.
Journal: Journal of Electrostatics
Year:2006
Abstract: This paper presents design considerations and implementation of
InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD
protection circuits. The inherit benefits of both bandwidth and ESD robustness
of distributed amplifiers are first compared to those of single-ended feedback
amplifiers. Next, novel on-chip ESD protection circuits are introduced,
featuring low capacitance loading for wide bandwidth, low leakage, and good
linearity under high RF power. This paper discusses the principle of operation,
ESD performance, and RF loading of the ESD protection circuits. The RF
performance and ESD robustness of the distributed amplifier with the ESD
protection circuits are also presented.

Title InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD
protection circuits
Author : Ma, Yintat
Li, G. P.
Journal: Journal of Electrostatics
Year:2006
Abstract: This paper presents design considerations and implementation of
InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD
protection circuits. The inherit benefits of both bandwidth and ESD robustness
of distributed amplifiers are first compared to those of single-ended feedback
amplifiers. Next, novel on-chip ESD protection circuits are introduced,
featuring low capacitance loading for wide bandwidth, low leakage, and good
linearity under high RF power. This paper discusses the principle of operation,
ESD performance, and RF loading of the ESD protection circuits. The RF
performance and ESD robustness of the distributed amplifier with the ESD
protection circuits are also presented.

Title Comprehensive ESD protection approach in advanced CMOS SOI
technologies
Author : Khazhinsky, Michael G.
Stockinger, Michael
Miller, James W.
Weldon, James C.
Journal: Journal of Electrostatics
Year:2006
Abstract: In this paper we describe a 90 nm SOI ESD protection network and
design methodology including both device and circuit level characterization
data. We compare TLP results of SOI MOSFETs and diodes to bulk devices.
We present a new response surface method to optimize device sizes in the
ESD networks and show circuit level data comparing TLP test results and
SPICE simulation results of an I/O test circuit. We also present product test
data for standard ESD stress models.

Title Damped transient power clamps for improved ESD protection of CMOS
Author : Hunter, Bradford L.
Butka, Brian K.
Journal: Microelectronics and Reliability
Year:2006
Abstract: Small transient power clamps that include inverters may oscillate and
disengage during an HBM ESD event. A transient power clamp created in a
0.25 [mu]m process revealed an interesting solution to the problem. Adding a
resistance to the final inverter may improve ESD performance.

Title Analysis of triggering behaviour of high voltage CMOS LDMOS clamps
and SCRs during ESD induced latch-up
Author : Heer, M.
Dubec, V.
Bychikhin, S.
Pogany, D.
Gornik, E.
Frank, M.
Konrad, A.
Schulz, J.
Journal: Microelectronics and Reliability
Year:2006
Abstract: Current flow uniformity during ESD induced latch-up event is
investigated in multi-finger LDMOS clamps and SCR ESD protection devices
fabricated in a 0.6 [mu]m high voltage CMOS process. Current flow, excess
free carrier and hot spot distribution are analyzed by transient interferometric
mapping technique combined with a latch-up pulse system consisting of a solid
state pulser and a clear pulse unit. During latch-up, the current in the LDMOS
clamps flows just in a single spot and the failure position is random and
independent on device type. The position of the failure site correlates with the
trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in
the current flow.

Title ESD protection structure qualification - a new approach for release for
automotive applications
Author : Goroll, M.
Kanert, W.
Pufall, R.
Journal: Microelectronics and Reliability
Year:2006
Abstract: To protect semiconductor products against damages due to
electrostatic discharges separate protection structures are necessary. These
structures are part of the device pad circuitry and designed for a dedicated
wafer technology and ESD (Electrostatic Discharge) withstanding voltage. All
present automotive qualification standards AEC-Q100/101 (Automotive
Electronic Council) [1,2] do not cover a qualification and release of ESD
protection structures related to their designed ESD strength. The paper will
introduce a new qualification strategy for ESD protection structures depending
on the designed ESD target. On dedicated ESD diodes drifts of several
parameters versus time were analyzed. The results will be presented and
discussed. Release targets for automotive applications will be defined.

Title A review of latchup and electrostatic discharge (ESD) in BiCMOS RF
silicon germanium technologies: Part I--ESD
Author : Voldman, Steven H.
Journal: Microelectronics and Reliability
Year:2005
Abstract: Electrostatic discharge (ESD) continues to be a semiconductor
quality and reliability area of interest as semiconductor components are
reduced to smaller dimensions. The combination of scaling, design integration,
circuit performance objectives, new applications, and the evolving system
environments, ESD robustness will continue to be a technology concern. With
the transition from silicon bipolar junction transistor to modern BiCMOS silicon
germanium (SiGe) semiconductor technologies, new semiconductor process
and integration issues have evolved which influence both device performance
and ESD protection. Additionally, the issues of low cost, low power and radio
frequency (RF) GHz performance objectives has lead to both revolutionary as
well as derivative technologies; these have opened new doors for discovery,
development and research in the area of on-chip ESD protection and design.
With the growth of interest of ESD in RF technology, new innovations and
inventions are occurring at a rapid pace. In this paper, we will provide an
introductory review of silicon germanium technology and ESD.

Title ESD-RF co-design methodology for the state of the art RF-CMOS blocks
Author : Vassilev, V.
Thijs, S.
Segura, P. L.
Wambacq, P.
Leroux, P.
Groeseneken, G.
Natarajan, M. I.
Maes, H. E.
Steyaert, M.
Journal: Microelectronics and Reliability
Year:2005
Abstract: This paper describes an approach to design ESD protection for
integrated low noise amplifier (LNA) circuits used in narrowband transceiver
front-ends. The RF constraints on the implementation of ESD protection
devices are relaxed by co-designing the RF and the ESD blocks, considering
them as one single circuit to optimise. The method is applied for the design of
0.25 [mu]m CMOS LNA. Circuit protection levels higher than 3 kV HBM stress
are achieved using conventional highly capacitive ggNMOS snapback devices.
The methodology can be extended to other RF-CMOS circuits requiring ESD
protection by merging the ESD devices in the functionality of the
corresponding matching blocks.

Title High abstraction level permutational ESD concept analysis
Author : Streibl, M.
Zangl, F.
Esmark, K.
Schwencker, R.
Stadler, W.
Gossner, H.
Druen, S.
Schmitt-Landsiedel, D.
Journal: Microelectronics and Reliability
Year:2005
Abstract: A simulation approach is presented that allows handling ESD
simulation and analysis on a chip-level complexity. In a Monte-Carlo like
permutational simulation approach, worst case ESD paths are identified. The
simulator is embedded in an ESD analysis framework spanning from the chip
protection description to an automated virtual HBM test routine with a
respective fail reporting interface. The tools capabilities are demonstrated in
the ESD analysis of a complex mixed-signal design.

Title Thermally-driven motion of current filaments in ESD protection devices
Author : Pogany, D.
Bychikhin, S.
Denison, M.
Rodin, P.
Jensen, N.
Groos, G.
Stecher, M.
Gornik, E.
Journal: Solid-State Electronics
Year:2005
Abstract: Dynamics of localized current filaments is analyzed in electrostatic
discharge protection devices of a smart power technology during microsecond
long constant current pulses. Experiments performed by backside transient
interferometric mapping technique and transmission line pulser stressing are
correlated with 3D device simulation. Motion of the filament along the device
width and its reflection at the device ends are observed. This behavior is
related to the time evolution of the voltage waveform and is explained by the
simulation. The filament motion is driven by the temperature gradient in the
filament due to the negative temperature dependence of the impact ionization
rates. A simplified analytical expression for the filament speed as a function of
stress conditions and thermal characteristics is given.

Title Electrostatic discharge directly to the chip surface, caused by automatic
post-wafer processing
Author : Jacob, Peter
Thiemann, Uwe
Reiner, Joachim C.
Journal: Microelectronics Reliability
Year:2005
Abstract: Up to now, ESD damage is understood to be induced via device pads
and to be avoided by means of appropriate protection structures located at
these pads. The ESD susceptibility is classified by means of standardized
stress tests. This paper shows, that with increasing importance a variety of
post-wafer manufacturing and packaging processes may create a new type of
evident and latent ESD damage in the device. We define this phenomenon as
ESD-from-outside-to-surface (ESDFOS), as charged handlers cause
discharges directly from outside into the device surface. Classical ESD tests
do not cover this mechanism. The paper describes the phenomenon, its root
causes, and gives practical hints for analysis and prevention.

Title Comprehensive ESD protection for RF inputs
Author : Hyvonen, Sami
Joshi, Sopan
Rosenbaum, Elyse
Journal: Microelectronics Reliability
Year:2005
Abstract: We demonstrate that narrow-band tuned circuits may be used for
ESD protection of RF inputs, and a figure of merit for optimization of these
circuits is presented. The performance of the ESD-protected RF circuit is
dependent on the quality factor of the ESD device, and various protection
devices are evaluated in this work. Record-breaking human body model (HBM)
protection levels, exceeding 5 kV, have been achieved without significantly
degrading the RF performance at 5 GHz. Broadband circuit protection is also
addressed.

Title Optimization of input protection diode for high-speed applications
Author : Worley, Eugene R.
Bakulin, Alex
Journal: Journal of Electrostatics
Year:2003
Abstract: Optimization of input protection diodes for high-speed applications
including radio frequency and Internet receivers is examined. The key
parameters used to rate the diodes are the RC time constant and the failure
point defined by human body model failure voltage per unit of capacitance.
Minimizing the RC time constant for stripe diodes includes looking at tapered
metal, wide ground stripes, slot contacts, background doping, and the length of
the stripes. Maximizing the failure point includes looking at tapered metal,
contacts, and proximity effects.

Title Sub-circuit models of silicon-on-insulator insulated-gate pn-junction
devices for electrostatic discharge protection circuit design and their
applications
Author : Wakita, Shigeyuki
Omura, Yasuhisa
Journal: Solid-State Electronics
Year:2003
Abstract: This paper proposes equivalent circuit models of silicon-on-insulator
(SOI) insulated-gate pn-junction devices for circuit simulations. Fundamental
device models are investigated using a device simulator. The proposed
equivalent circuit models of the devices utilize standard SPICE circuit
elements. Equivalent circuit models are used to evaluate the performance of
an electrostatic discharge (ESD) protection circuit. It is shown that the SOI
insulated pn-junction devices have sufficient performance to act as ESD
protection devices. By combining circuit simulations and device simulations,
the high-current characteristics of SOI insulated-gate pn-junction devices are
also addressed, and a couple of issues are raised with regard to the further
development of these circuits.

Title An automated design system methodology and strategy for electrostatic
discharge protection circuits in RF CMOS and BiCMOS silicon germanium
technology
Author : Voldman, Steven H.
Strang, Susan E.
Jordan, Donald
Journal: Journal of Electrostatics
Year:2003
Abstract: In a Cadence environment, a novel automated methodology is
established to optimize (electrostatic discharge) ESD networks. An automated
ESD design system for digital, analog and radio frequency (RF) circuits in a
mixed signal semiconductor chips using a hierarchy of RF-characterized
higher order graphical parameterized cells allows for co-synthesis of RF
design and ESD evaluation. The auto-generated ESD design system includes
CMOS and BiCMOS input, rail-to-rail and power clamp ESD network with
layout, schematic and symbolic representations. Human body model (HBM),
machine model (MM), and transmission line pulse (TLP) results demonstrate
the operation of the ESD designs, and the region of optimum ESD results.

Title High frequency characterization and modelling of the parasitic RC
performance of two terminal ESD CMOS protection devices
Author : Vassilev, V.
Jenei, S.
Groeseneken, G.
Venegas, R.
Thijs, S.
De Heyn, V.
Natarajan, M.
Steyaert, M.
Maes, H. E.
Journal: Microelectronics Reliability
Year:2003
Abstract: This paper describes a simplified high frequency characterization
approach to extract the parasitic RC figures of merit of two terminal CMOS
electrostatic discharge (ESD) protection devices. Basic RC small signal
equivalent models and corresponding parameter extraction procedures,
applicable for the most typical structures--grounded gate NMOS, diodes and
SCR's are presented. The model application to study the impact of the ESD
failures on the HF device and circuit characteristics is demonstrated.

Title LVTSCR structures for latch-up free ESD protection of BiCMOS RF
circuits
Author : Vashchenko, V.
Concannon, A.
ter Beek, M.
Hopper, P.
Journal: Microelectronics Reliability
Year:2003
Abstract: The results of a numerical and experimental study aimed at
increasing the holding on-state voltage of a low-voltage triggered silicon
controlled rectifier are presented. Using TCAD numerical simulations two
solutions are presented that are based on emitter injection control by the
modification of the emitter-drain area ratio and by the addition of internal
diodes in the emitter line. Experimental data generated in a 0.18 [mu]m CMOS
technology demonstrate the effectiveness of the new low-voltage triggered
silicon controlled rectifier (LVTSCR) structures and validates the simulation
results. It has been demonstrated that for the LVTSCR structures with high
holding voltage the electrostatic discharge efficiency is 3-5 times higher than
that of a conventional grounded gate snapback NMOS and simultaneously has
50% lower RF load capacitance.

Title A novel on-chip ESD protection circuit for GaAs HBT RF power amplifiers
Author : Ma, Yintat
Li, G. P.
Journal: Journal of Electrostatics
Year:2003
Abstract: A low loading capacitance, 0.1 pF, on-chip electrostatic discharge
(ESD) protection circuit for 2000 V HBM for GaAs power amplifiers that does
not degrade RF circuit performance is introduced. Its principle of operation,
loading capacitance, leakage current, ESD clamping characteristics, and
robustness over process variation and temperature are investigated. Finally, a
case study of its application to a 5.8 GHz power amplifier used for the wireless
802.11 A local area network is discussed.

Title A novel on-chip ESD protection circuit for GaAs HBT RF power amplifiers
Author : Ma, Yintat
Li, G. P.
Journal: Journal of Electrostatics
Year:2003
Abstract: A low loading capacitance, 0.1 pF, on-chip electrostatic discharge
(ESD) protection circuit for 2000 V HBM for GaAs power amplifiers that does
not degrade RF circuit performance is introduced. Its principle of operation,
loading capacitance, leakage current, ESD clamping characteristics, and
robustness over process variation and temperature are investigated. Finally, a
case study of its application to a 5.8 GHz power amplifier used for the wireless
802.11 A local area network is discussed.

Title High ESD performance, low power CMOS LNA for GPS applications
Author : Leroux, Paul
Vassilev, Vesselin
Steyaert, Michiel
Maes, Herman
Journal: Journal of Electrostatics
Year:2003
Abstract: This paper describes the design of a high performance 0.25 [mu]m
CMOS low noise amplifier (LNA) for the global positioning system (GPS)
operating at 1.57 GHz. The LNA features a 1.5 dB noise figure. The input
ESD-protection is in the order of 3 kV HBM and the power consumption is only
6 mW.

Title An improved electrostatic discharge protection structure for reducing
triggering voltage and parasitic capacitance
Author : Gao, Xiaofang
Liou, Juin J.
Wong, Waisum
Vishwanathan, Satya
Journal: Solid-State Electronics
Year:2003
Abstract: On-chip electrostatic discharge (ESD) protection structures are
frequently used in microchips to protect the core circuit again ESD damages.
Relatively large parasitic capacitances associated with these structures,
however, can degrade the performance of microchips. In this paper, a new
type of supply clamp is studied for the purpose of reducing the parasitic
capacitance in ESD protection structures. The approach and physics of the
new supply clamp are discussed, and both experimental data and device
simulation are provided in support of the investigation.

Title An improved electrostatic discharge protection structure for reducing
triggering voltage and parasitic capacitance
Author : Gao, Xiaofang
Liou, Juin J.
Wong, Waisum
Vishwanathan, Satya
Journal: Solid-State Electronics
Year:2003
Abstract: On-chip electrostatic discharge (ESD) protection structures are
frequently used in microchips to protect the core circuit again ESD damages.
Relatively large parasitic capacitances associated with these structures,
however, can degrade the performance of microchips. In this paper, a new
type of supply clamp is studied for the purpose of reducing the parasitic
capacitance in ESD protection structures. The approach and physics of the
new supply clamp are discussed, and both experimental data and device
simulation are provided in support of the investigation.

				
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