# CECS 201 Syllabus by nuhman10

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```									                CALIFORNIA STATE UNIVERSITY, LONG BEACH
COLLEGE OF ENGINEERING
Department of computer Engineering and Computer Science
CECS 201 Digital Logic Design (3) F,S
Course Description

2009 - 10 Catalog:        Prerequisite: MATH 113 (or equivalent). Basic topics in
combinational and sequential switching circuits with applications to the design of digital
devices. Laboratory projects with Small Scale Integration (SSI) implementations using
Computer Aided Design (CAD). (Lecture 2 hours, lab 3 hours.) Letter grade only (A-F).

Textbook:      Mano, M. Morris. Logic and Computer Design Fundamentals, Forth Edition,
Prentice-Hall
Coordinator:
Instructor:    Bob Ward                             Office Hours:
Office:        ECS 630                              MW 12:30 – 1:00
Phone:         985-5225                             T TH 10:15 – 11:00
Email:         brewer@csulb.edu

Goals:         Provide basic concepts in combinational switching circuits as well as
foundations of sequential circuits to create an understanding of the
fundamental principles underlying operation of digital computers.

# Weeks        Lecture Subjects
1½       Number representation, conversion and arithmetic (decimal, binary and
hex.)
1½       Binary codes (8421, BCD, XS3, ASCII, and gray.)
2       Simplification – minterms, maxterms, canonical forms, don’t cares, and K-
maps (up to four variables.)
2       Combinational logic (2 level logic) SSI.
2       Addition and subtraction using modulo arithmetic and complement
2       Combinational logic (glue logic) MSI and LSI.
3       Synchronous sequential logic. FF (D. T and JK) function (not design.)
Timing diagrams (clock edges and levels.) Sequential counter and shift
register design.
# Weeks        Laboratory Subjects
3       Fundamentals – Creation of: schematics (gates, wires, junctions and mod
ports), Netlist, stimulus files and trace files.
How to: run the simulation, change the view, make hardcopies, read the
timing diagram from the simulation (gate delays) and understand pin
numbers and their relationship to a chip.
2       Different logic families (74xx, 74sxx, etc.) Different gate delays (hi to low
vs lo to hi.) Gate response times for changing inputs.
2       Ckt. Delays (critical path) and the relationship to gate delays. F/A design
using two-level logic (glitches.) NAND logic. Relating the number of gates
to the number of chips.
2       Pal programming, Creation of JEDEC files using TT and Boolean algebra
input. Testing with vectors.
2       Fielders choice. Ripple adder, counter, register, MUX, decoder.
2       Bread boarding. An introduction to improve understanding of gates vs
chips and 1 and 0’s vs voltage levels.

Computer Usage: Circuit design graphical computer tools are used in this course for
computer-aided design and as an introduction to review Boolean algebra as
well as combinational and sequential logic.

Estimated ABET Category Content:           Engineering Science: 2 units or 67%
Engineering Design: 1 unit or 33%

Grading:             2 Midterms (@100 points each)               200 Points
Homework/Quizzes                     100 Points
Lab Projects                         100 Points
Final Exam                           150 Points
`                        Total              550 Points

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