VIEWS: 33 PAGES: 58 POSTED ON: 4/21/2011 Public Domain
ECEN 607(ESS) Low Drop-Out Voltage Regulators 1 Analog and Mixed-Signal Center, Texas A&M University Power Management • Why do we need power management? – Batteries discharge “almost” linearly with time. – Circuits with reduced power supply that are time dependent operate poorly. Optimal circuit performance can not be obtained. – Mobile applications impose saving power as much as possible. Thus, the sleep-mode and full-power mode must be carefully controlled. – What is the objective of a power converter? • To provide a regulated output voltage Voltage Battery (i.e. Li-ion) Regulated Voltage Time 2 What are the conventional power converters? – Low drop-out linear regulator (LDO) – Switch-inductor regulator (switching regulators) – Switch-capacitor regulator (charge pump) Why do we need different Power Converters Types? – Different applications – Desired efficiency and output ripple Can we combine them? + Battery SR LDO VREGULATED - + Battery CP LDO VREGULATED - + Battery LDO CP VREGULATED - What is the purpose of combining several converters? 3 Linear Regulator: Principles + RC – Vo must be constant and R R C LOAD RLOAD VO VBAT – VBAT is changing as a function of time - RLOAD VO VBAT RLOAD RC Thus in order to keep constant Vo, the value of the controlling resistor RC yields: V V V V R R C V 1 R V LOAD BAT R LOAD V BAT O LOAD LDO O O O How can we automatically pick the value of RC such that Vo= Vdesired, reg- voltage? RC + VC Feedback RLOAD VO VBAT Control 4 - How can we implement RC and the Feedback Control? ID NMOS Transistor VGS PMOS Transistor a b a b a b VC = VGS ILOAD VC = -VGS = VSG VDO,n= VSAT+Vgs Vdo = ILOADRC VDO,p= VSD(SAT) Can we implement RC as follows? For which applications? RC1 RC2 RC1 RC2 a b a b VC MN MP VC 5 MN and MP are transistors operating in the Ohmic region. Discuss the option. How the feedback control could be implemented? VO VO Error Amplifier R1 Error Amplifier R1 VC,PMOS VC,NMOS R2 R2 VREF VREF • Remarks – Make sure the closed loop is negative – For an ideal op amp gain, the differential input is zero, i.e. R R V V2 0 OR V V V 1 R 1 V R R O UT REG O REF O REF 1 2 2 – VREF is a Bandgap voltage which is also supplied by VBAT=VIN. 6 The efficiency is defined as: P V I V V V OUT OUT LOAD OUT IN DO PIN V I IN LOAD V V IN IN V 1 DO V BAT • Where VDO is the voltage drop across the pass transistor, i.e. VDS • The output error voltage (EVO) is defined as: R E C 100% R R VO C LOAD OR V V E VO OUT MAX OUT LOAD 100% V OUT MAX 7 LDO Analysis • Let us analyze the basic LDO architecture. First, we will consider ideal components, then the non-idealities are introduced together with the accompanied design challenges to tackle VIN Error Amplifier Ref VX gm( Vx – ViN ) rop VIN = VBAT PMOS Pass Transistor AEA VIN AEA( VDIV - VREF) Vo R1 R1 Io VDIV VDIV RL Load (RL) R2 R2 Basic LDO Topology Small Signal Representation 1 1 1 VIN 1 g m VDIV 1 g m AEA g m AEAVREF VO r R (1) rop RL R1 op 1 1 1 V VDIV O 0 R R R (2) 1 2 1 8 Solving the (1) and (2), Vo becomes: Vin (1 APT ) VREF APT AEA Vo rop [1 APT AEA ] RL Where: APT g m rop , R2 /( R1 R2 ), and ( R1 R2 ) R L Thus Vo can be expressed as: Vin APT V A A Vo REF PT EA (1 APT AEA ) (1 APT AEA ) Vin T / AEA V T If T APT AEA Vo yields: Vo REF (1 T ) (1 T ) T is the open loop gain. Furthermore for T >>1 Vin V Vo REF AEA 9 Observe that Vin is attenuated by AEA and Vref is not. Line Regulation The line regulation is a steady-state specification. It can be defined as: V o APT APT LR Vin (1 APT AEA ) 1 APT AEA V 1 L o V A R in EA For a practical case with non-idealities such as offset Op-Amp voltage Vos and reference voltage error i.e. V ref ; the line regulator becomes: Vo 1 R V Vos 1 1 REF Vin AEA R2 Vin Observe that designers should also minimize: Vos and provide Vref to be independent of VBAT and temperature and process variations. 10 Note that Rc given in page 3 for a transistor can be expressed as: VDS V VBAT Vo RC RLoad DS RLoad V I OUT Vo o In order to maintain the regulation the transistor must operate properly NMOS case Vin VDS VC ID Io Exercise: Repeat the above case for a PMOS case 11 Load/Line Regulation Let us assume the error amplifier is a transconductance amplifier of value GEA and α is the current gain of the pass transistor i.e. Thus Io Vo I o Req I o ( R1 R2 ) // R L Vo I o RL R1 Furthermore: GEA ∆VDIV RL RL I o G EAV DIV Req G EA R2 /( R1 R2 )Vo Vin Vo+∆Vo Then, the load regulation can be expressed as: R2 Vo 1 R1 1 VREF I o GEA R2 Or line regulation: Vo 1 R1 1 1 Vin GEA R2 R R DS L 12 Efficiency Calculation Example of efficiency: A 3.3V LDO with 3.7 V < Vin < 4.71V, 100mA < Io < 150mA Io,q (maximum quiescent current) = 100 μA I o max Vout ,nominal ( I o max I o,q ) Vin ,max 150 mA 3.3 100 70 % (150 mA 100 A) 4.71 The output current can be represented as a pulse for simulation purposes Io,max OR Io,max Io,min Io,min t0 t1 t0 t1 t3 t4 13 LDO ESR Stability One of the most challenging problems in designing LDO is the stability problems due to the closed loop and the parasitic components associated with the pass transistor and the error amplifier. In fact to compensate the loop stability a large external capacitor is often connected at the output. i.e. Vo 1 s / wL Z CL (s) sC L Im RESR Re -wL CL w L 1 / RESR C L Where CL is of the order of μF with a small equivalent series resistor (RESR). 14 LDO Parameters 1 • Dropout voltage (Vdo); This is the difference between the minimum voltage the input DC supply can attain and the regulated output voltage. • Input rail range; This is the input supply voltage range that can be regulated. The lower limit is dependent on the dropout voltage and upper limit on the process capability. • Output current range; This is the output current handling capability of the regulated output voltage. The minimum current limit is mainly dependent on the stability requirements and the maximum limit dependent on Safe Operating Area (SOA) of pass FET and also maintaining output voltage in regulation. • Output capacitor range; This is the specified output capacitance the regulator is expected to accommodate without going unstable for a given load current range. • Output regulated voltage range; This is the output voltage variation the regulator guarantees. When output voltage is in this range, it is said to be in regulation. • Load regulation; This is the variation in output voltage as current moves from min to max 15 LDO Parameters 2 • Line regulation; This the variation in output voltage as supply • voltage is varied from minimum to maximum. • PSR; Power Supply Rejection ( or ripple rejection) is a measure of the • ac coupling between the input supply voltage on the output voltage. • Load/Line transient regulation; This is a measure of the response speed • of the regulator when subjected to a fast load/Vsupply change. • Short circuit current limit; This is the current drawn when the • output voltage is short circuited to ground. The lower limit is • determined by the maximum regulated load current and the upper • limit is mainly determined by the SOA and specified requirements • Power Efficiency; This is the ratio of the output load power • consumption to input supply power. Linear regulators are not really • efficient especially at high input supply voltages. • Overshoot: It is important to minimized high transient voltages at start-up and during load and line transients. • Thermal Shut down: This is needed to protect the part from damage 16 Conventional LDO: Modeling Close Loop Schematic Open Loop Transfer Function: TF H1 H 2 H 3 H 4 VIN g R g m3 R A H H2 R A CGS AV 1CGD s 1 m1 p Error Amplifier PND1CGs R C s 1 1 p p VREF PD C Rds g mp RPAR RESRC L s RPAR H4 R2 H3 R2 R1 PND2 Vout RPAR RESR CL s 1 B CGD R1 CL 1 Av g mp R par RPAR Rds R1 R2 RL Rds A D RL I ds z 1EH RPAR : Output impedance 1EF R2 RESR RL : Load resistance VTest RDS : Drain to source impedance of the pass transistor Loop Breaking Point for Stability Analysis R1 &R2 : Feedback Resistors Open Loop Block Diagram Vdropout 200mV VDSSATPass 200mV Vdropout : Minimum voltage drop across the input and output terminalsof the LDO with shich the system is able to regulate. VDSSATPass : Vdsat of the pass transistor W W p Cox VDSSATPass 2 1 2I D ID 2 L L p Cox VDSSATPass 2 W Note: The error amplifier is a two-stage amplifier without miller compensation g 2 C i 17 L mp p ox load Error Amplifier AEA ROUT Dominant pole Cgate R 01 Two stage amplifier without miller compensation A g R g R o m1 01 m8 out g R g GBW m1 o1 m8 Notes: C gate 1. CGATE is connected to output node. 2. Miller Compensation is not required since the dominant pole is at the output. 18 Matlab/Simulink Macromodel Pass Transistor Dominant Pole / Compensation Zero Transconductance Non-dominat Pole due to Pass Transistor Gate Capacitance Error Amplifier Nondominant Pole Feedback Factor Formulas and Component Values R2 44e 3 K C 10F C gd 30 pF Gm1 15.62A / V g 80e 6 i R1 R2 o mp 0.6e 6 load R1 420K Vdsat 200mV C gs 50 pF R p 64k Vout RL Ra 7.36M C p 100 fF iload R2 240K iload 50mA 1 Vout 3.3V resr 5 0.1 Gm3 1.35mA/ V R 19 DS i load Simulation Results From Simulink z Loop Gain and Phase P ND 2 P ND 1 P D Loop Gain ~ 100dB Fu ~ 2.7MHz 1 Phase boost due to Compensation Zero Z C R L ESR PM ~ 90° 20 Open Loop Gain and Phase Under Load Variation Notes: 1-Open Loop System 2- Load Variation (iload varies from 10mA to 50mA) 3- The load variation (iload) was simulated in Matlab using a “for loop” 21 Simulation Results From Matlab Step Response Vout varies from 0 to 3.3V Vin varies from 0 to 3.5V 22 Power Supply Rejection Vsupply Problem: Low frequency and high frequency noise affects the operation of the highly sensitive circuits External noise is mainly coupled through the supply lines A regulator (LDO) is mandatory with high PSR 23 Power Supply Rejection Existing Solutions VIN VIN VIN VDD VIN Current Solutions: RC filtering: Larger drop-out voltage, and larger power consumption Cascading of LDO: Larger area, power consumption, larger drop- out voltage Combined RC filtering and cascading: Larger area and power consumption, larger drop-out voltage and complexity 24 Enhancing PSR over a wide frequency range Proposed Topology • The NMOS cascode, MNC, shields the entire regulator from fluctuations in the power supply. • MNC gate needs to be biased at a voltage above the supply using a charge pump. • MNC acts as a voltage follower for noise at its gate, it is critical to shield the gate of MNC from supply fluctuations using an RC filter to shunt supply ripple to ground. G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance ,” ISSCC, feb. 2007. 25 Enhancing PSR over a wide frequency range • With the help of an NMOS cascode, a charge pump, a voltage reference and an RC filter to shield the entire regulator from power supply fluctuations, a 5mA LDO regulator utilizing 60pF of on-chip capacitance achieves a worst- case PSR performance of -27dB over 50MHz. G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance ,” ISSCC, feb. 2007. 26 Stability and PSR Simulations • Stability test (Open Loop) Frequency Response Open loop gain shows a low pass frequency response AC signal is injected here Loop Gain ~ 65dB Fu ~ 10MHz PM ~ 60° 27 Stability and PSR Simulations (Continue) • PSR simulation AC signal is injected here PSR versus Frequency PSR curve shows a Quasi-Band Pass frequency response it is less than -40 dB up to 10KHz, -30 dB at 100 KHz 28 Different Compensation Techniques for Stability Purposes • Internal zero generation using a differentiator – An auxiliary fast loop (differentiator) provides both a fast transient detector path as well as internal ac compensation. – The simplest coupling network might be a unity gain current buffer. – Cf senses the changes in the output voltage in the form of a current that is then injected into pass transistor gate capacitance. Robert J. Milliken, Jose Silva-Martínez, and Edgar Sánchez-Sinencio “Full on-chip CMOS low-dropout voltage regulator,” 29 IEEE Trans. on Circuits and Systems – I, pp 1879-1890, vol. 54, Issue 9, Sept. 2007. Different Compensation Techniques • Capacitive feedback for frequency compensation – It introduces a left hand plane zero in the feedback loop to replace the zero generated by ESR of the output capacitor. – the capacitor is split into two frequency-dependent voltage-controlled current sources (VCCS) and grounded capacitors. – Instead of adding a pole–zero pair with zero at lower frequency than the pole, in this technique only a zero is added. – It needs a frequency dependent voltage control current source (VCCS). 30 Chaitanya K. Chava, and Jose Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 1041-1050, June 2004. Different Compensation Techniques • DFC frequency compensation – It is a pole-splitting compensation technique especially designed for compensating amplifier with large-capacitive load. – DFC block composed of a negative gain stage with a compensation capacitor Cm2, and it is connected at output of the first stage. Another compensation capacitor Cm1 is required to achieve pole-splitting effect. – The feedback-resistive network creates a medium frequency zero for improving the LDO stability. 31 K. N. Leung, and P.K.T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol.38, no.10, pp.1691-1702, Oct. 2003. Different Compensation Techniques • Pole-zero tracking frequency compensation – To have pole-zero cancellation, the position of the output pole po and compensation zero zc should match each other. – The resistor is implemented using a transistor Mc in the linear region, where its value is controlled by the gate terminal. K. C. Kwok, P. K. T. Mok. “Pole-zero tracking frequency compensation for low dropout regulator,” 2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735-738,May 2002. 32 Fast Transient Response • A current-efficient adaptively biased regulation scheme is implemented using a low- voltage high-speed super current mirror. It does not require a compensation capacitor. • The adaptively error amplifier drives a small transconductance (MA9) to modulate the output current IOUT through a transient-enhanced super current mirror. Yat Lei Lam, Wing-Hung Ki, “A 0.9V 0.35µm Adaptively Biased CMOS LDO Regulator with Fast Transient Response,” 2008 IEEE International Solid-State Circuit Conference, February 2008. 33 Noise in Linear Regulators • LDO noise is sometimes confused with PSRR PSRR is the amount of ripple on the output coming from the ripple of the input. On the other hand, noise is purely a physical phenomenon that occurs with the transistors and resistors (ideally, capacitors are noise free) on a very fundamental level. • Primary noise sources: 1. Bandgap-Reference (Primary source of noise) Possible solution: add a low-pass filter (LPF) to the output of the bandgap. – Drawback: it can slow down the output startup. 2. The resistor divider ( thermal noise = 4KTR ) Possible solution: Use resistors as small as possible. – Drawback: Smaller resistors burn more current through the feedback divider. Possible solution: add a capacitor across the top resistor in the resistor feedback divider. At high frequencies it reduces the close loop gain and thus the noise. – Drawback: it could slow down start-up time significantly, since the capacitor would have to be charged by the current in the resistor divider. 3. Input stage of the error amplifier (thermal and flicker noise) Possible Solution: Large input drivers. – Drawback: larger area. • Second order noise sources: – Load current and output capacitance (Phase Margin) • Low phase margin will cause peaking in the close-loop gain and since the close-loop gain amplifies this noise, the total output noise increases. 34 Reference: J. C. Teel, “Understanding noise in linear regulators” Analog Application Journal, 2Q 2005, www.ti.com/aaj LDO Design Example Conventional LDO Parameters Specifications VIN 3.5V Error Amplifier VOUT 3.3V ILoad 0mA-50mA Pass Transistor VREF VOUT IQ < 100µA Technology 0.5µm CMOS R1 CL RL R2 RESR 35 Design Flow Diagram Vin Vout ILoad Vdropout RL W/L Design Error Amplifier CGate RDS Cp Rp RA Calculate non dominant poles: PND1, PND2 Adjust poles and zeros locations using CL and RESR Check stability Check transient, PSR, load regulation, line regulation, … 36 LDO Design Example Since Vdropout 200mV VDSSATPass 200mV W W p Cox VDSSATPass 2 1 2I D ID 2 L L p Cox VDSSATPass 2 Assuming µPCox= 65µA/V2 the pass transistor size can be calculated by: W 38,462 L In order to minimize the gate capacitance, we use minimum length L = 0.6µm W 38462 0.6m 23mm The gate capacitance of the pass transistor is given by the following equation: C C g R 1C gate GS mp par GD 2 1 where C W L C C W L C RPAR Rds R1 R2 RL Rds GS 3 ox GD D ox I ds 37 Design Example (Continue) The values of CGS and CGD can be also obtained if we run a dc simulation and verify the operating point of the pass transistor. Using the last method, we found: 1 R DS 15 C 26 pF GS C 7.6 pF GD g ds R R1 and R2 are calculated using : V OUT 1 R 2 V REF 1 Assuming a reference voltage of 1.2V and choosing R1 = 240K, We found R2 = 420K . V 3.3V R L OUT 66 R 15 420 K 240 K 66 12 PAR I LOAD 50mA W 23e 3 G 2 C i 130e 6 50e 3 50mA / V 2 L 0.6e 6 mp p ox load C gate C g R 1C 36.5 pF GS mp par GD 38 Design Example (Continue) Error Amplifier Design and Considerations – High DC Gain to guarantee high loop gain over the range of loads (AV > 60dB) – Low output impedance for higher frequency pole created with CGS of pass transistor – Internal poles must be kept at high frequencies, preferably > fU of the system (~1MHz) – Low DC current consumption – Low Noise Error Amplifier schematic The error amplifier is implemented using a two stage without miller compensation topology in order to achieve a gain larger than 60dB and GBW =7MHz using 0.5µm CMOS technology 39 Design Example (Continue) Error Amplifier Simulation Results Magnitude Plot Phase Plot A 65dB o GBW 7.6 MHz PM 51 Note: This results were obtained using Cgate = 36.5pF as the load 40 Design Example (Continue) z Pole / Zero Locations P ND 2 P ND 1 P D Dominant Pole Location Second non-dominant pole location 1 1 P 1.2 KHz P 7.3MHz 2 R R C ND 2 D PAR ESR L RC p p First non-dominant pole location Zero location 1 P 1 5.3KHz Z 3.2 KHz ND 1 RC A Gate R C ESR L Notes: 1- RA was obtained from simulations. Basically, it is the output resistance of the error amplifier. 2-PND2 is greater than 7.3MHz since the phase margin of the amplifier is around 51°. This is good news since we want this pole to be located above the gain bandwidth product of the overall system. 3- RESR equal 5 was chosen for stability reasons (see next slide). 41 Design Example (Continue) Stability versus RESR UGB versus RESR Phase margin versus RESR Note: RESR was swept from 0 to 10 42 Design Example (Continue) System Simulation Results Magnitude Plot (IL=50mA) Phase Plot (IL=50mA) Phase Margin = 55° DC Gain = 74dB UGB = 6.3MHz Magnitude Plot (IL=100µA) Phase Plot (IL=100µA) Phase Margin = 90° DC Gain = 75dB UGB = 172KHz 43 Design Example (Continue) System Simulation Results VIN Step Plot IL Step Plot V 3.30352V V 3.30206V 2 4 V 3.30238V 3 V 3.30238V 1 V V 1.17 mV Load Regulation = 2 1 0.0234V / A I I L2 50mA L1 V V 313V Line Regulation = 2 1 0.0031V / V I I L2 100mV L1 Notes: 1- VIN step from 3.4 to 3.5V 44 2- ILOAD step from 0 to 50mA Design Example (Continue) System Simulation Results PSR versus Frequency PSR @ 100KHz = -35dB 45 Summary of the Results Parameters Results VIN 3.5V VOUT 3.3V ILoad_max 50mA ILoad_min 0mA IQ 30µA PSRR@100KHz -35dB Line Regulation 0.0031V/V Load Regulation 0.0234V/A TR 1µs Technology 0.5µm CMOS 46 Current Efficient LDO For low IL, for R1+R2 >> Ro_pass Note that RL is significantly larger Loop Gain: 1 I L Ro _ pass //(R1 R2 ) Ro _ pass Av AEA g mp Ro _ pass w p1 Ro _ pass Co Co 2 KI L W pCox Av AEA K I L L p 2 For no-load current 2 K g mQ1 Av AEA w p3 2 KI bias IL C par C par AEA g ma Roa 47 Current Efficient LDO GB Avw p1 AEA g mp Ro _ pass / Ro _ passCo GB AEA g mp / Co 2 AEA KI L / Co 2 g ma Roa KI L / Co Note that GB will change as I L changes, this effects modify the pole-zero locations and the phase margin. i.e., GBMAX 2 AEA KI L,max / Co ; w p1 GBMIN 2 AEA KI L,min / Co ; w p1 Due to current mirror when load current exist, then we have 2 KI bias I L / N w p3,load w p1 GB w p 3,load ; make , C par I L I L I L 2 1 C or par KN 2 I bias C par NI L 1 2 C 2 C par KN 2 I bias NI L Co o 1 The zero is located at: w z |Cb Co Co RESR 1 Another pole is located at the output of the AEA, w p 2 Roa C pa G. A. Rincon-Mora, P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” 48 IEEE J. Solid-State Circuits, vol.33, no.1, pp.36-44, Jan. 1998. To determine the stability one can consider the open loop gain defined as: Aopen s A 1 w Avo vo v A fb z s s open v s 1 ref 1 1 w w w p1 p2 p3 where wp1 wz wp2 wp3 1 Avo g ma Roa g mp Ro _ pass w w w w p1 z p2 p3 R 1 2 R 1 Stability imposes the following conditions: A ( jw ) 1 open o Where wo is defined as: ARG A ( jw ) 0 open o Or A ( jw ) 1 open o where w GB o Phase Margin: 180 ARG A jw M open w w w w 180 tan 1 tan 1 tan 1 tan 1 w w w w 49 M z p1 p2 p3 For w w GB ; o M is the arbitrary phase margin w GB GB 180 tan M w 1 o tan A tan 1 vo 1 w tan 1 w z p2 p3 In order to determine an approximated relation between wp3 and GB several assumptions are required. Avo >> 1, Then tan-1(Avo) 90° wo Avow p1 R ESR Avo wz wz Ro _ pass wo RoaC pa Avo wz Ro _ pass Co Thus one can write R Roa C pa GB 90 MX tan 1 ESR Avo tan 1 Avo tan 1 R R Co w o _ pass o _ pass p3 50 Cadence Simulation • This current efficient LDO is implemented using 0.5 μm CMOS process • The LDO provides a 3.3 V regulated output voltage from a 3.5 V supply, for a load current IL ranging from 250 μA to 25mA • The current in the buffer ranges from 20μA (which is only the bias current) in case of ILmin to 180µA in case of ILmax. • The output voltage for load current alternating between ILmin and ILmax is shown. 51 Cadence Simulation iload 25 mA Vout 3.3V Loop Gain ~ 52dB Fu ~ 0.78MHz PM ~ 82° 1 RESR 100 m C 10F wz 1M o RESRCo 1 Ro _ pass 8.5 C 10F w p1 11 .8 K o Ro _ pass Co 1 Roa 900 k C pa 1 pF w p2 1.1M Roa C pa 1 R par 400 C par 3 pF w p3 833 .33 M 52 R par C par Cadence Simulation • ωz cancels ωp2 and the phase margin can be approximated to: GB M 90 tan 1 90 tan 1 2 0.78 89o w 833.33 p3 • Which is close to the simulated value of 82o • The step response for this case of ILmax is shown where Vin varies from 0 to 3.5V and accordingly Vo varies from 0 to 3.3V • For the case of ILmin of 250µA, the dominant pole becomes even smaller and very far away from ωp3 and so the phase margin is almost 90o 53 Simulation Results From Simulink Loop Gain and Phase Fu ~ 5.4MHz Loop Gain ~ 51.8dB PM ~ 90° 54 Open Loop Gain and Phase For Different wp3 Locations PM 90° wp3 100GBW PM 45° wp3 GBW Notes: 1-Open Loop System 2- The location of wp3 was varied 3- The variation (wp3) was simulated in Matlab using a “for loop” 55 Current Limiters Architecture Courtesy of Tuli Dake from TI 56 ILIM Op Amp 57 References [1] G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS miller-compensated LDO regulator with -27dB worst-case power-supply rejection using 60pF of on-chip capacitance ,” ISSCC, Feb. 2007. [2] L.-G. Shen et al., “Design of low-voltage low-dropout regulator with wide-band high-PSR characteristic,” International Conference on Solid-State and Integrated Circuit Technology, ICSICT, Oct. 2006. [3] R. J. Milliken, J. Silva-Martínez, and E. Sánchez-Sinencio, “Full on-chip CMOS low- dropout voltage regulator,” IEEE Trans. on Circuits and Systems – I, pp 1879-1890, vol. 54, Issue 9, Sept. 2007. [4] C. K. Chava, and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 1041-1050, June 2004. [5] K. N. Leung, and P.K.T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol.38, no.10, pp.1691-1702, Oct. 2003. [6] K. C. Kwok, P. K. T. Mok. “Pole-zero tracking frequency compensation for low dropout regulator,” 2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735-738, May 2002. [7] J. C. Teel, “Understanding noise in linear regulators” Analog Application Journal, 2Q 2005, www.ti.com/aaj [8] K. N. Leung, P. K. T. Mok, and W. H. Ki, "A novel frequency compensation technique for low-voltage low-dropout regulator," IEEE International Symposium on Circuits and Systems, vol. 5, May 1999. [9] G. A. Rincon-Mora and P. A. Allen, "A low-voltage, low quiescent current, low drop-out regulator," IEEE J. Solid-State Circuits, vol.33, no.1, pp.36-44, Jan. 1998. 58