Docstoc

215_full

Document Sample
215_full Powered By Docstoc
					International Conference on Science, Technology and Innovation for Sustainable Well-Being
(STISWB), 23-24 July 2009, Mahasarakham University, Thailand


Designing Vector Summation Signal Circuit
    by High-Precision CMOS Inverter
                      Bancha Burapattanasiri1,2*, Phaiboon Booppha1,2
     1
      Department of Electronic and Telecommunication Engineering, Faculty of Engineering
             2
               Engineering Collaborative Research Center, Faculty of Engineering
                     Kasem Bundit University, Bangkok, Thailand 10250
                              E-mail: bancha_bu@eng.kbu.ac.th*

                                  Sanchaiya Pasomkusolsil
                  Department of Electrical Engineering, Faculty of Engineering,
                      Kasem Bundit University, Bangkok, Thailand 10250

                                              Abstract

   This paper presents the designing vector summation signal circuit by high-precision CMOS
inverter. To using 0.5 µm CMOS technology and + 1.5 V power supply. The circuit consist of
three parts are CMOS inverter circuit, differential amplifier circuit and square-rooter circuit. The
designing circuit has received voltage input and output signal, used a lower of MOS transistors,
noncomplex circuit, high precision, low error and low power consumption. The simulation result
of MOS transistors in saturation and non-saturation period to analysis circuit by the PSpice
program.

Keywords: high-precision, inverter, summation circuit.


1. Introduction                                        2. Designation and Functional
   Vector summation circuit is popular in                 Designing vector summation signal circuit by
communication technology. It useful for                high-precision CMOS inverter has three part of
measurement and circuit analyzing. A majority          circuit as for part 1. CMOS inverter circuit, it has
of research is present MOS transistor function in      function to invert phase input signal was receive
voltage and current mode. Moreover CCII circuit        high-precision, low error and high speed. Part 2.
has designed to receive two input only [1], high       Differential amplifier circuit, it has functioned to
error and low precision output signal, because of      square formulae circuit.
a majority in designing may be has DC voltage
interfere output signal [2-4]. This paper is
present designing vector summation signal
circuit by high-precision CMOS inverter, to              VX          (VX)2         VX2  VY2  ....  VN2   VO
suitable in establish high IC circuit, because of
this circuit has designed noncomplex circuit,
used MOS transistor in saturation and non-
saturation period function combination to CMOS           VY          (VY)2
inverter, differential amplifier and square-rooter
circuit. The result from three circuit is a lower of
MOS transistor, but still high quality working,
+ 1.5V power supplies, high precision, low error         VN          (VN)2
and low power consumption. The propose of this
research doesn’t want to error in circuit, so the      Fig. 1: Vector summation signal circuit by high-
designing is setting K of MOS transistor to equal.     precision CMOS inverter diagram.
International Conference on Science, Technology and Innovation for Sustainable Well-Being
(STISWB), 23-24 July 2009, Mahasarakham University, Thailand

    Part 3. Square-rooter circuit, it has functioned                         VDD  Vtp  Vtn  n /  p 1 / 2 
                                                          then       Vin                                             (7)
                                                                                   1   n /  p 
to square root of differential amplifier circuit to
                                                                                                  1/ 2         
unite by MOS transistor working in saturation                                                                  
And non-saturation period. For easier to
understand in summation circuit see diagram               If a symmetry point of circuit in equation (8)
fig. 1
                                                                               Vin  Vout  VDD / 2                      (8)
2.1 CMOS inverter circuit.                                by              n   p and Vtn  Vtp                        (9)
   From the fig. 2 show CMOS inverter circuit
component by M1, M2, M3 and M4. So, Sending               so                      Vout  Vin                           (10)
input signal has to positive and negative phase
entrance pin-gate M1 and M2 it will two MOS               2.2 Differential amplifier circuit
transistor serration working. To be a result of              From the fig. 3 is show a differential amplifier
CMOS inverter designed working in MOS                     circuit component M5 and M6. Functional of
transistor saturation.                                    circuit is working when M5 and M6 receive
                                                          signal from CMOS inverter circuit, and to setting
                                                          MOS transistor working by square formulation.
                                VDD
                                                          The relation M5 and M6 current able to show [5]

                                 M3

                                                                                              RL
                                 M1
               Vin                      Vout
                                 M2
                                                                         Vin            M5 M6               -Vin
                                 M4


                                VSS

Fig. 2: CMOS inverter circuit                             Fig. 3: Differential amplifier circuit

So we can computable output–input relation of                               I RL  I DM 5  I DM 6                      (11)
CMOS inverter by
                                                          by            I DM 5  K 5 (Vin  Vss  VT ) 2                (12)
         I DM 1  I DM 3 and I DM 2  I DM 4        (1)   and         I DM 6  K 6 (Vin  VSS  VT )       2
                                                                                                                        (13)

An equation current of MOS transistor saturation          Instead of an equation (12) and (13) in to (11)
working is                                                then the result is

       I D  K (VGS  VT ) 2 ; (VGS  VT ) VDS     (2)                                 
                                                           I RL  K5 (Vin  VSS  VT )2  K6 (Vin  VSS  VT )2       (14)
                  ins O  n
When        K                  and   K (W / L)   (3)   From the designing is setting K5=K6=K
                      D

Whence (1) equation and CMOS inverter circuit
                                                          so                        
                                                                      I RL  2K (Vin ) 2  (VSS  VT ) 2               (15)
value to result is
                                                          2.3 Square-rooter circuit
                     I DM1  I DM 2                (4)       From the fig. 4 is show a square-rooter circuit
                                                          component M13 and M14. The circuit designing is
                      p
and        I DM 1          Vin  VDD  Vtp 2     (5)   setting M13 work in saturation period, and M14
                        2                                 work in non-saturation period. The circuit
                                                         relation show as an equation current [6]
                I DM 2  n Vin  Vtn 
                                        2
                                                    (6)
                           2
International Conference on Science, Technology and Innovation for Sustainable Well-Being
(STISWB), 23-24 July 2009, Mahasarakham University, Thailand
                                                               VDD
         I DM13  K (VDM13  VO  VT ) 2                (16)
                                   V 
                                      2

     I DM 14  K (VDM 14  VT )VO  O                 (17)             M3
                                                                                             M14
                                                                                                             M9                   M17
                                                                               IS       VO
                 
                                    2                                                     M13
                                                                         M1                                  M7                   M15
                                                               VX                                                  VY                      VN

                             IRL                                         M2                                  M8                   M16
                                                                                M5 M6              M12 M11              M20 M19
                       M13                                               M4                                  M10                  M18
                                   VO
                       M14
                                                               VSS
                                                               Fig. 5: Completely vector summation signal
Fig. 4: Square-rooter circuit
                                                               circuit by high-precision CMOS inverter.
From fig. 4 if I DM 13  I DM 14 so, the relation
                                                                   From equation (15). It has offset voltage, so
Voltage output Circuit computable by                           it have to decrease offset voltage before use. In
                                                               this test use I S  2(VSS  VT ) 2  (0.1) 2 current
                   I DM 13
     VDM 14                VO  VT                    (18)   source for decrease offset voltage and when we
                      K                                        bring output current from (15) sending to square-
                                                               rooter circuit, so the relation as (21), then the
When instead result of an equation (18) to (17)                output relation of vector summation signal circuit
the new result is                                              by high-precision CMOS inverter is

                       I                      V 2                                   1
I DM 13  I DM 14  K  DM 13 VO  VT  VT VO  O 
                                           
                                                        (19)         VO  0.732           (2KVX2  2KVY 2  ...  2KVN2 )               (22)
                       K
                                                2 
                                                                                       K
         VO 2    I DM 13 2                                                    VO  1.035 VX2  VY 2  ...  VN2                         (23)
     K        K        V0  I DM 13  0                (20)
          2         K
                                                               3. Simulation and measurement result
From equation (20) is able mathematic                             The result from presented completely vector
calculation to finding VO then the result is square            summation signal circuit by high-precision
root of Drain current as (21)                                  CMOS inverter. It has simulation and
                                                               measurement result of working circuit from
                   0.732                                       PSpice program for testing and analize by
            VO          I DM 13                        (21)   sending voltage input signal as (24) and (25)
                      K                                        when setting VDD = 1.5 V, VSS = -1.5 V and
                                                               W/L = 0.5µm
2.4 Completely vector summation signal
circuit by high-precision CMOS inverter.                                                VX  0.1sin 2000 t                             (24)
    This research presented vector summation
signal circuit by high-precision CMOS inverter,                                         VY  0.1sin 2000 t                             (25)
it has been high precision, low error and used a
lower of MOS transistor for made a low power.
So, from three part of circuit when bring it to
connect for find all circuit relation by equation
(10) of CMOS inverter circuit. If we fix Vin= VX
and VY, so the output result of CMOS inverter
circuit is –VX and –VY, while differential
amplifier circuit has connected to CMOS inverter
circuit and square-rooter circuit has connected to
differential amplifier circuit then the new result
is relate to all of circuit result. So it is able to           Fig. 6: The result from sending input signal as
establish output circuit equation as (22) and (23)             (24) when fix VY in equation (25) = 0 V
International Conference on Science, Technology and Innovation for Sustainable Well-Being
(STISWB), 23-24 July 2009, Mahasarakham University, Thailand

                                                      Kasem Bundit University, Engineering Faculty
                                                      for supporting and give opportunity to our to
                                                      development in knowledge and research, so we
                                                      are special thanks for everything.

                                                      6. References
                                                      [1] Liv, S.I. 1995. Square-rooting and vector
                                                      summation circuit using current conveyer. Proc.
                                                      IEEE Circuit Devices Syst, Vol.142, No.4,
  Fig. 7: The result from sending input signal as     August 1995: PP.223-226.
 (25) when fix VX in equation (24) = 0 V              [2] Kiranon, W., Wardkein, P., Sangpisit, W.
                                                      and Kesorn, J. 1996. Vector summation circuit
                                                      using a single current conveyor. EECON19,
                                                      Khonkaen,Thailand, November 7-8, 1996:Vol.2,
                                                      EL 109-112.
                                                      [3] Nobnoob, B., Dejhan, K., Lerkvarunyu. S.
                                                      and Nokyoo, C. 1998. A MOSFET Vector
                                                      Summation      Circuit Design. Ladkrabang
                                                      Engineering Journal Letters, 15: Vol.1, Page 1-5.
                                                      [4] Sakul, S. and Pongtana, K. 2007. + 1.5
                                                      Voltage Power Supply CMOS Vector Summation
                                                      Circuit Design. EECON-30, Kanchanaburi,
Fig. 8: The result from sending input signal as       Thailand, October 25-26, 2007: Vol. 2, EL 04,
equation (24) and (25)                                Page 869-872.
                                                      [5] Chaisayun, I. and Dejhan, K. 1996. A
                                                      Design Technique of The Squaring Circuit
                                                      Using MOSFET. EECON, Khonkaen, Thailand,
                                                      Vol.2,No.19, November 7-8, 1996 : EL10-14.
                                                      [6] Sakul, C., Dejhan, K. and Sailee, W. 2002.
                                                      Low Voltage Squaring and Square-root Circuit.
                                                      Ladkrabang Engineering Journal, Letters, 19:
                                                      Vol.1, Page13-18.

                                                      About the Authors
Fig. 9: The result from sending input signal at
VX  0.1sin 2000 t and VY  0.1cos 2000 t                           Bancha Burapattanasiri received
                                                                      the     master      degree      in
                                                                      Telecommunication Engineering,
4. Conclusion
                                                                      from King Mongkut’s Institute of
   From completely vector summation signal
                                                                      Technology Ladkrabang in 2008.
circuit by high-precision CMOS inverter has non
                                                                      He is a lecture of Electronic and
complication of working, reduce MOS transistor
                                                      Telecommunication Engineering, Faculty of
and current supplies working at input and output
                                                      Engineering, Kasem         Bundit      University,
voltage mode, high precision and low error. The
                                                      Bangkok, Thailand. His research interests analog
simulation circuit result able to confirm a quality
                                                      circuit design, low voltage, high frequency and
of working by PSpice program and the result as
(23)                                                  high-speed CMOS technology.
                                                                      .
                                                                      Phaiboon Booppha received the
5. Acknowledgement                                                    master degree in Telecom-
   The researchers , we are thank you very much                       munication Engineering, from King
to our parents, who has supporting everything to                      Mongkut’s Institute of Technology
us. Thankfully to all of professor for knowledge                      Ladkrabang in 2005.He is a lecture
and a consultant, thank you to Miss Suphansa                          of Electronic and Telecommu-
Kansa-Ard for her time and supporting to this         nication Engineering, Faculty of Engineering,
research. The last one we couldn’t forget that is     Kasem Bundit University, Bangkok, Thailand.

				
DOCUMENT INFO
Shared By:
Categories:
Stats:
views:15
posted:4/21/2011
language:English
pages:4