Review of Research Paper Digital Electronics Dr. Fahim Arif NUST 1- Explain the proposed checker for a 3 input and 4 input circuits.
We need a checker to generate an extra output such that the parity of output bits for each 2^n combination of inputs is equal to parity of n input bits. There’s also a comparator to check for errors if the parity are different for input and output. 3-input circuit: A 3 input circuit will be needing 2^3 minterms that is 8 minterms, the number of functions generated would be 2^(2^3) that is 256. For each possible function we need to check the feasibility of the proposed approach when the parity used for the checker function is equal to or different from that of the inputs for a given minterm. The table is given below:
The no of a fn is defined by the set of output bits generated by that fn of all minterms with the bit corresponding to first minterm being the most significant one.
4-input circuit:
A 4 input circuit will be needing 2^4 minterms that is 16 minterms, the number of functions generated would be 2^(2^4) that is 65536. For each possible function we need to check the feasibility of the proposed approach
when the parity used for the checker function is equal to or different from that of the inputs for a given minterm. For each of these fns, we can decide to generate the parity of the outputs equal to that of the inputs or its complement. Therefore the total no of possible combinations grows very fast with the no of inputs.
2- Explain in your own words, how the parity function is generated.
Use of Parity of Outputs Equal to the Parity of Inputs: Two separate parity functions have been used for the output of the full adder that is being checked when considering a 3 input circuit. Co is the carry out bit (which would correspond to f23), S is the sum bit (f105), and PCo and PS are the checker functions (f126 and f0) generated according to the rule given before. For each min term the parity of the inputs (i1, i2, and i3) is the same as that of the outputs (Co and PCo for the carry, and S and PS for the sum).
For a 3 input function the parity of all the min terms always remains the same, even parity for min terms m0, m3, m5 and m6 and odd parity for min terms m1, m2, m4 and m7. Therefore, PCo and PS are calculated to provide to the 2 outputs of a min term the same parity of the inputs of that min term. The next logical step is to create a circuit based on that particular function. The checker function defined is as follows:
There are 18 transitions are required for equation (2) but equation (1) requires none. The equations for S and Co are:
Use of Parity of Outputs Different from the Parity of Inputs: PCo and PS are calculated in order to provide to the 2 outputs for a given min term and the parity of inputs for that minterm.
Resulting output tables show the checker function circuits for PS and PCo.
Result: The complexity of the parity generator circuit may vary, for the same main function, depending on the choice between equal or different parities for inputs and outputs.
3- Is it a low cost checker? How?
Yes, it is indeed a low cost checker. Because of the use of low cost XOR gates in the parity verification circuits. Also, the methods used elaborate a 3-input, 2output circuit, and then the results obtained with an exhaustive design space exploration for 3-input and 4-input functions have been presented. The results indicate that the proposed approach becomes more intriguing as the inputs to the circuits are increased. In the following table it is observed that cases in which this approach proposed solves the cases, has overhead less than or equal to that of the duplication with comparison approach is almost the same.
Result: There are many functions, using the approach proposed, which can lead to the provision of an area with an overhead lower than that of the duplication with comparison, and therefore this technique could be a better solution for protection against single errors of the corresponding circuits.