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					Q. Explain the difference the first bit and best fit.                          (10-marks)

    Two widely used algorithms for non- preemptive allocation of variable-sized blocks-
unpaged segments. For examples, are first-fit and best-fit.
     The first-fit method scan the memory map sequentially until an available region RJ of
Ni and more words is found, where Ni is the size of the incoming blocks KI. It then
allocates KI to RJ.
     The best-fit approach requires searching the memory map completely and assigning
KI to a region of NJ  NI words such that NJ- NI is minized.

             Region address                        Sizes (words)

             0                                         50
             300                                       400
             800                                       200


   0                              0                                0

 300         Block K1                     Block K1                      Block K4
                                         Block K4                        Block K5
                                                                  550
                                         Block K5
                                650

             Block K2                       Block K2                    Block K2
  800                            800
                                                                        Block K4
                                                                  900

           Block K3                       Block K3                      Block K3

                (a)                              (b)                          (c)

Figure: 6.34
(a)Initial memory state ;(b)allocation of K4 and K5 by first fit ;(c)allocation of K4 and
K5 by best fit .


                   Cache M1                      Main memory M2

           M1(0)                         M2(0)
           M2(1)                         M2(1)
                                         M2(2)
                                         M2(3)




                                        M2(62)
                                        M2(63)
              Figure: 6.47 Direct-mapped cache with block capacity of two

Eg(6.3)
      MAGNETIC HARD-DISK MEMORY UNIT[QUANTUM CORP.1996].

The XP 39100 is a 9.8 GB hard disk memory in the Atlas II series manufactured by
quantum corp and introduced in the min-1990s.It is housed in a rectangular box whose
dimensions are approximately 14.6x*10.2*4.14 cm. It contains ten 3.5in (8.89 cm)
diameter disks, supplying a total of 20 recording surfaces, each with it own read-write
head fig6.18 summarize the main features of this device. The cited capacity of 9.1GB is
for a formalized disk, which stores a directory and other control information needed to
make the disk drive ready for use. The number of sectors along a track varies from 108 to
108 and each sector within a track accommodates a 512 bytes block. While the sector size
is fixed, the number of sector per track varies due to the fact that the inner tracks are
smaller and can therefore store less than information at the maximum recording density
of the magnetic medium. The average block access time given by equation(6.1) with the
data from fig6.18 is
                     TB=7.9 + 4.2 + 0.6 = 12.7ms
Where TS=7.9ms, r =0.120 revs/ms, n=8 and we take (108+180)/2=144 to be the average
member of sectors per track, implying that N=144*512=73.728 bytes/track.
                                                                                (8-marks)
Solution

       The average block access time (TB) =?
       TS=7.9ms, TL=4ms, n=512B, r =7200rev/min=7200/60=120rev/sec
Average number sector per track =108+180/2=144
The average capacity of track (N) = 144*512=737388/track data-transfer rate (RN) =
120*73728=8.85MBs-1
average data transfer time for one block= n/RN = 512 = 0.0578*10-3 = 8.85 MBs-1



average block = average    + average              + average data transfer
 access time seek time(TS) rationally latency (TL)  time for one block (N/RN)
              = (709 + 402 + 0.06) ms
              = 12.16ms


                                                                       (16- marks)
Example (6.1) A COMMERCIAL 64Mb DRAM CHIP
 Data bus D01:D08
                                        Internal
         Timing and                     control signals                         Data buffer
         refreshing
         control logic


                                   Row
                                   Address
                                   decoder                     8192*1024*8
                                                               storage cell
                                                               array




                                                               Column address
                                                               decoder


                              Row                                               Column address
                              address                                           buffer
                              buffer


   RAS   CAS     WE      OE
   Control lines                          Address bus A0:A12


     Structure of a commercial 8M*8bit DRAM chip


SE 1 operation

           First the row address is transferred to the DRAM by the external device, which
places the row address on the SE is address bus and activates RAS . The master then
places the column address on the address bus and activates CAS . CAS also serves to
indicate that a data word is ready on the data bus (write operation) or that the external bus
is ready to receive a data word (read operation). WE and OE are the write enable and
output enable /mc.

Page mode access
           If a sequence of memory access share the same row address,then it is sufficient
to transfer the row address to the DRAM once at the start of the sequence. This transfer
causes an entire row of data, referred to as a page, to be read out and held in an internal
buffer . A subsequent memory access to the same page needs to transfer only a column
address, thus reducing the receive effective memory cycle time t M .This time is further
reduced by the fact that there is no need to write book and restore the page data every
time a word from it is accessed. A fast access method of this type is called page mode .
Example 6.2 THE RAMBUS DRAM AND INTERFACE [ PRINCE 1996 ]. (10-mks)

 First announced in 1992, this is a proprictary DRAM design with a supporting processor
memory interface that aims to transfer memory data at very high rates over a narrow
processor memory link. Its employs several speedup techniques including a synchronous
interface, address interleaving and eaching inside the DRAM units, very fast signal
timing and stringent electrical design rules. The Rambus data bus is 8 or 9 bits wide,
with the 9th bit typically serving as a parity check. The peak data transfer rate is 500MB/s
which , however is achievable only in burst mode .




                        Rambus              Rambus                      Rambus
                        DRAM R0             DRAM R1                     DRAM Rk



             Sin
             Sout
                                                                                           Data bus D
   Master                                                                                  Bus control
   (CPU)                                                                                   Bus enable
                                                                                           Receive clock
                                                                                           Transmit clock
                                                                                           Power (Vin)
                                                                                           Ground
                                                                                           Vref



            The Rambus DRAM interface .




Rambus operation

                   The master transmits an initial “packet” of information on the Rambus
channel; this packet contains a target memory address and the desired access (read or
write) operation. Each Rambus DRAM chip examines the address and the DRAM unit
R1 containing that address returns either a “ ready “ or a “ busy “ control signal to the
master . If R1 is ready , the master then proceeds to transfer to R1 a data packet of up to
256 bytes ( write case ) or R1 sends the master a data packet ( read case ). If R1 is busy
with an earlier operation when an access request arrives, the master must try again later
and a significant delay in response time occurs.
                                                                             W
  Internal control signals                                                   bits



                                                                         storage
                                               row
       Timing&                                 addres
                                                                         cell
       control                                 -s                        unit
                                               decod
                                               -er




                                                                                    Read /Write drivers
                                                                                    (sense amplifiers)


                                                                                    Data buffer



                             m                                     w
     Control line                Address bus                             Data bus


One dimensional (1-D) random access memory unit.
  One dimensional RAMs to find the total number of cells N is Nx Ny. one


                                                        Storage cell array




                             Row
                             adder-
                             ss
                             decod
                             -er




Address buffer
           X                 Y




          mx                            my

          m                                                        Column address
                                                                   decoder

           Address bus




Two dimensional (2-D) RAM addressing scheme .
           Two dimensional RAM , if Nx = Ny = N ,the number of address drives needed
           is 2 N .Two dimensional RAM use of two one of N addre

Difference between Fig 6.11 & Fig 6.12 (8-marks)



                                                Data D
                                                     4w




                    2m*W               2m*W                2m*W        2m*W
                    RAM                RAM                 RAM         RAM
                   CS WEOE           CS WE OE
 Address                                                  CS WE OE   CS WE OE
   A




           m
 Control lines   CS WE OE




           Increasing the word size of a RAM by a factor of four.
                                                                           2m * w
                                                                                         w
                                                                            RAM


                                                                         CS WE OE




                                                                            2m * w

                                                                                         w
                                                                            RAM


                                                                         CS WE OE
                                   One out
                                    of four
                                   decoder
                                                                          2m * w

                                                                           RAM           w


                        2                                                CS WE OE




                                                                            2m * w

                 M+2        m                                               RAM          w   w   Data
            Address A                                                                             D

                                                                         CS WE OE
          Chip select CS
          Write enable WE
              Output OE

                            Increasing the number of words stored in a RAM by a factor




       Compare FIFO, LRU, OPT and stack.
         FIFO (First-In-First-Out)
         -Hardware implements are easily
         -Hit ratios are many
         -Memory capacity is good but hit ratio is not good. (8-marks)

LRU(Least Recently Used)
-Better than FIFO
-Hit ratios are many
-Can be made by software and hardware
-Used to check by page registers
OPT(Optional Replacement Strategy)
-No marking
-No system
-To get many bit ratios any time
-Tj – Ti = Tk
      ( Tk>>        Tj >Ti)
        Tj = Next block interval
        Ti = Initial interval

Stack
 -Capacity required distinct pages
- Hit ratios are good


Example (6.7)
    DETERMINATION OF HIT RATIOS WITH LRW REPLACEMENT
                                                      (8-
                                               marks)

If letSt = {St (1 ), St ( 2 ),----, St (k ) } denote the stock content at time t . St processing
         requires placing the most recently used page address in the top of stock that the
         least recently used page gets pushed to the bottom .

time
t           1       2        3        4          5       6    7     8     9     10       11        12
address
trace       2       3        2        1          5       2    4     5     3      2        5         2
St(1)       2       3        2        1          5       2    4     5     3      2        5         2
St(2)               2        3        2          1       5    2     4     5      3        2         5
St(3)                                 3          2       1    5     2     4      5        3         3
St(4)                                            3       3    1     1     2      4        4         4
St(5)                                                         3     3     1      1        1         1


n=1
n=2                         Hit                                                                    Hit
n=3                         Hit                      Hit           Hit                  Hit        Hit
n=4                         Hit                      Hit           Hit          Hit     Hit        Hit
n=5                         Hit                      Hit           Hit   Hit    Hit     Hit        Hit




                                     N1 *
  Page-hit ratios       H* =
                                  N1 *  N 2 *


 n    = 1               2         3       4          5       > 5
 H* = 0.00          0.17       0.42   0.50   0.58      0.58


   Problems
 6.1.List the main physical differences between the following memory
technologies.SRAMs,flash memories, magnetic, floppy disks,optical hard disks and CD-
ROMs.

solutions

                     Physical                                                        Typical
                     storage                        Alter                            Acess
technology           medium            Acess mode   ability       Performance        time(tA)

SRAM                 Electronic        Random       Read/write    NDRO,volatile      5ns
                                                    Word read
Flash memories       Electronic        Random       block write   NDRO,nonvolatile   5ns
Magnetic hard
disk                 Magnetic          Semirandom   Read/write    NDRO,nonvolatile   10ns

Optical hard disk    Optical           Semirandom   Read/write    NDRO,nonvolatile   50ms

CDROMs               Optical           Semirandom   Read only     NDRO,nonvolatile   100ms

 6.3.Consider the generic 1-D RAM organization depicted in figure 6.7 .Assume that
storage cell unit is implemented by the DRAM cell of figure (6.9 b).Brifly describe three
ways in which the RAM modified to double its data transfer rate .
( 6- marks )

 Solution

(I)     Use a faster more expensive circuit such as the SRAM cell .
(II)    Use 2D addressing with separate row and column address .Then page mode
        operation can be used in which after the initial transfer of row address ,only
        column address read to be transmitted and restoring write back are eliminated .
        Page mode typically increase a RAM’s data transfer rate .
(III)   Use a s-way address interleaving .

 6.4. A128 MB RAM is to be designed from 2M*4 bit RAM ICs .Assume that 1-out-of 2k
decoder ICs arealso available for k  3, as well as ICs containing standard logic gate .
The main design is to minimize the total number of ICs used. (a) Carry out the design
assuming that each RAM chip has a single chip select line CS and give your answer in
the style of figure 6.11&6.12.(b) Repeat the design assuming that each RAM IC has two
chip .Select lines CS1 and CS2 and is enabled if and only if CS1=CS2=1 .
(16-marks)
 Solution
(a) 128MB = 128M * 8 bits
             = 2 27 * 8 bit
address lines = 27 ( A26 -----A 0 )

data word sizes = 8 bit
Target design is 128 MB RAM = 128M * 8 bit
 Used design is 2M * 4 bit
                         128M * 8bit
 no: of RAM ICs =                   = 64*2 = 128 ICs
                           2M * 4bit

 K > 3 ( K = 6)
     1                                      1
        decoder is needed to decode but decoder are avit .
    64                                      8
  Nine subdecoder free from 1 out of 8 decoder . Each RAM chip has a single chip
select line CS use six address . ( A 26 : A 21 ).




                                                        0   CS
                                                        1
            6                         3       3         2         M 0, 0
                                                        3
                                                        4
                                                        5
                                                        6
                                                    E   7
                                                            CS
                                                                  M 0, 7
                               0
                               1                        0   CS
                                                        1
                               2              3         2        M 3, 0
                          1/8 3                         3
                                                        4
                        decoder                         5
                               4                        6
                                                    E       CS
                               5                        7
                                                                 M 3, 7
                               6
                           E 7

            CS                                          0   CS
                                                        1
                                              3         2         M 7,0
                                                        3
                                                        4
                                                        5
                                                        6
                                                    E   7
                                                            CS
                                                                 M 7,7


                  Fig – 9 decoder and 128 RAM Ics are needed
 (b) Two chip select line CS1 and CS2
    CS1 =CS2 = 1
    If used 1-D = 64 rows
If used 2-D =8-rows * 8-columns
  128MB = 8*8*2*8 bit




                3                         3

                                   CS 2                                1/3
                                                           1    2
                                                                     decoder
                                                     0               3     4     5       6   7

                                      0
                                               CS1

                3                             CS1
                                      1

                                              CS1
                                          2

                             1/3               CS1
                                   3
                           decoder
                                               CS1
                                          4

                                          5
                                               CS1


                                          6
                                               CS1
                               E
                                               CS1
                                          7
                         CS1
                    CS
                                              Fig – 2 ½ decoder and 64M Ics are needed

 6.5. Using the 64 Mb DRAM of Example 6.1 as the basic component , design a 256M;
32 bit DRAM . Include in your answer a diagram in the style of figure 6.11&6.12
 Solution
        8EI DRAM = 8M * 32bit
        Target design = 256M * 32bit
                                          256M * 32bit
         Total number of RAM ICs = p*q =
                                            8M * 8bit
                                        = 25*4 = 32*4 =128ICs
            Total number of address =32
                 Data word size          =8 bit

  Only 13 element address lines are used allowing the BE1 to be used in small ,32 pin
package.

        Two OR- gate allow the external decoder to enable RAS and CAS
simultaneously in four 8E1 is form a selected 8M*32 submemory




         RAS                                      M0        A       D   32
                                                            RAS
       CAS

                              1                             CAS WE OE
                                                       M0
                                                  M1                    32
                                                            A       D
                 5
                        1/32                                RAS

                       Decoder
     A17 : A13                                              CAS WE OE



                                                  M 31      A      D    32   32
                                                                                  D
                        E                                   RAS
                             31
 Chip CS                                                    CAS WE OE
 A( A0 : A12 )
                 13
        WE
        OE

                     Fig – A 256M*32 bit DRAM base on the Micro Tech BE1




             6.6. A16Mb DRAM chip has a word size W=8 bits. Like the 8E1 of Example
       6.1,has a 2-D organization with multiplexed row-column addressing .(a) If the
       column address is 10bits, what is the size of the row address?(b)How many copies
       of this DRAM are needed to make a 1G*32bit memory?

Solution

 16Mb,W=8bit
 (a)16Mb= 2M * 8bit
          = 2 * 220 * 8bit
          = 221 * 8bit
   Total number of decoded address =21bit
                   Word size       = 8 bit

Column address= 10bit(given)
   row address =11 bit
(b) need design =1G*32 bit
    using IC     =2M*8bit
    Total number of DRAM ICs =1G*32bit
                                2M*8bit
                              =230 *32
                                221 *8
                              =29 *4
                              =2048 ICs

6.7. Oscasionally, it is decribeed to implement a small RAM using a singke RAM IC of
     large capacity.For example,DRAM manufactirers sometimes cell RAMs that are
     defective but contain sub-RAMs that are fully operational, these units are used in
     low-cost applications such as toys. Describe how the 64Mb DRAM of figure 6.13
     can be used as a 512k*4 bit DRAM.

Solution

  8E1 DRAM       =8M *8 bit
                  =223 *8 bit
                        =213*210 *8 bit
                  =8192*1024*8 bit
                  =29*210*4 bit
                  =29*1024*4 bit
   Reducing the number of addressing bit from 23 to log 512k=219.
          19bit required.
       For 512k *4 bit DRAM
 Method 1
     213-4 =29 = 512 rows (pages)
      210 =1024 column (page size)
 Method 2
      2 11 = 2048 rows (pages)
       2 8 = 256 columns (page sizes )
       This method -2 drops to quarter of its original page size (1024 ).

6.8 . For the 64 Mb DRAM described in Example 6.1 , calculate the minimum time
     required to read out the contents of every addressable location in the memory (a ) if
     the addresses are generated in a random sequence and (b) if page mode is used .

Solution

8E1 DRAM = 64 Mb =8M *8 bit

                       = 213 * 210 *8 bit

                        = 8192*1024 *8 bit

            (a) The number of word stored in the 8E1 is 8M =223

            (b) The memory cycle time for random access is tm =90ns

      The time to read out every location           = 223 * 90ns

                                                       = 223*90*10-9 =0.7553

           (b)A fast page mode cycle time tm =30 ns
             One page read out tm           = 30ns * 1024 locations
                                             = 30720ns
                For all pages               =30720 ns *8192 pages
                                              = 0.254s

Problem

6.25 . A certain 1M* 16bit RAM has four-way address interleaving with four memory
      banks M0 , M1 , M2 and M3 . (a)Identify the bank to which each of the following
      hexencoded addresses is assigned : 01234 , AVCDE . 91272 , and FFFF . (b)If one
      of the memory bank is busy when a new read request arrives at the memory ,What
      is the probability that the request will be delayed due to memory contention?

Solution:

(a)used 4-way address interleaving
   s=4=22
      p = 2 bit
   The target bank is determined by the right most 2 bit of given binary address
Hex-address          binary – address                 corresponding bank
01234                0000 0001 0010 0100              M0
ABCDE                 1010 1011 1100 1110             M2
91272                1001 0001 0010 0111              M2
FFFFF                1111 1111 1111 1111              M3
(b) The probability of contention is one in four or 0.25 .

6.14    A moving arm disk . storage device has the following specification .
        Number of tracks per recording surface surface            200
        Disk – rotation speed                                   2400 rev / min
        Track storage capacity                                   62,5000 bits

       solution

       r = 2400 rev / min
         = 2400/60 rev / sec
       N = 62,500 bits
       TL = 1/2r
          = 1*60/2*2400
          = 0.01253 = 12.5ms
       Data transfer rate = r N
                         = (2400/60)*62500
                         = 2.5*106 bit / sec


6.15 . A certain magnetic hard disk drive has the following specifications in its data
sheet:
       Number of disks (recording surface )         14(27)
       Number of tracks per recording surface       4925
       Number of sectors on all recording surfaces 17,755,614
       storage capacity (formatted ) of disk drive   9.09 GB
       Disk – rotation speed                       rev / min
       Average seek time                           11.5 ms
       Internal data – transfer rate                44 to 65 MB / s
                                                               ( 10 Marks)
solution :

r = 5400 rev / min
ts = 11.5 ms
Block of sector size B = total capacity of the unit
                        total number of sector
                     = 9.09*109 B
                        17755614
                    = 511.95 ≈ 512 B

rotation speed r = 5400 rev / min
                 = 5400/60 rev/sec
               tL = 1/2r
                 = (1*60)/(2*5400) = 5.56 ms
average data transfer rate = (44*65)/2
                         = 55 MB/s
                         = 55 KB/ Ms

average data transfer time for , one block =( 512B) / (55000 B/ms)
                                         = 9.309*10-6
                                         = 0.009*10-3
                                        = 0.01ms

average block = average seek + average rotation + average data transfer
access time (tB) time (ts)      latency ( tL)    time for n/rN one block

               = (11.5+5.56+0.01) ms
               = 17.07 ms



Serical – access Memories
 Seek time (ts )

         In memories that share the read – write b , the need to move the heads between
tracks introduces a delay. The average time to move a head from one track to another is
seek time (ts) of the memory .



Ratational latency (tL)

      The average time for this movement to take place is the latency (tL) of the memory
. In memories where information rotates around a closed track tL is called rotational
latency (tL).

         tL = ½ r
         tB = ts + 1/2r + n/rN

No.6.23. A computer has a two – level vitual memory system . The main memory M1 and
         the secondary memory M2 have average access times of 10-6 and 10-3 s ,
         respectively . We know that the average access time for the memory hierarchy is
         10-4s , which is considered unacceptably high . Describe two ways in which this
         memory access time could be reduced from 10-4 to 10-5 s and discuss the hardware
         and software costs involved.
      tA1 = 10-6s
      tA2 = 10-3s
      tA = 10-4s to 10-5s
(i) Increasing the bit ratio (H)
       This may be ratio by improving the memory mapping algorithm. so , the costs thus
incurred are mainly software costs.
        It is often possible to improve H'
 by increasing main memory capacity , which increase hardware cost.
        tA = HtA1 + (1-H) tA2
        H = (tA1 - tA2)/ (tA1 – tA2) = (10-4 – 10-3)/ (10-6 – 10-3)
 To make tA = 10-5s .We must increase H to H'

   H'
= tA-tA2 / (tA1-tA2)

   H'
= (10-5 -10-3)/(10-6 – 10-3) = 0.991

     In order to decrease tA = 10-4 to 10-5 , we can obtain by increasing the hit ratio 0.901
to 0.991.

(ii)Decreasing tA2

tA2 = 10-5 , tA1 = 10-6 , H = 0.901
tA2 = (tA – HtA1)/(1-H) = (10-5 – 0.901*10-6) /(1-0.901) ≈ 10-4s

Thus it is necessary to decrease tA2 by a factor of about 10.

(iii) Decreasing tA1

tA = 10-5 ,H = 0.901 , tA2 = 10-3
tA = (tA –(1-H)tA2) / H
   = (10-5 – (1-0.901)*10-3) / 0.901
   = -0.988*10-4s

tA1 value is negative 80 it is impossible to get desired value of tA1

No (6.24) A two level memory (M1 ,M2) has the access times tA1 = 10-8 s and tA2 = 10-3 s
          What must the ratio H be in order for the access efficiency , to be at least 65
          percent of its maximum possible value?

tA1 = 10-8 , tA2 = 10-3s

e = tA1 / tA

In order to make e = 0.65 (65%)
tA = 10-8/0.65 = 1.53846 * 10-8s
tA = HtA1 + (1-H)tA2
H = (tA1-tA2) / (tA1-tA2)
H = 1.538946*10-8 – 10-3 = 0.9999946
we need H ≥0.9999946 in order to make e≥ 0.65

No (6.25) In an n- level memory, the hit ratio Hi associated with the memory Mi at level i
         may be defined as the probability that the information requested by the CPU has
         been assigned to Mi, . Assuming that all information assigned to Mi,also appears
         in Mi+1 , then H1<H2 < ---- < Hn=1 . Using this definition of Hi , generatize the
         expression for tA given in Equation (6.6) to on n-level memory hierarchy.
                                                                                (6 marks)

All information assigned to M i also appear in M i 1 , H 1 < H 2 < H 3 < ----< H N =1.

     The frequency of access to level Mi of the memory hierarchy is defined as the
probability that an item x represented by CPU is satisfied by accessing M i, Mi is the
highest level.
        Pi = H i – H i 1
Where            H 0 = 0 and H n =1
                   n
     tA=          
                  i 1
                         Pi t Ai
            n
       =  ( H i - H i 1 ) t Ai
           i 1

				
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