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Ch11The ABCs of ESD EOS and SOA

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					Bridging Theory in Practice
Transferring Technical Knowledge
to Practical Applications
The ABC’s of ESD,
  EOS, and SOA
The ABC’s of ESD, EOS, and SOA
 The ABC’s of ESD, EOS, and SOA
Intended Audience:
• Electrical engineers with a knowledge of simple electrical circuits
• An understanding of MOSFET devices


Topics Covered:
• What is Electrostatic Discharge (ESD)
• What is Electrical Over Stress (EOS)
• What is Safe Operating Area (SOA)


Expected Time:
• Approximately 90 minutes
The ABC’s of ESD, EOS, and SOA
• What is ESD
  – Where does ESD come from
  – MOSFET Gate susceptibility
  – Test Standards
  – Component level vs. module level tests

• What is EOS


• What is SOA
Electrostatic Discharge (ESD)
 • We are all familiar with a common form of electrostatic discharge (ESD):




                               Shaggy Carpet

 • ESD is the sudden transfer of electrostatic charge between objects at
   different electrostatic potentials
 Where Does ESD Come From
   • Triboelectric Charging
        – Mechanical Contact and Separation
        – “Walking on carpet”
 Direct Charging
   – Mobile Charge Transfer
   – ―Plugging in a cable‖ (e.g. USB to PC)


 Ionic Charging
   – Not properly balanced Air Ionizer can charge an object (instead of intended operation
   to neutralize/balance charge)

   –Charged object comes into contact with a grounded object (such as machine pick-up
   probe or grounded human operator)

   –This is example of charged device model (CDM) event—more to come!!!
  Where Does ESD Come From?

   • Which levels can occur?
       – Below 3-4kV you see, hear or feel nothing!
       – Just above 4kV, air-gap-sparks can occur
       – 1mm == 1kV (5mm spark ~ 5kV)
 Why does a 2kV protected device survive the real world?
   – You are charged relatively to earth, not to ―pin7‖

   – You do not have 4kV between your thumb and your index finger
Where Does ESD Come From?
                                                                     office room (winter) without

• Influence of Air Humidity
                                                      16




                                   ESD Voltage (kV)
                                                                        air humidity regulation
                                                      15


   – Higher relative air
                                                      14

                                                      13

     humidity does cause a                            12

                                                      11
     “moisture” film on                               10


     surfaces                                         9

                                                      8                               synthetic

   – Charge is more                                   7

                                                      6
     distributed, lower voltages                      5


     thus occur                                       4

                                                      3
                                                                                          wool


   – But dry air does not have                        2

                                                      1
                                                                                      anti-static

     a higher inherent                                     5   10     20
                                                                    15%
                                                                           30 40
                                                                             35%
                                                                                     50   60   70   80   90 100
                                                                                            % Relative Air Humidity
     “resistance”
MOSFET Gate Susceptibility
       Source                Gate                Drain
                Often, the
                source is           Insulating
                grounded            SiO2 Gate


SiO2


 n                                                         n



                                                         p-type
Charge Is Applied to the
MOSFET Gate
                         But, the
       Source     Gate               Drain
                         charge is
                         stuck on gate due
                         to insulating SiO2


SiO2
            Cgs

 n                                            n



                                          p-type
A Quick Review of
Voltage and Capacitance
                                             +12V   Ground
Voltage
• Think of voltage as an amount of             Battery
  possible electrical work
• A high voltage means additional
  electrical work is possible
• If the voltage is improperly directed or
  used, unintended        (and potentially
  harmful) work will be performed
  A Quick Review of
  Voltage and Capacitance
• Variables and Constants:
       C  Capacitance       0ox  Permittivity of Silicon Dioxide
       Q  Charge              A  Area of Capacitor Plates
       V  Voltage             d  Distance Between Conductors

• Two Basic Equations:

                         Q             ox A
                    C           C     0
                         V                d
• Rearranging yields:
                   Q    Q                 Qd
                 V                  
                   C 0ox A            0ox A
                                  d
Quick Review Summary:
                         Qd
                    V
                       0ox A


 0ox
•      is a constant for a given material (SiO2)
• As the charge (Q) on the capacitor increases -
      the voltage across the capacitor increases….
Gate Charge Induces a
Gate Voltage
       Source                  Gate                  Drain
                     QGATE d          VGATE  100V
           VGATE   
                     0ox A



SiO2               POP

 n                                                             n



                                                             p-type
Induced Gate Voltage
Creates a Hole in the SiO2
       Source       Gate               Drain




SiO2


 n                                               n

                  Allowable E-field
                within SiO2 exceeded
                                               p-type
Induced Gate Voltage Creates a
Hole in the SiO2
       Source                 Gate   MOSFET    Drain
                                      cannot
                Gate-Source          turn on
                   Short

SiO2


 n                                                       n



                                                       p-type
   Gate susceptibility summary:
                                      Qd
                                 V
                                    0ox A
• As the charge (Q) on the capacitor increases -
        the voltage across the capacitor increases….

• If the transistor decreases in size -
         the thickness of the SiO2 gate (d) decreases -
         but, the area (A) of the gate decreases faster -

• For the same amount of charge, the voltage across the capacitor is higher for a
  smaller transistor

• More advanced technologies may require additional ESD precautions
Induced Voltage for 3m and
1.2m CMOS Processes
• 3m Process (Minimum Size Transistor)
   –   tox   = 400 Å = 4x10-8 m
   –   L     = 3m
                             V
                                               1.16 x1011C  4.0 x108 m         1.5kV
   –   W     = 3m               3.9   8.85 x10 F / m  3.0 x10 m 3.0 x10 m 
                                                   12               6        6


   –   Q     = 1.16x10-11 C


• 1.2m Process (Minimum Size Transistor)
   –   tox   = 200 Å = 2x10-8 m
   –   L     = 1.2m        V
                                              1.16 x1011C  2.0 x108 m         4.7kV
   –   W     = 1.2m             3.9   8.85 x10 F / m 1.2 x10 m 1.2 x10 m 
                                                  12               6        6



   –   Q     = 1.16x10-11 C

                                                Note: 0OX  (3.9)(8.85x10-12 F/m)
 ESD Standards & Test: Overview
   • ESD Standards & Tests should simulate “real world” events as realistic as
     possible

   • There is no “single/one size fits all” ESD Test available 
     Different handling/mounting conditions have resulted in different ESD
     tests
       – e.g. car-manufacturers follow different ESD standards than component-
         suppliers: both are talking about ESD but not about the same applied ESD-
         standards

 Be careful to know complete standard definition
   – “ESD 2kV”, “2kV HBM”,… does not mean much: The Standard is
     missing
        e.g   JEDEC22-A114; MIL-STD-883, Method 3015.7, ……(more complete)
 ESD Standards & Tests: Overview
    • A “Standard” consists of …
        – … a used MODEL
          (HBM, MM, …)
   – … VALUES for the elements used in the model
     (R=1500 Ohm, C=100pF)
   – … plus TEST PROCEDURE: how to apply the standard
     (e.g. 3 pulses)


                        Standard = Model + Values + Procedure

 Therefore Standards can differ in each subset, in the
    – MODEL
    – VALUES
    – TEST PROCEDURE



 “HBM 2kV” is not specific – “2kV JEDEC22-A114” is better defined
ESD Models: Human Body Model
                                                                    R

 • Human Body Model (HBM) consists
   of a Capacitor and a series Resistor                           C

 • Values are defined in the specific
   standard                                                    Model

    – Commonly used: C =100pf, R=1500       HBM Standards
      Ohm (JEDEC, Mil, etc.)                (R=1500 Ohm, C=100 pF)
                                            • JEDEC JESD 22-A114 [2]
 • Test Procedure is defined in the         • Military Standard Mil.883 3015.7 [3]
                                            • ANSI/ESD STM5.1 [4]
   specific standard                        • IEC 61340-3-1
    – Commonly used: 1 to 3 pulses, both
      polarities, 3 devices/voltage level   “Human ESD Model”
                                            (R=2000 Ohm, C=150 pF – 330 pF)
                                            • ISO/TR 10605 [5]

                                            “Human Body Representative”
                                            (R=330 Ohm, C=150 pF)
     Commonly used for component tests      • IEC 61000-4-2 [6]
ESD Models: Human Body Model 
Waveform
• HBM Jedec22-A1114                               1kV
  Waveform:

  – 10ns rise time typically (short)
      • 2-10ns are allowed


  – Peak current:
      • Rule of Thumb:
          – 1kV = 2/3 Ampere


                Vesd
                                       VESD (V)   Ipeak - Ipeak+10%
       Ipeak 
              1500 [ W]                                   (A)
                                        1000        0.67 – 0.74
ESD Models: Machine Model
 • Machine Model (MM) consists of a
   Capacitor and no series Resistor
 • Values are defined in the specific                                   C
   standard
     – Commonly used: C =200pF,
 • Test Procedure is defined in the specific
   standard                                                     Model
     – Commonly used: 1 to 3 pulses, both
       polarities, 3 devices/level
                                               MM Standards
                                               (C=200 pf)
                                               • JEDEC JESD 22-A115 [11]
                                               • ANSI/ESD STM5.2
Some definitions use MM
―standard‖ with a 25 Ohm series                “Philips Standard”
resistor, which at least doubles               (C=200 pF, R=10-25 Ohm, L=0.75-2.5µH)
the achievable ESD Level!                      • Standard??
ESD Models: Machine Model
 • MM stress is similar to
   HBM
    – Oscillations due to setup
      parasitics


 • MM and HBM failure
   modes are similar
                                  Source: T. Brodbeck; Models.pdf


 • Less reproducible than           VESD (kV)               Ipeak - Ipeak+30%
   HBM                                                              (A)
                                         0.1                   1.5 - 2.0
                                         0.2                   2.8 - 3.8
Charged Device Model Test
• Models an ESD event which occurs when a device acquires
  electrostatic charge and then touches a grounded object
                                Device
                              discharges         Device placed
                        through ground probe      in dead-bug
                                                    position


                                                 Dielectric


                                                 Field Plate
           High Voltage Source
CDM Waveform: Highly dependent on
die size and package capacitance




 500V with 4pF verification module
 tr<400psec / Ip1~4.5A / Ip2<0.5Ip1 / Ip3<0.25Ip1
 Source: AEC-Q100-011B
 AEC-Q100
• Automotive Electronic Council (AEC) Stress
  Test Qualification “100”: AEC Q100 – xxx
       AEC is not a single standard but a collection of requirements for automotive suppliers


 AEC Q100 validated suppliers have to fulfill the ESD regarding
  qualification described in it
    – AEC Q100-002: HBM (JEDEC) 2000V OR AEC Q100-003: MM
      (JEDEC) 200V
    AND
    – AEC Q100-011: CDM (JEDEC)
           Corner Pins 750V   / Non-corner pins 500V
  Component vs. Module level tests

    • ESD (pulses) testing originates from a subset of the wide field of EMC
      (Electromagnetic Compatibility, EMI … Immunity)
    • Due to the importance in the Semiconductor Industry, ESD testing has
      evolved into its own field of specialization

 The ESD/EMC world in general can be divided into two main-
  fields:
                      (Powered) Systems             (Unpowered) Components
 ESD Standards & Tests:
 System vs. Component
Goal: UNDISTURBED functionality                Goal: UNDESTROYED
during and after ESD stress                    components after ESD stress:
under powered / functional                     All specification-parameters
conditions                                     should stay within its limits


ESD is a part of EMC qualification             ESD is a part of product qualification
Different ―behavior criteria‖ in response to   ―Pass‖/‖fail‖ criteria
ESD on system level exists (class A to D)


 Just dedicated pin combinations               All pin combinations can occur
  feasible                                       and are tested
   I/O vs. GND
                                                Relative measure of robustness
 The reference/enemy is always earth            during handling/manufacturing
  potential
 Relative measure of robustness of
  end product during operation
ESD Test methods (Models)
System     vs.     Component
Module/System Level        Component Level
  Human Body Model        Human Body Model (HBM)
          (HBM)               100pF / 1500 W
     150pF / 330 W          JEDEC-Norm JESD22-A114-B
                            (MIL-STD883D, method 3015)
     EN 61000-4-2
 (so called ―GUN Test‖)


 Human Body Model (HBM)      Machine Model (MM)
     150pF / 2000 W             200pF / 0 W
       ISO 10605            JEDEC-Norm JESD22-A115-A
                                (correlates to HBM)



 Human Body Model (HBM)   Charged Device Model (CDM)
     330pF / 2000 W               Package pF / 0 W
        ISO 10605              JEDEC-Norm JESD22-C101-A
ESD Models: Human Body Model 
Component Test
• A “Pin-to-Pin” ESD Tester            R   Terminal A

  (like HBM, MM Testers)
  consists of the HV source and   HV   C
  the model with its values,
  connected to two “Terminals”
                                           Terminal B

• The Terminals are not changed
  for polarity reversal …
   The capacitance is charged
  one time positively and one
  time negatively
   Tester-Ground along with
  parasitics stay constant
  ESD Models: Human Body Model 
  Component Test
• 2 different Pin-Combination-Types are tested
    – Supply-Pin-Tests
        • All Pins (individually one at a time) at Terminal A vs. Supply-X at
          Terminal B
        • Repeat for Supply-Y, Supply-Z, etc. at Terminal B
    – Non-Supply-Pin-Test
        • “All Non-Supplies (individually one at a time) at Terminal A vs. all
          other non-supplies together at Terminal B”
        • Repeat for each non-supply at Terminal A

• 1 positive and 1 negative pulse for each pin-combination

• Step-Stress, 500V, 1kV, 2kV and 4kV should be used; different
  levels and steps can be defined
   – A new set of 3 devices per level is used
                                                         ESD Product Qualification Test @ IFX according to
                                                         JEDEC EIA/JESD 22-A114-B [2] described in IFX
                                                         Procedure [1]
  ESD Supply-Pin Test: HBM ESD Each pin
  vs. Supply-1 (GND)
• ESD Test P1.1
   – All pins vs. Supply 1 (in this
     case GND)

    – In this case:
        • 10 different
          combinations
        • 1+ and 1- pulse for each
          combination
        •  20 pulses for each
          voltage step
ESD Supply-Pin Test: HBM ESD Each pin
vs. Supply-2 (VBB)
• ESD Test P1.2
   – All pins vs. Supply 2 (in
     this case VBB)
   – Then subsequently All
     pins vs. Supply 3 (Vdd)

   – In this case:
      • 11 different
        combinations
      • 1+ and 1- pulse for each
        combination
      •  22 pulses for each
        voltage step
  ESD Non-Supply-Pin Test: HBM ESD Each non-
  supply vs all other non-supply

• ESD Test P2
  – Each non-supply vs. All
    other non-supply
  – One non-supply at a
    time on Terminal A
  – All other non-supplies
    at Terminal B
  – In this case:
     • 8 different combinations
     • 1+ and 1- pulse for each
       combination
     •  16 pulses for each
       voltage step
ESD Standards & Test:
System-Level Test
• Direct Discharge: Test points
  of normal accessibility.
   – The Reference-’”Pin” at
     System-Level test is “Earth”
     and not a part of the DUT


• Indirect Discharge into
  couple plate: Test for
  radiated disturbance
  immunity
HBM: System Level Tests applied to
components??
• Some Customers ask for system-
  level test at component level
   – Component is not powered
   – Only pins which are accessible to the
     outside world are tested                  7.5A
   – Reference pin(s) are the component                    ESD @ 2kV
     ground pin(s)                                         Red: IEC (―GUN‖)
   – Pass/Fail according to Component                      Blue: JEDEC ―HBM‖
     test-program
   – ESD current is 5x higher at a dedicated
     voltage level compared to component
     ESD tests
                                                1.3A



                                                      1ns 10ns
  Pulse Charge Comparison
                                        Discharge generated Pulses (RC)
                                                                                                          Charge
                                              Duratio                                                   relatively
                                                n                                 C                      to HBM,
                                     Vma       (10-                       Ri     [pF   Ipeak             JESD22-
 Application     Standard/Pulse      x [V]     90%)      # of Pulses    [Ohm]     ]     [A]    Charge      114
Component      "HBM" JESD 22-114     8000      150ns               1      1500   100     5.3   800nC             1
               "GUN" IEC 61000-4-
System         2                     8000      120ns              10      330    150      33    1.2µC          1.5
System/Vehic
le             ISO/TR 10605 inside   8000         1µs              3      2000   330      30   2.64µC          3.3
System/Vehic   ISO/TR 10605
le             outside               8000      360ns               3      2000   150      30    1.2µC          1.5
                                             Voltage generated Pulses
Vehicle        ISO 7637: 1           -100        2ms           5000        10     -       10    20mC     25x10^3
                                                                                                        6.25x10^-
Vehicle        ISO 7637: 2            100        50µs          5000        10     -       10    0.5nC           4
                                                                  1h
Vehicle        ISO 7637: 3a           150      100ns      (3.6x10^6)       50     -        3   300nC        0.375
                                                                  1h
Vehicle        ISO 7637: 3b           150      100ns      (3.6x10^6)       50 HBM
                                                                            •   -      8kV 2 normalized 0.25
                                                                                           is 200nC     to ―1‖
HBM ESD
Gate Shorted to Source




Very small damage area due to low energy of ESD pulses, normally cannot be seen
with ―naked eye‖
 HBM ESD
 Gate Shorted to Source
    This device had a G-S short and you can see the burn
    mark is right at the boundary region of gate poly and source
    metal which is common since this is the area of highest
    E field strength




Gate contact metal   Gate Polysilicon      Source contact metal
Can ESD Sensitive Devices in an
Automobile Be Protected?
• Electrostatic discharge sensitive components
  can be protected in an automobile

• Installation of spark gap topologies

• Establishing a predictable charge well
  topology such as capacitors
Decrease ESD Sensitivity with a
Predictable Charge Well Topology
• Recall our earlier equation:
                         Qd
                    V
                       0ox A


• Place a capacitor across the device/pin to be
  protected

• The additional external capacitor sheds the
  electrostatic discharge energy, reducing the voltage
  at the pins of the semiconductor device
Decrease ESD Sensitivity with a
Predictable Charge Well Topology
  ESD generator                                               IC
                                                       Protected
                                                       Pin



                                   Cprotection

       ESD current/charge



For most robust design, the voltage at this point should be lowered to be less than
internal ESD structure breakdown voltage so all current/energy is shed thru external
capacitor. Please note that there is no resistor between C_prot and IC so high
current/energy can flow into IC if internal ESD structure breaks down and begins to
conduct current
Decrease ESD Sensitivity with a
Predictable Charge Well Topology
 • System level/gun tests ESD voltages may need to be 15,000V
   (direct contact)
    – Gun tests uses 330pf for source capacitor


 • For automotive technologies having ESD structures with 40-
   45V breakdown is common
 C_prot = (C_gun / Vbr_ESD) * V_gun
       = (330pF / 45V) * 15kV
        = 110nF
Typical internal IC
ESD Protection Circuits
Ground Referenced Protection          VSupply Referenced Protection
                      IC                                       VSupply
  Protected Circuit




                           External
                                Pin



                                      Protected Circuit




                                                                         External Pin
                                                          IC
ESD Summary
• Electrostatic discharge occurs when excessive static charge on
  an object builds up to a very high voltage (thousands of volts)
  and causes device damage during contact and subsequent
  discharge (current flow) with another object
• MOS devices with insulating SiO2 gates are especially
  susceptible to ESD damage
• Different test standards have evolved for component level and
  system level tests and confusion can result if these standards
  are not understood and clarified in reports and
  communication
• The very fast (HBM=nsecs / CDM=psecs) ESD pulses have low
  energy and result in VERY small physical damage signatures
 The ABC’s of ESD,
 EOS, and SOA
• What is ESD
  – Where does ESD come from
  – MOSFET Gate susceptibility
  – Test Standards
  – Component level vs. module level tests

• What is EOS


• What is SOA
   What is Electrical Over
   Stress (EOS)?
• Electrical Over Stress is exactly what it says….

   A device is electrically stressed over it’s specified limits in terms of voltage, current,
   and/or power/energy

• Unlike ESD events, EOS is the result of "long" duration stress events (millisecond
  duration or longer)
   – Excessive energy from turning off inductive loads
   – Load Dump
   – Extended operation at junction temperatures > 150degC
   – Repetitive excessive thermal cycling
   – Excessive/extended EMC exposure, etc.
• EOS often results in large scorch marks, discoloration of metal, melted metallization
  and/or bond wires, and massive destruction of the semiconductor component
What is Electrical Over
Stress (EOS)?
• Failures from EOS can result in the following:

   – Hard failure: failure is immediate and results in a complete
     non-operational device

   – Soft failure: EOS results in a marginal failure or a shift in
     parametric performance of the device

   – Latent failure: At first the EOS results in a non-catastrophic
     damage but after a period of time further degradation
     occurs resulting in a hard or soft failure
EOS: Thermal Lifetime Curve
Lifetime                            Point of accelerated
                                    device qualification
10 000 h
                                                            Lifetime curve for device
                                                            worst case parameters
 1 000 h

  100 h
                                                                                 270°C
   10 h
                                                                                              app. 350°C
                            170°C
     1h                                                                                       Irreversible damage
                       Over-
                                                       220°C        260°C
                       temperature
   0.1 h                                                   Soldering
                       shutdown
                                                                                                  Device temperature


           Ⅰ        150°C           Ⅱ       200°C                 Ⅲ         270°C         350°C            Ⅳ
   Spec valid,         Spec restricted,      No spec, no permanent damage,               Device destruction,
   full lifetime,      reduced lifetime,     highly reduced lifetime,                    irreversible damage,
   full function       limited functionality no function guaranteed                      permanent out of control
 What is Electrical Over
 Stress (EOS)?
• What indicates EOS?



                                 Degradation/recrystalisation of metal (≥400ºC)
                                 ---also repetitive fast transients<100ºC



Scorched/Melted metal (≥650ºC)




           Melted silicon (≥1200ºC)
 EOS Failure Signatures---Generalities
Visualization of single- and repetitive pulse events
  : max. Chip temperature

           single mode

                                                         melting point in
                                                         thermal hot spot


                                                          repetitive mode




                                                                   number of cycles

        1         (e.g.)102                                           106
   This isn‗t a completely black & white effect, but there can be a significant
   difference in single- and repetitive pulse failure signatures
  EOS: Failure signature from excessive
  inductive turn-off energy
• Example – Inductive clamp single pulse
  IDS(start)=10A, t=11.8 ms, T=25°C, Vbb = 12V
I_ramp(10A/11.8ms)   E=2.14 Joules

                                                     Failure signature (10A):
                                                     - No metal degradation
                                                     - Scorch in DMOS field
                                                     - NO bond fuse
    EOS at the
    „hot spot“                No metal degradation
                              near bond
EOS: Failure signature from repetitive
thermal cycling combined with high current
                               Severely degraded
                               recrystalized metal
  Electrical Over Stress (EOS)
• A common failure for electrical over stresses is
  MELTED METALLIZATION AND/OR BOND WIRES
 Gold Wire DC Ratings*                     Aluminum Wire DC Ratings*
                                                                         350m
         50m
                                                                          40A
         2.5A




    25m
     1A                                50m                           125m
                                        2A                              8A
*Assumes TJ < 150C, TLeads < 85C, TWire < 220C, and Wire Length<3mm
  How to Electrically Over Stress
  Components
• Put components in/out of sockets while power already applied (hot
  plug)
• Applying electrical signals which exceeds a component’s ratings
• Apply an input signal to a device before applying supply voltage
  and/or ground
• Apply an input signal to a device output
• Use an inexpensive power supply (supply overshoot)
• Provide insufficient noise filtering on the board’s input line(s)
• Use a poor ground with high resistance and inductance
EOS Summary
• Electrical over stress refers to a condition when a
  device is electrically stressed over its specified limits

• EOS often catastrophically damages devices by
  degrading or melting of metallization and bond wires

• Operation of devices within the specified Safe
  Operating Area will eliminate electrical over stress
  damage
  The ABC’s of ESD,
  EOS, and SOA
• What is ESD
  – Where does ESD come from
  – MOSFET Gate susceptibility
  – Test Standards
  – Component level vs. module level tests

• What is EOS


• What is SOA
Safe Operating Area (SOA)
• The safe operating area is a set of conditions
  specified for a certain device

• Within the safe operating area, the
  semiconductor component is specified to
  operate as expected

• By definition, no electrical over stress occurs
  within the specified safe operating area
 SOA Graph for MOS Transistor
• Single pulse, Tcase = 25C, Tjunction < 125C
                         100A                                   4s

                                                                15s
     ID, Drain Current




                                                                        Pulse Width
                         10A                                    50s

                                                                200s

                         1A                                    1ms


                                                                DC
                         0.1A
                                1V      10V      100V        1000V
                                 VDS, Drain-Source Voltage
       SOA Graph for
       Linear Voltage Regulator
• VOUT = 5V, Tjunction < 150C                                        Soldered to board
                       150mA                                         with 3cm2 copper
                                                                          heatsink
IOUT, Output Current




                       100mA
                                                         Ta = 25C


                       50mA                              Ta = 85C

                                                         Ta = 125C

                        0A
                             10V      15V      20V      25V
                                   VIN, Input Voltage
The ABC’s of ESD,
EOS, and SOA
Thank you!
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