RD1020 - DDR SDRAM Controller

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RD1020 - DDR SDRAM Controller Powered By Docstoc
					                                                                     DDR SDRAM Controller
April 2004                                                                                  Reference Design RD1020

Introduction
The DDR SDRAM uses double data rate architecture to achieve high-speed data transfers. DDR SDRAM (referred
to as DDR) transfers data on both the rising and falling edge of the clock. This reference design provides an imple-
mentation of the DDR memory controller implemented in a Lattice ORCA® Series 4 FPGA device. This DDR con-
troller is typically implemented in a system between the DDR and the bus master. Figure 1 shows the relationship
of the controller between the bus master and the DDR. The bus master could be either a microprocessor like the
Intel i960 or a user’s proprietary module interface.

For illustration purposes, the Micron DDR SDRAM MT46V16M8 (4Meg x 8 x 4 banks) is chosen for this design.
This design has been verified using Micron’s simulation model. It is highly recommended to download the simula-
tion model from the DDR vendor for timing simulation.

Figure 1. SDR SDRAM Controller System
                                      System                       DDR System
                                     Interface                      Interface

                                                                      ddr_clk
                                                                     ddr_clkn
                                     sys_add                         ddr_rasn
                                     sys_adsn                        ddr_casn
                                                                     ddr_wen
                                     sys_r_wn
                                                                     ddr_cke
                                       sysd                           ddr_add
                                                    DDR SDRAM
                  BUS MASTER         sys_rdyn                                           DDR SDRAM
                                                   CONTROLLER         ddr_ba
                                    sys_dmsel
                                                                      ddr_dq
                                   sys_init_done
                                                                     ddr_dqm
                                   sys_dly_200us
                                                                      ddr_dqs
                                                                      ddr_csn



Features
     • Simplifies DDR command interface to standard system read/write interface.
     • Internal state machine built for DDR power-on initialization and auto refresh.
     • Read/Write cycle access time optimized automatically according to DDR timing spec and the mode it is
       configured to.
     • Auto refresh is done automatically without bus master intervention.
     • Easily configurable to support different CAS latency and burst length, by changing the parameters.
     • Supports ORCA Series 4 devices.




www.latticesemi.com                                      1                                                rd1020_01
Lattice Semiconductor                                                                     DDR SDRAM Controller

Pin Descriptions
           Pin Name               Type      Active                               Pin Description
System Interface Signals
clk                                 In        NA     System interface clock.
reset_n                             In       Low     This active low signal resets the controller to the initial state.
sys_adsn                                             Active low system interface address strobe. This pin indicates the
                                    In       Low
                                                     start of a bus master cycle.
sys_add[RA_MSB:CA_LSB]              In        NA     System interface address bus.
sys_r_wn                                             System interface read/write signal. High indicates a read cycle and
                                                     low indicates a write cycle. When this pin is high, it indicates to the
                                    In        NA
                                                     controller that the bus master is performing a read cycle. When low,
                                                     it indicates that it’s a write cycle.
sysd[DSIZE-1:0]                   In/Out      NA     Bi-directional system interface data bus.
sys_rdyn                                             Active low ready signal (for both read/write cycles). Indicates that
                                   Out       Low     data on sysd bus is valid when asserted low. System samples this
                                                     pin on rising edge of clk and if asserted low makes a data transfer.
sys_init_done                                        This active high signal indicates that the DDR SDRAM initialization
                                   Out       High    is completed. Until this signal is asserted no READ/WRITE to be
                                                     performed.
sys_dly_200us                                        This active high signal indicates to the controller that the DDR
                                    In       High    SDRAM has gone through the 200µs delay for power and clock sta-
                                                     bilization.
DDR SDRAM Controller
ddr_clk                            Out        NA     DDR SDRAM clock
ddr_clkn                           Out        NA     DDR SDRAM negated clock
ddr_cke                            Out       High    DDR SDRAM clock enable
ddr_csn                            Out       Low     DDR SDRAM command inputs CS#
ddr_dq[DSIZE/2-1:0]               In/Out      NA     DDR SDRAM data bus
ddr_dqs[DSIZE/16-1:0]              Out        NA     DDR SDRAM data strobe bus
ddr_add[DDR_A_WIDTH-1:0]           Out        NA     DDR SDRAM address bus
ddr_ba[DDR_BA_WIDTH-1:0]           Out        NA     DDR SDRAM bank address
ddr_rasn                           Out       Low     DDR SDRAM command inputs RAS#
ddr_casn                           Out       Low     DDR SDRAM command inputs CAS#
ddr_wen                            Out       Low     DDR SDRAM command inputs WE#
ddr_dqm[DSIZE/16-1:0]              Out       High    DDR SDRAM data bus mask When high, masks write data.


Functional Description
The functional block diagram of the DDR controller is shown in Figure 2. It consists of three modules, the main con-
trol module, the signal generation module and the data path module. The main control module has two state
machines and a refresh counter, which generates proper istate and cstate outputs according to the system
interface control signals. The signal generation module generates the address and command signals required for
DDR based on istate and cstate. The data path module performs the data latching and dispatching of the data
between the bus master and DDR.




                                                         2
Lattice Semiconductor                                                           DDR SDRAM Controller

Figure 2. Block Diagram


                           ddr_ctrl.v

                                                                                            ddr_csn
  sys_dly_200us              INIT_FSM             istate                                    ddr_cke


                                                                                            ddr_rasn
                                                                                            ddr_casn
                           Clock
                          Counter                               ddr_sig.v                   ddr_wen

   sys_init_done
                                                                                            ddr_add
                                                  cstate                                    ddr_ba

        sys_add                                    addr
       sys_adsn              CMD_FSM
       sys_r_wn


                                                                              dqout
                               latch_ref_req          wren
                                                                              dqout_en      ddr_dq
                          Refresh Req             cstate
                             LFSR                                             dqin
                            Counter


       sys_rdyn                                                 ddr_data.v    dqsout
                                                                                            ddr_dqs
                                               sys_dataout

                                                                              dqsout_en
           sysd                                sys_dataout_en

                                               sys_datain                    dqm_out
                                                                                            ddr_dqm

     sys_dmsel



                                                     clk
             clk                    HPPLL
                                                     clk2x



                                                                                            ddr_clk
                                    PPLL
                                                                                            ddr_clkn




                                                            3
Lattice Semiconductor                                                               DDR SDRAM Controller

PLL
HPPLL (range 60-420MHz) is required for generation clk (133MHz) and clk2x (266MHz). PPLL is required for gen-
erating ddr_clk and ddr_clkn. The reason for PPLL is to control the read data path delay. ddr_clk delay can
be varied by varying feedback delay (FB_PDEL).

DDR Initialization
Before normal memory accesses can be performed, DDR needs to be initialized by a sequence of commands. The
INIT_FSM state machine handles this initialization. Figure 3 shows the state diagram of the INIT_FSM state
machine. During reset, the INIT_FSM is forced to the i_IDLE state. After reset, the sys_dly_200US signal will
be sampled to determine if the 200µs power/clock stabilization delay is completed. After the power/clock stabiliza-
tion is complete, the DDR initialization sequence will begin and the INIT_FSM will switch from i_IDLE to i_NOP
state and in the next clock to I_PRE. The initialization starts with the PRECHARGE ALL command. Next a LOAD
MODE REGISTER command will be applied for the Extended mode register to enable the DLL inside DDR, fol-
lowed by another LOAD MODE REGISTER command to the mode register to reset the DLL. Then a PRECHAGE
command will be applied to make all banks in the device to idle state. Then two, AUTO REFRESH commands, and
then the LOAD MODE REGISTER command to configure DDR to a specific mode of operation. After issuing the
LOAD MODE REGISTER command and the tMRD timing delay is satisfied, INIT_FSM goes to i_ready state and
remains there for the normal memory access cycles unless reset_n is asserted. Also, signal sys_init_done is
set to high to indicate the DDR initialization is completed. The i_PRE, i_AR1, i_AR2, i_EMRS and i_MRS states
are used for issuing DDR commands.

The LOAD MODE REGISTER command configures the DDR by loading data into the mode register through the
address bus. The data present on the address bus (ddr_add) during the LOAD MODE REGISTER command is
loaded to the mode register. The mode register contents specify the burst length, burst type, CAS latency, etc.
Refer to the DDR vendor’s data sheet for more detailed information about the mode register field definitions. A
PRECHARGE/AUTO PRECHARGE command moves all banks to idle state. As long as all banks of the DDR are in
idle state, mode register can be reloaded with different value thereby changing the mode of operation. However, in
most applications the mode register value will not be changed after initialization. This design assumes the mode
register stays the same after initialization. However, the user can change parameters like cas_latency, burst length
etc. in the ddr_par.v file as necessary, without changing any code in the Verilog files.




                                                         4
Lattice Semiconductor                                                                                                                                                                                 DDR SDRAM Controller

Figure 3. INIT_FSM State Diagram
   load_mrs_done = 1'b0
                                                                   _____________
   load_mrs_af = 1'b0     i_IDLE                                   sys_dly_200us




                              sys_dly_200us==1
                                                                                         NUM_CLK_tRP==0 &
                                                                                         load_mrs_done                                        endOf_tRP_i & load_mrs_done


                                                                                                                                                                                                  NUM_CLK_tRFC != 0
                                                                                                                                                            __________
                                                                                             NUM_CLK_tRP !=0                                                endOf_tRP_i                                                                    _____________
                          i_NOP                                          i_PRE                                                       i_tRP                                      i_AR1                                         i_tRFC1      endOf_tRFC_i

                                                                                                                                 i
                                                                                                                               P_
                                                                                                                          tR
                                                                   NUM_CLK_tRP==0 &




                                                                                                                                                                                NUM_CLK_tRFC==0
                                                                                                                     f_
                                                                                                                dO                                                                                                       _i
                                                                                                           en
                                                                   !load_mrs_done




                                                                                                                                                                                                                    FC




                                                                                                                en
                                                                                                                                                                                                               tR
                                                                                                                                                                                                            f_




                                                                                                                  dO & rs_ rs_
                                                                                                                                                                                                           O

                                                                                                                   lo !lo


                                                                                                                    f_
                                                                                                                                                                                                         nd

                                                                                                                     ad a
                                                                                                                      &




                                                                                                                       tM
                                                                                                                                                                                                        e


                                                                                                                        _m d_


                                                                                                                         R
                                                                                                                          D
                                                                                                                            _i
                                                                                                                               do a
                                                                                                                               m

                                                                                                                                 ne f
                                                 NUM_CLK_tMRD==0




                                                                                                                                                                                                                               i_tRFC2
                                                 & !load_mrs_af




                                                                                             NUM_CLK_tMRD !=0                                               ____________                                                                   ___________
                                                                     i_EMRS                                                          i_tMRD                 endOf_tMRD_i        i_AR2                                          (load_m     endOf_tRFC_i
                                                                                                                                                                                                                              rs_af = 1)
                                                                       NUM_CLK_tMRD==0




                                                                                                                                                                                                  NUM_CLK_tRFC != 0
                                                                                                              &
                                                                                                           _i
                                                                                                                                        NUM_CLK_tMRD==0

                                                                                                          D ne
                                                                                                                                        & load_mrs_done &

                                                                                                         R do
                                                                                                       tM s _
                                                                                                     f_ r
                                                                                                  dO _ m
                                                                                                en oad
                                                                                                                                        load_mrs_af



                                                                                                  !l


                                                                             i_MRS
                                                                            (load_m               NUM_CLK_tMRD !=0
                                                                            rs_done                                                                         NUM_CLK_tRFC == 0
                                                                               = 1)




                                                                                            NUM_CLK_tMRD !=0
                                                                                            & load_mrs_af
                                                                                                                                     i_ready




As mentioned above, certain timing delays (like tRP, tRFC, tMRD) need to be satisfied before another non-NOP com-
mand can be issued. These DDR delays vary from speed grade to speed grade and sometimes from vendor to
vendor. To accommodate this without sacrificing performance, the designer needs to modify the ddr_par.v file for
the specific delays and clock period (tCK). According to these timing values, the number of clocks, the state
machine will stay at i_tRP, i_tRFC1, i_tRFC2, i_tMRD states will be determined. In the case when tCK is larger
than the timing delay, the state machine doesn’t need to switch to the timing delay states and can go directly to the
command states. The dashed lines in Figure 3 show the possible state switching paths.

Read/Write Cycle
Figure 4 shows the state diagram of CMD_FSM, which handles read, write and refresh of the DDR. The CMD_FSM
state machine is initialized to c_idle during reset. After reset, CMD_FSM stays in c_idle as long as
sys_init_done is low which indicates the DDR initialization sequence is not yet completed. From this state, a
READA/WRITEA/REFRESH cycle starts depending on sys_adsn/rd_wr_req_during_ref_req and
latch_ref_req signals as shown in the state diagram.




                                                                                                                                                 5
Lattice Semiconductor                                                                                                                                                              DDR SDRAM Controller

Figure 4. CMD_FSM State Diagram

                                                                                                                                                            c_AR
                                                                                                                                        0
                                                                                                                                   ==
                                                                                                                              FC
                                                                                                                             R




                                                                                                                                                               NUM_CLK_tRFC != 0
                                                                                                                         _t
                                                                                                                       LK
                                                                                                                    _C                   &
                                                                                                                U
                                                                                                                   M                   eq e
                                                                                                               N                     _r n
                                                                                                                                   ef _do
                                                                                                                                  r t
                                                                                                                                h_ i
                                                                                                                              tc in
                                                                                                                            la ys_
                                                                                                                                s




                                                                                                                                 endOf_tRFC                                                             __________
                                                                                    c_idle                                                                  c_tRFC                                      endOf_tRFC




                                                                                                                                              en
                                                            st




                                                                                                                                                dO
                                                          ur




                                                                                                                                                   f_
                                                         B
                                                       d_




                                                                                                                                                     tD
                                                                        (sys_init_done & !sys_adsn_r) ||




                                                                                                                                                       A
                                                     ea




                                                                                                                                                        L
                                                    R
                                                   f_
                                               dO




                                                                        rd_wr_req_during_ref_req
                                              en




     _________________   c_rdata                                                                                                                                                     c_tDAL                          __________
     endOf_Read_Burst                                                                                                                                                                                                endOf_tDAL
                          endOf_Cas_Latency




                                                                                                                                                                                    endOf_Write_Burst
                                                                                                                                                                                    wren = 1'b0

                                                                            c_active                                                                                                                                  _______________
     _________________       c_cl                                                                                                                                                   c_wdata                          endOf_Write_Burst
     endOf_Cas_Latency
                                                           r =0




                                                                                                                                            N
                                                                                                                                            U
                                                                                           NUM_CLK_tRCD != 0
                                                         n_ =




                                                                                                                                            M !s
                                                        w D




                                                                                                                                             _C ys
                                                                                                                                              &
                                                      r_ C




                                                                                                                                               LK _r
                                                    s_ _tR




                                                                                                                                                 _t _w
                                                  sy LK




                                                                                                                                                   R n_
                                                                                                                                                    C
                                                   _C




                                                                                                                                                      D r
                                                  M




                                                                                                                                                       ==
                                              U
                                                    &
                                              N




                                                                                                                                                          0




                                              endOf_tRCD & sys_r_wn_r                                                       endOf_tRCD & !sys_r_wn_r
                         c_reada                                                c_tRCD                                                                                              c_writea                wren = 1'b1




                                                                                                                    !endOf_tRCD



All rows are in the “closed” status after the DDR initialization. The rows need to be “opened” before they can be
accessed. However, only one row in the same bank can be opened at a time. Since there are four banks, there can
be at most four rows opened at the same time. If a row in one bank, is currently opened, it needs to be closed
before another row in the same bank can be opened. ACTIVE command is used to open the rows and PRE-
CHARGE (or the AUTO PRECHARGE hidden in the WRITE and READ commands as used in this design) is used
to close the rows. When issuing the commands for opening or closing the rows, both row address and bank
address need to be provided.




                                                                                                   6
Lattice Semiconductor                                                               DDR SDRAM Controller

In this design, the ACTIVE command will be issued for each read or write access to open the row. After a tRCD delay
is satisfied, READA or WRITEA commands will be issued with a high ddr_add[10] to enable the AUTO
REFRESH for closing the row after access. Therefore, the clocks required for read/write cycle are fixed and the
access can be random over the full address range.

Read or write is determined by the sys_r_wn status sampled at the rising edge of the clock before the tRCD delay
is satisfied. If a logic high is sampled, the state machine switches to c_READA. If a logic low is sampled, the state
machine switches to c_WRITEA.

For read cycles, the state machine switches from c_READA to c_cl for CAS latency, then switches to c_rdata for
transferring data from DDR to bus master. The burst length determines the number of clocks the state machine
stays in c_rdata state. After the data is transferred, it switches back to c_idle.

For write cycles, the state machine switches from c_WRITEA to c_wdata for transferring data from bus master to
DDR, then switches to c_tDAL. Similar to read, the number of clocks the state machine stays in c_wdata state is
determined by the burst length. The time delay tDAL is the sum of WRITE recovery time tWR and the AUTO PRE-
CHARGE timing delay tRP. After the clock rising edge of the last data in the burst sequence, no commands other
than NOP can be issued to DDR before tDAL is satisfied.

The dashed lines indicate possible state switching paths when the tCK period is larger than the timing delay specifi-
cation.

Refresh Cycle
DDR memory needs a periodic refresh to hold the data. This periodic refresh is done using AUTO REFRESH com-
mand. All banks must be idle before an AUTO REFRESH command is issued. In this design all banks will be in idle
state, as every read/write operation uses auto pre charge. A 128Mb DDR SDRAM requires an AUTO REFRESH
command every 15.625µs. At 133MHz, this results in 2078 clocks (15.625µs). LFSR counter is used to count for
2000 clocks and generates a refresh request to control state machine (CMD_FSM). CMD_FSM generates auto
refresh command and resets the refresh request. For 256Mb/512Mb/1Gb DDR devices, AUTO REFRESH com-
mand is required every 7.8125µs. At 133MHz this results to 1039 clocks. Hence according to the device and fre-
quency of operation select the appropriate values for REF_INTERVAL in ddr_par.v file. There are four pre-
defined values for REF_INTERVAL. They are REF_INT_128MBIT_100MHz (for 128Mb devices running at
100MHz), REF_INT_NON128MBIT_100MHZ (for 256Mb/512Mb/1Gb devices running at 100MHz),
REF_INT_128MBIT_133MHZ (for 128Mb parts running at 133MHz) and REF_INT_NON128MBIT_133MHZ (for
256Mb/512Mb/1Gb parts running at 133MHz).

Data Path
Figure 5 shows the data flow design between the DDR and the system interface. The module in this reference
design interfaces between the DDR with an 8-bit data bus, and the bus master with a 16-bit data bus. The user
should be able to modify this module to customize to fit the system bus requirements, by changing the DSIZE
parameter in the ddr_par.v file.




                                                         7
Lattice Semiconductor                                                                                                       DDR SDRAM Controller

Figure 5. Data Path Module

   READ DATA PATH
                                                                       SET         dqin_x_reg                                          SET       dqin_reg_h
                                                                  D          Q                                                     D         Q
                                                         clk                                                                 clk
             dqin         SET       dqin_2x_sync_reg
                      D         Q
            clk2x                                                      CLR
                                                                             Q                                                         CLR
                                                                                                                                             Q

                                                                       SET         dqin_xn_reg          SET        dqin_xnx_reg        SET       dqin_reg_l
                          CLR
                                Q                                 D          Q                    D           Q                    D         Q
                                                         clk                             clk                                 clk


                                                                       CLR
                                                                             Q                          CLR
                                                                                                              Q                        CLR
                                                                                                                                             Q

   WRITE DATA PATH



   sys_datain[15:8]       SET        datain_regl                             SET         dqout_reg                SET          dqout
                      D         Q                                        D          Q                         D         Q
              clk                                              clk2x                            clk2x
                                    sys_datain[7:0]

                          CLR
                                Q    select_lower_half
                                                                             CLR
                                                                                    Q                             CLR
                                                                                                                        Q


Timing Diagrams
Figure 6 and Figure 7 are the read cycle and write cycle timing diagrams of the reference design with the 2.5 CAS
latency cycles and the burst length of eight. The timing diagrams may be different due to the values of the timing
delays tMRD/tRP/tRFC/tRCD/tRCD/tWR, the clock period tCK, the CAS latency and the burst length. The total number of
clocks for read and writes cycles are decided by these factors.

The state variable c_State of CMD_FSM is also shown in these figures. Note that the ACTIVE, READ and WRITE
commands are asserted one and half clock after the c_ACTIVE, c_READA and c_WRITEA states respectively.

The values of the region filed with slashes in the system interface input signals of these figures are “don’t care”.




                                                                             8
Lattice Semiconductor                                                                                                                                                                DDR SDRAM Controller

Figure 6. Read Cycle Timing Diagram

               clk

             clk2x

         sys_adsn

          sys_add             24’h001400                                                                                                                                                                              24’h001500



         sys_r_wn

           c_state      c_IDLE             c_ACTIVE       c_tRCD             c_READA                            c_CL                                             c_rdata                                    c_IDLE                  c_ACTIVE



             wren

         sys_rdyn

    sys_dataout_en                                                                 16’hFFFF                                                                                             16’h0000                              16’hFFFF



             sysd                                                                                                                                                 D1, D0      D3, D2         D5, D4     D7, D6



     ddr_command                   NOP                    ACTIVE               NOP               READA                                                                              NOP



          ddr_add                 12’hFFF                 12’h001             12’hFFF            12’h400                                                                           12’hFFF



           ddr_ba                  2’b11                   2’b01               2’b11              2’b01                                                                            2’b11



         dqout_en                                                                                                                       8’hFF



        dqsout_en                                                                                                                        1’b1



          ddr_dqs

           ddr_dq                                                                                                                 D1     D0     D3    D2    D5   D4    D7   D6




Figure 7. Write Cycle Timing Diagram

              clk

            clk2x

        sys_adsn

         sys_add                 24'h001400                                                                                                                      24'h001500



        sys_r_wn

          c_state    c_IDLE                    c_ACTIVE    c_tRCD                       c_WRITEA                                 c_wdata                                                     c_tDAL                  c_IDLE        c_ACTIVE



             wren

         sys_rdyn

             sysd                                                                                          D1, D0       D3, D2         D5, D4         D7, D6



     ddr_command                   NOP                              ACTIVE               NOP                   WRITEA                                                                          NOP



          ddr_add                12'hFFF                            12'h001             12'hFFF                 12'h400                                                                       12'hFFF



           ddr_ba                 2'b11                              2'b01               2'b11                  2'b01                                                                          2'b11



         dqout_en                                         8'hFF                                                                                                                  8'h0                                                    8'hFF



       dqsout_en                                              1'b1                                                                                                               1'b0



          ddr_dqs

           ddr_dq                                                                                                          D1     D0      D3         D2    D5    D4    D7     D6




                                                                                                                9
Lattice Semiconductor                                                                 DDR SDRAM Controller

Implementation Results
The design software used for this implementation is Lattice ispLEVER® version 3.0 and the Synplicity Synplify syn-
thesis tool, version 7.1.

Device utilization and performance summary for OR4E02-2 is given below.

                                           Resource           Resource Used
                                               I/O                  80/410
                                              PFU                   50/624
                                              LUT4                   185
                                              REG                    249
                                              GSR                     1
                                             HPPLL                    1
                                              PPLL                    1

Performance:

                                   Clocks in the Design          Reported Frequency
                                       clk (pll_mclk)                146.649MHz
                                      clk2x (pll_nclk)               314.358MHz

Test bench:

The Verilog source code and test fixture for this DDR controller design is provided as part of this reference design

Figure 8. Test Bench
                                                           ddr_tb
                                                         ddr_top




                                                                 ddr_sig
                                                ddr_ctrl

                       STIMULUS                                                       DDR




                                                  PPLL           ddr_data

                                                 HPPLL




Source code:

     •   ddr_top.v                : Top level source code
     •   ddr_ctrl.v               : Main control module
     •   ddr_sig.v                : Signal generation module
     •   ddr_data.v               : Data path module
     •   ddr_par.v                : Parameter definition
     •   ddr_pll_orca.v           : HPPLL instantiation
     •   ddr_pll_orca_sp.v        : PPLL instantiation

                                                            10
Lattice Semiconductor                                                           DDR SDRAM Controller

Test bench:

     • ddr_tb.v                : Test bench top file
     • stimulus.v              : Generates stimulus to the design

Models:

     • mt46v16m8.v             : Micron DDR simulation model. Not included as part of this reference design.

Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
          +1-408-826-6002 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com




                                                    11

				
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Description: DDR = Double Data Rate Synchronous Dynamic Random Access Memory Double Data Rate. Strictly speaking, should be called DDR DDR SDRAM, it is commonly called DDR, which, SDRAM Synchronous Dynamic Random Access Memory is the acronym for synchronous dynamic random access memory. The DDR SDRAM is the abbreviation for Double Data Rate SDRAM is double data rate synchronous dynamic random access memory means. DDR SDRAM memory is developed on the basis of memory, and still in use SDRAM production system, so for the memory manufacturers, the only common SDRAM devices for manufacturing improved slightly, you can achieve the production of DDR memory, which can effectively reduce costs.