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					Application Specific Integrated
    Circuits: Introduction


              Jun-Dong Cho
          SungKyunKwan Univ.
         Dept. of ECE, Vada Lab.
           http://vada.skku.ac.kr
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Contents


   Why ASIC?
   Introduction to System On Chip Design
   Hardware and Software Co-design
   Low Power ASIC Designs




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Why ASIC - Design productivity grows!
  Complexity increase 40 % per year           Design
  productivity increase 15 % per year
                             Integration of PCB on single die




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Silicon in 2010
                                      Dens           s
                                           ity Acces Time
Die Area:   2.5x2.5 cm              (Gbits/cm2)    (ns )
Voltage:    0.6 V            DRAM       8.5         10
Technology: 0.07 m    DRAM (Logic)     2.5         10
                       SRAM (Cache)     0.3        1.5

                   Dens ity   Max. Ave. Power Clock Rate
                 (Mgates/cm2)    (W /cm2)       (GHz)
       Cus tom        25            54             3
       Std. Cell      10            27            1.5
      Gate Array      5             18             1
              k
   Single-Mas GA     2.5           12.5           0.7
        FPGA         0.4            4.5          0.25
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ASIC Principles
   Value-added ASIC for huge volume opportunities;
    standard parts for quick time to market applications
   Economics of Design
       Fast Prototyping, Low Volume
       Custom Design, Labor Intensive, High Volume
    CAD Tools Needed to Achieve the Design
    Strategies
       System-level design: Concept to VHDL/C
       Physical design VHDL/C to silicon, Timing closure (Monterey,
        Magma, Synopsys, Cadence, Avant!)
   Design Strategies: Hierarchy; Regularity; Modularity;
    Locality
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ASIC Design Strategies
   Design is a continuous tradeoff to achieve
    performance specs with adequate results in all the
    other parameters.
   Performance Specs - function, timing, speed, power
   Size of Die - manufacturing cost
   Time to Design - engineering cost and schedule
   Ease of Test Generation & Testability - engineering
    cost, manufacturing cost, schedule



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ASIC Flow




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Structured ASIC Designs
   Hierarchy: Subdivide the design into many levels of
    sub-modules
   Regularity: Subdivide to max number of similar sub-
    modules at each level
   Modularity: Define sub-modules unambiguously &
    well defined interfaces
   Locality: Max local connections, keeping critical
    paths within module boundaries




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ASIC Design Options
   Programmable Logic
   Programmable Interconnect
   Reprogrammable Gate Arrays
   Sea of Gates & Gate Array Design
   Standard Cell Design
   Full Custom Mask Design

   Symbolic Layout
   Process Migration - Retargeting Designs

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ASIC Design Methodologies

                        Custom       Cell-based   Prediffused     Prewired
 Density              Very High      High         High          Medium - Low
 Performance          Very High      High         High          Medium - Low
 Flexibility          Very High      High         Medium        Low
 Design time          Very Long      Short        Short         Very Short
 Manufacturing time   Medium         Medium       Short         Very Short
 Cost - low volume    Very High      High         High          Low
 Cost - high volume   Low            Low          Low           High




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 Why SOC?

• SOC specs are coming from ICT system engineers rather
 than RTL descriptions
•SOC will bridge the gap b/w s/w and their implementation
in novel, energy-efficient silicon architecture.
•In SOC design, chips are assembled at IP block level
(design reusable) and IP interfaces rather than gate level


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Common Fabric for IP Blocks
   Soft IP blocks are portable, but not as predictable as
    hard IP.
   Hard IP blocks are very predictable since a specific
    physical implementation can be characterized, but are
    hard to port since are often tied to a specific process.
   Common fabric is required for both portability and
    predictability.
   Wide availability: Cell Based Array, metal programmable
    architecture that provides the performance of a standard
    cell and is optimized for synthesis.

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Four main applications
   Set-top box: Mobile multimedia system, base station for
    the home local-area network.
   Digital PCTV: concurrent use of TV,3D graphics, and
    Internet services
   Set-top box LAN service: Wireless home-networks, multi-
    user wireless LAN
   Navigation system: steer and control traffic and/or
    goods-transportation



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PC-Multimedia Applications




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Types of System-on-a-Chip Designs




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Physical gap
   Timing closure problem: layout-driven logic and RT-level synthesis

   Energy efficiency requires locality of computation and storage:
    match for stream-based data processing of speech,images, and
    multimedia-system packets.

   Next generation SOC designers must bridge the architectural gap
    b/w system specification and energy-efficient IP-based architectures,
    while CAE vendors and IP providers will bridge the physical gap.




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Circular Y-Chart




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SOC Co-Design Challenges
   Current systems are complex and heterogenous Contain
    many different types of components
   Half of the chip can be filled with 200 low-power, RISC-
    like processors (ASIP) interconnected by field-
    programmable buses, embedded in 20Mbytes of
    distributed DRAM and flash memory, Another Half: ASIC
   Computational power will not result from multi-GHz
    clocking but from parallelism, with below 200 MHz.                           This will greatly
    simplify the design for correct timing, testability, and signal integrity.




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Bridging the architectural gap
   One-M gate reconfigurable, one-M gate hardwired logic.
   50GIPS for programmable components or 500 GIPS for
    dedicated hardwares
   Product reliability: design at a level far above the RT level,
    with reuse factors in excess of 100
   Trade-off: 100MOPs/watt (microprocessor)
    100GOPs/watt (hardwired) Reconf. Computing with a
    large number of computing nodes and a very restricted
    instruction set (Pleiades)


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Why Lower Power
   Portable systems                     Technology direction
      long battery life

      light weight
                                          Reduced voltage/power
                                          designs based on mature
      small form factor                  high performance IC
   IC priority list                      technology, high integration
      power dissipation
                                          to minimize size, cost,
                                          power, and speed
      cost

      performance




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Microprocessor Power Dissipation
        Power(W)
                                                     Alpha 21164            Alpha 21264
            50
            45                                                                P III 500
                                                                      P II 300
            40
            35
                                              Alpha21064 200
            30
            25
                                                                   P6 166
            20                                    P5 66
            15
                                                               P-PC604 133
            10                             i486 DX2 66     P-PC601 50
            5                i386 DX 16 i486 DX25            i486 DX4 100
                        i286
                                                    i486 DX 50         P-PC750 400

                 1980         1985          1990          1995          2000
                                                                       year
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Levels for Low Power Design
                             Hardware-software partitioning,
                System       Power down
          Algorithm       Complexity, Concurrency, Locality,
                             Regularity, Data representation
      Architecture     Parallelism, Pipelining, Signal correlations
                          Instruction set selection, Data rep.
   Circuit/Logic    Sizing, Logic Style, Logic Design
 Technology       Threshold Reduction, Scaling, Advanced packaging
                      SOI
 Possible Power Savings at Different Design Levels
                  Level of
                 Abstraction         Expected Saving
                  Algorithm          10 - 100 times
                 Architecture        10 - 90%
                 Logic Level         20 - 40%
                 Layout Level        10 - 30%
                 Device Level        10 - 30%

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Power-hungry Applications

   Signal Compression: HDTV Standard, ADPCM, Vector
    Quantization, H.263, 2-D motion estimation, MPEG-2
    storage management
   Digital Communications: Shaping Filters, Equalizers,
    Viterbi decoders, Reed-Solomon decoders




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New Computing Platforms
       P  kCFV 2

   SOC power efficiency more than 10GOPs/w
       Higher On Chip System Integration: COTS: 100W, SOAC:10W
        (inter-chip capacitive loads, I/O buffers)
       Speed & Performance: shorter interconnection,fewer
        drivers,faster devices,more efficient processing artchitectures
   Mixed signal systems
   Reuse of IP blocks
   Multiprocessor, configurable computing
   Domain-specific, combined memory-logic

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Low Power Design Flow I
                                                  Function
              System                           Partitioning and     System-Level
               Level                                                Power Analysis
                                              HW/SW Allocation
            Specification


                    Software                       Behavioral
                    Functions                      Description


                                                 Power-driven       Behavioral-Level
                   Processor                     Behavioral         Power Analysis
                   Selection                     Transformation



                                                  Power Conscious
                                                  Behavioral
                                                  Description


 Software-Level                                   High-Level         RT-Level
                            Software              Synthesis and
 Power Analysis             Optimization                            Power Analysis
                                                  Optimization

                                      To RT-Level Design



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Low Power Design Flow II
                                       RT-level
                                       Description
                          Data-path                        Controller

                                                     Logic Synthesis       Gate-Level
     RTL                  RTL                        and
                          mapping                                          Power Analysis
     Library                                         Optimization



                                                         Gate-level
                                                          Description



                                Standard cell          High-Level        Switch-Level
   Processor       Memory       Library                Synthesis and    Power Analysis
                                                       Optimization

  Control and
  Steering Logic   RTL
                   Macrocells                            Switch-level
                                                          Description


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Three Factors affecting Energy
–   Reducing waste by Hardware Simplification: redundant
    h/w extraction, Locality of reference,Demand-driven /
    Data-driven computation,Application-specific
    processing,Preservation of data correlations, Distributed
    processing
–   All in one Approach(SOC): I/O pin and buffer reduction
–   Voltage Reducible Hardwares
        2-D pipelining (systolic arrays)
      SIMD:Parallel Processing:useful for data w/ parallel
        structure
      VLIW: Approach- flexible




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 IBM’s PowerPC Lower Power
Architecture
   Optimum Supply Voltage through Hardware Parallel, Pipelining ,Parallel instruction
    execution
       603e executes five instruction in parallel (IU, FPU, BPU, LSU, SRU)
       FPU is pipelined so a multiply-add instruction can be issued every clock cycle
       Low power 3.3-volt design
   Use small complex instruction with smaller instruction length
       IBM’s PowerPC 603e is RISC
   Superscalar: CPI < 1
       603e issues as many as three instructions per cycle
   Low Power Management
       603e provides four software controllable power-saving modes.
   Copper Processor with SOI
   IBM’s Blue Logic ASIC :New design reduces of power by a factor of 10 times

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 Power-Down Techniques

                                             ◆ Lowering the
                                             voltage along with
                                             the clock actually
                                             alters the energy-
                                             per-operation of
                                             the microprocessor,
                                             reducing the
                                             energy
                                             required to
                                             perform a fixed
                                             amount of work
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Implementing Digital Systems




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H/W and S/W Co-design




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Three Co-Design Approaches
   IFIP International Conference FORTE/PSTV’98, Nov.’98 N.S. Voros et.al, “Hardware -software co-design of

    embedded systems using multiple formalisms for application development   ”
   ASIP co-design: starts with an application, builds a specific
    programmable processor and translates the application into software
    code. H/w and s/w partitioning includes the instruction set design.
   H/w s/w synchronous system co-design: s/w processor as a master
    controller, and a set of h/w accelerators as co-processors.
    Vulcan,Codes,Tosca,Cosyma
   H/w s/w for distributed systems: mapping of a set of communication
    processors onto a set of interconnected processors. Behavioral
    decomposition, process allocation and communication transformation.
    Coware(powerful),Siera (reuse),Ptolemy (DSP)
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Mixing H/W and S/W
   Argument: Mixed hardware/ software systems
     represent the best of both worlds.
     High performance, flexibility, design reuse, etc.

   Counterpoint: From a design standpoint, it is
     the worst of both worlds
      Simulation: Problems of verification, and test become harder

      Interface: Too many tools, too many interactions, too much

       heterogeneity
      Hardware/ software partitioning is “AI- complete”!




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Low power partitioning approach
     Different HW resources are invoked according to the
     instruction executed at a specific point in time
     During the execution of the add op., ALU and
     register are used, but Multiplier is in idle state.
     Non-active resources will still consume energy since
     the according circuit continue to switch
     Calculate wasting energy
     Adding application specific core and partial running
      Whenever one core performing, all the other cores
     are shut down

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ASIP Design
   Given a set of applications, determine micro architecture
    of ASIP (i. e., configuration of functional units in
    datapaths, instruction set)
   To accurately evaluate performance of processor on a
    given application need to compile the application
    program onto the processor datapath and simulate object
    code.
   The micro architecture of the processor is a design
    parameter!



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ASIP Design Flow




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Cross-Disciplinary nature

   Software for low power:loop transformation leads to
    much higher temporal and spatial locality of data.
   Code size becomes an important objective Software will
    eventually become a part of the chip
   Behavior-platform-compiler codesign: codesigned with
    C++ or JAVA, describing their h/w and s/w
    implementation.
   Multidisciplinary system thinking is required for future
    designs (e.g., Eindhoven Embedded Systems Institute http://www.eesi.tue.nl/english)


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VLSI Signal Processing Design
Methodology
   pipelining, parallel processing, retiming, folding,
    unfolding, look-ahead, relaxed look-ahead, and
    approximate filtering
   bit-serial, bit-parallel and digit-serial architectures, carry
    save architecture
   redundant and residue systems
   Viterbi decoder, motion compensation, 2D-filtering, and
    data transmission systems

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Low Power DSP
   DO-LOOP Dominant

                                 VSELP Vocoder : 83.4 %
                                 2D 8x8 DCT              : 98.3 %
                                 LPC computation : 98.0 %
          DO-LOOP Power Minimization
           ==> DSP Power Minimization

                           VSELP : Vector Sum Excited Linear Prediction
                           LPC : Linear Prediction Coding



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Deep-Submicron Design Flows
   Rapid evaluation of complex designs for area and
    performance
   Timing convergence via estimated routing parasitics
   In-place timing repair without resynthesis
   Shorter design intervals, minimum iterations
   Block-level design and place and route
   Localized changes without disturbance
   Integration of complex projects and design reuse



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SOC CAD Companies
   Avant! www.avanticorp.com                Synopsys www.synopsys.com
   Cadence www.cadence.com                  Topdown design solutions
   Duet Tech www.duettech.com                www.topdown.com
   Escalade www.escalade.com                Xynetix Design Systems
   Logic visions                             www.xynetix.com
    www.logicvision.com                      Zuken-Redac www.redac.co.uk
   Mentor Graphics
    www.mentor.com
   Palmchip www.palmchip.com
   Sonic www.sonicsinc.com
   Summit Design www.summit-
    design.com

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