3__AC_analysis_of_JFET by niusheng11


Experiment 3
AC analysis of JFET


            Revise the dc analysis of JFET circuits.

            To bias the JFET.

            To understand JFET AC model.

            To make JFET amplification.


Referring to figure (1), design a common source configuration that has an operating
point ( IDQ = 4mA, and Vout = 10V).

Theoretical background :

Bipolar junction transistors have low input impedance, small high frequency gain
and are non linear when |VCE| < 0.2 V. The input impedance is naturally restricted
by the forward-biased base-emitter junction. There are always problems due to the
main charge carriers passing through the region where the majority carriers are of
opposite polarity.

The field effect transistor (JFET) overcomes some of the problems of the bipolar
junction transistor. JFETs come in two types : N- channel and P- channel.

The designation refers to the polarity of the majority charge carriers in the bar of
semiconductor that connects the drain terminal D to the source terminal S. Since the
channel is formed from a single polarity (unipolar) material, its resistance is a
function only of the geometry of the conducting volume and the conductivity of the
material. The JFET operates with all PN junctions reverse-biased so as to obtain a
high input impedance into the gate.

    Common Source Configuration :

The common source configuration for a FET is similar to the common emitter bipolar
transistor configuration and is shown in figure(1). The common source amplifier can
provide both a voltage and current gain. Since the input resistance looking into the
gate is extremely large the current gain available from the FET amplifier can be large
but the voltage gain is generally inferior to that available from a bipolar device. The
source by-pass capacitor is connected to provide a low impedance path to ground for
high frequency components. As a result of presence of by-pass capacitor, AC signals
wi11 not cause a swing in the bias voltage.

Since the FET gate current is small we can make the approximations i D=is and
Vg=Vgs: the source is positive with respect to the gate for reverse bias.

                        Figure (1): Common source configuration

Note: Don't forward bias JFET gate, forward gate current larger than 50 mA will
burn out the JFET.

Lab Work:

Part 1: JFET Biasing:

   1. Refer to figure (1) use VDD = 14V.

   2. Operating point IDQ = 4mA and Vout = 10 V.

   3. Set RG = 1M ohm (or 2M ohms).

   4. Place Rd with the value calculating in the pre-lab to get the desired operating

   5. Adjust the value of Rs until it matches the calculated value.

   6. Switch the power on and confirm the Q-point, try to tune Rs until IQis close
       as possible to 4mA.

   7. Summarize your measurements in table (1).
    IDQ               Vout              VDSQ                  Rs              RD

                                       Table (1)

Part 2: JFET Amplification:


                   Rsource        C1                               10u


       Function Generator

                                       Figure (2)

   1. Refer to figure (2).

   2. Apply AC sine wave from the function generator (100mV p-p at 1KHz).

   3. Observe the input and output signal on the oscilloscope.

   4. Vary the amplitude of AC input as shown in table (2).

   5. Record the corresponding parameters using the voltmeter.

   6. Plot the input and the output signal on the same paper.

   7. Connect the RL = 10k and measure Av, Avs, Ro.

   8. Shunt Rs with 10uF capacitor, put AC signal 100mV p-p and observe the
      output voltage on the oscilloscope.
  Vin(t) 1kHz (rms)     Vg(t) Iout Vout(t) Ro=Vout/Iout        Distortion   Av    Avs







                                     Table (2)


   1. For the circuit in figure (1), Find JFET power and compare your result with
      data sheet.

   2. For the circuit of figure (2), Does the output voltage increases or decreases
      compared with first steps? Why?

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