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Operational Amplifier

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					      Design of Single Stage Open Loop Op-Amp


The op-amp which I designed primarily consisted of three parts:
   1. The current mirror
   2. Differential amplifier
   3. Active load

Current Sink Design:
All the three components need to be DC biased at proper DC voltages. I assumed a
current of 100 microAmp through the reference branch of the current mirror and intended
to draw the same current at the other end. Using the saturation equation I worked out the
possible value of “overdrive voltage” and using DC analysis in the software found out the
values of drain voltage and gate voltage to keep the transistor in saturation. With drain
voltage known I calculated the value of resistance.
 I selected the value of W/L to be 4 since this ensured the required current.

Differential Amplifier Design:

Using the same DC analysis and evaluating the saturation equation I properly DC biased
the differential amplifier. I selected the W/L for both the amplifiers transistors to be 3
since this ensured me that both of them are in saturation.

Active Load:

I set their W/L to be 20 since this ensured the required amount of voltage drop across the
load.
Schematic of op amp with DC operating points shown:
Schematic showing the W and L of CMOS transistors:
Transient Response:
Op-Amp Specifications:
  1. Gain:
Turned out to be 27 dB at maximum.




   2. Bandwidth:
A minimun BW of 100MHz was observed.
   3. Lower 3 dB frequency:
Was observed to be around 144MHz




   4. Unity Gain Frequency:
      Frequency where the gain reduces to 1 is 2GHz.
   5. Phase Margin:
      The phase of the amplifier where the gain reduces to 1 is -110
      degress.




Op-Amp with passive load:

Using resistors as load, and applying the small signal to the differential input I analyzed
the output. With differential input as the current increases in one branch of differential
amplifier, the same amount of current decreases in the other one. I used a subtractor to
subtract the voltages generated at the two drains. For common signals to both inputs the
result was almost zero.



                                                                     SAMI UR REHMAN
                                                                    samiseecs@gmail.com

				
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posted:4/6/2011
language:English
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