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LAB 1

On
Basic Analog Building Blocks

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Summary
Lab 1 is regarding Cadence-Virtuoso software and a tutorial on the use of schematic capture and
analog simulation tools. Students will be required to develop schematics and work out DC, AC and
Transient Analysis for a basic CS amplifier and Current mirror circuitry.

Learning Objectives

1. Setup and become familiar with the Cadence software package
2. Practice schematic entry with Cadence Virtuoso and functional simulation using Cadence
specter simulator.
3. Observe the functional characteristics of several basic analog circuit blocks
4. Generate schematics for CS amplifier and Current mirror circuit and figure out their basic
functionality.

Resources
2. Following links can also be very useful for getting started with the Cadence.

http://www.vlsi.wpi.edu/cds/

Estimated Time to Complete
3-4 hours plus report preparation.

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Common Source Amplifier

Build Common Source amplifier using the handout given to you. The schematic of the probable CS
amplifier is given to you for help.

Circuit Specification:
Source: 5V
Aspect ratio of MOS: 20
Input: 50mV riding on 700mV DC level.

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1) Go through the DC, AC and Transient analysis of the circuit and work out the following
parameters:

For DC Analysis: VG, VD, ID
For Transient Analysis: Output Signal Swing, saturation limits
For AC Analysis: Magnitude and Phase response, poles and zeros of the circuit.

Now figure out the following (using three different values of the parameter under consideration) and
briefly state the reasons if there occurs any change:

Change of the circuit’s gain by changing the aspect ratio.
Change in ID with change in aspect ratio.
Change in gain with change in load resistance.
Change in gain with change in VG.
Change in output swing with change in load resistance.
Change in output swing with change in small signal amplitude.

2) Now append an appropriate degenerative resistance and workout its affect on the gain. Now
does the gain change with slight variations in ID ? If not then why?

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Current Mirrors
Build the current mirror circuit, like one shown in the following figure, using the Cadence tutorial
given to you.

Circuit Specifications

MOS pair aspect ratio: 5
IREF = 100u
Power Supply: 2.5

1) Append the following values of load resistors and watch out whether current in mirrored
branch follows IREF. Give reason in any case.

RL = 1K, RL = 10K, RL = 15K, RL = 50K, RL = 100K

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2) Now build the cascaded current mirror like the one shown in the following figure and work
out the effect of changing load on the current in the mirrored branch.

Remember to keep all the MOSFETs in saturation and state reasons why the varying load resistance
does not affect the ID like it was doing before?

GOOD LUCK