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Introduction to the PCI bus

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					      ogic                                                         Introduction to
                 evelopm ent ApS
www.logic-development.dk                                             the PCI bus
+45 70 22 19 44
sl@logic-development.dk



The PCI is used in PC’s as a common standardized bus interface standard. The well known edge connector PCI cards
took over from the ISA/EISA cards from about a decade ago in desktop PC’s. The basic PCI signaling is used in
derivatives of the standard which make the PCI standard one of the most used bus standard in PC based systems. Here
is a list of where the PCI bus is used today.

• PCI add-in cards used in desktop PC’s
• Single Board Computers (SBC) with PC/104plus. Typical used “small form factor” industrial applications. The
  PC/104plus will take over from the PC/104 (ISA bus signaling) in new SBC’s because of higher requirement to
  bandwidth and lack of (new) components with ISA interface.
• Compact PCI. A rack based rugged industrial variant typical used in telecom installation, data acquisition system
  and industrial automation systems. There are different possibilities in compactPCI, e.g. hot swap and additional
  backplane connections.
• PXI. National Instruments variant of compactPCI with integrated timing and triggering.
• PC Cards (or PCMCIA cards). A small form factor (55mm by 85 mm) dynamical removable card using in laptop
  PC’s (most laptop PC’s have 1-2 PC card slots).
• miniPCI. Internal small form factor add-in card used in laptop PC’s.
• Embedded PCI, PCI on PCB. Applications without a PCI connector but PCI devices are connected directly to the
  host processor on a PCB.

PCI technical overview
The PCI bus is a 32 bit bus with multiplexed address and data. The signaling is synchronous with a 33MHz clock1. All
PCI devices shall be slave capable, but the master mode is optional. As explained bellow using slave only devices has
big impact on system performance.
The PCI bus has an aggregate bandwidth of 4*33MHz = 132Mbytes/s = 1056Mbits/s. How close we can come to this
maximum bandwidth is discussed in the following two scenarios.

A PCI based system with slave only devices is shown in Figure 1. The devices are memory mapped2 into the processors
addressing space. All access and communication to the devices is done by the processor executing read/write
instructions.

Slave only devices characteristic see Figure 1:
• The PC host bridge is master and is using single word (32 bit) operations which typical takes 4 PCI clocks. This
    gives a maximum bandwidth of: 4*33MHz/4 = 33Mbytes/s = 264Mbits/s.
• This is the theoretical maximum, and will be lower if:
        o The processor is loaded with other tasks.
        o There is communication to other devices on the PCI bus.
• The processor is using CPU power to transfer the data (typical done by the driver software).




1
  The 32bit/33MHz is the most used PCI variant, also 64 bit and 66MHz variant of the standard is available.
2
  The PCI specification allows for IO mapping, but it is not recommend for new designs because the addressing space is
limited to 10 bits PC systems.


July 10, 2002. PCINote1                                                                                   page 1 of 3
        ogic                                                            Introduction to
                  evelopm ent ApS
www.logic-development.dk                                                  the PCI bus
+45 70 22 19 44
sl@logic-development.dk




      Hardware view                                                         Software view
                                                                             PCI #1 slave registers and
                                                                                      memory
               Processor
                                                                             PCI #2 slave registers and
                                                                                      memory




                                                                                                          Processor addressing space
             PCI bridge/
                                           Main memory
           memory controller

                           PCI bus


                                                                                   Main memory
           PCI slave                 PCI slave

         PCI module #1           PCI module #2




Figure 1 PCI based system with slave only devices.

A PCI based system with master and slave capable devices is shown in Figure 2. The devices slave registers are
memory mapped into the processors addressing space. These registers are used for configuration and control type of
data which only requires small access bandwidth. In the main memory a buffer is allocated to each device to which the
master part of the PCI device is allowed to read/write data from. These buffers are typical used to data which requires
high bandwidth.

Slave/master devices characteristic see Figure 2:
• The device is master and the PC host bride is slave. It is possible to initiate PCI burst operations of data from the
    device to the main memory (both read and write is possible). With a typical burst length of 64 words the maximum
    bandwidth is3: 64/66*132Mbytes/s = 128Mbytes/s = 1024Mbits/s.
• This is the theoretical maximum, and will be lower if:
        o There is communication to other devices on the PCI bus.
• The device can burst data directly to the main memory in the background without the processor is involved (similar
    to DMA), i.e. saving of CPU power/MIPS.


Conclusion:
To have a maximum utilization of the PCI bus and offload the processor it is important to make PCI devices
which are master capable.




3
    In the calculation there is used 2 PCI cycles to addressing and turn around for every burst.


July 10, 2002. PCINote1                                                                                                                page 2 of 3
      ogic                                                         Introduction to
                 evelopm ent ApS
www.logic-development.dk                                             the PCI bus
+45 70 22 19 44
sl@logic-development.dk




    Hardware view                                                     Software view

                                                                         PCI #1 slave registers
              Processor

                                                                         PCI #2 slave registers




                                                                                                      Processor addressing space
            PCI bridge/
                                        Main memory
          memory controller                                           Buffer allocated to #1 master

                                                                      Buffer allocated to #2 master
                          PCI bus


                                                                             Main memory
       PCI master and           PCI master and
           slave                    slave

       PCI module #1            PCI module #2




Figure 2 PCI based system with master/slave capable devices.




Other things possible with master capable devices:
• It is possible to burst data directly between two PCI devices.
• It is possible for a PCI device to use the PC main memory as “local” memory. The advantage of this is the cost of
    PC main memory typical is cheaper than to put it on the PCI module. Off course there are some latency and
    bandwidth issues.




July 10, 2002. PCINote1                                                                                                            page 3 of 3

				
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