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B.Narayana Babu, Sankara College, Kanchipuram NUMBER SYSTEMS, BOOLEAN ALGEBRA AND LOGIC GATES Number Systems 1. Binary Number System 2. Octal Number System 3. Hexadecimal Number System 4. Binary Arithmetic 5. BCD Addition 6. Alphanumeric Codes Boolean Algebra and Logic Gates 1. AND Gate 2. OR Gate 3. NOT Gate 4. NAND Gate 5. NOR Gate 6. XOR Gate 7. Basic Laws of Boolean Algebra 8. De-Morgan’s Theorems NUMBER SYSTEMS A number system relates quantities and symbols. The base or radix of a number system represents the number of digits or basic symbols in that particular number system. In decimal system the base is 10, because of use the numbers 0, 1, 2,3,4,5,6,7,8 and 9. 1. Binary Number System A binary number system is a code that uses only two basic symbols. The digits can be any two distinct characters, but it should be 0 or 1. The binary equivalent for some decimal numbers are given below Decimal 0 1 2 3 4 5 6 7 8 9 10 11 Binary 0 1 10 11 100 101 110 111 1000 1001 1010 1011 Each digit in a binary number has a value or weight. The LSB has a value of 1. The second from the right has a value of 2, the next 4 , etc., 16 8 4 2 1 24 23 22 21 20 1 B.Narayana Babu, Sankara College, Kanchipuram Binary to decimal conversion: (1001)2 = X10 1001 =1x23 + 0x22 + 0x21 +1x20 =8+0+0+1 (1001)2 = (9)10 Fractions: For fractions the weights of the digit positions are written from right of the binary point and weights are given as follows. 2-1 2-2 2-3 2-4 2-5 E.g.: (0.0110) 2= X10 =0x2-1 + 1x2-2+ 1x2-3 + 0x2-4 =0 x0.5 + 1x0.25 + 1x0.125 + 0x0.0625 = (0.375)10 E.g.: 1011.101) 2=X10 =1x23 + 0x22 + 1x21 + 1x20 + 1x2-1 + 0x2-2 + 1x2-3 =8 + 0 + 2 + 1 + 0.5 + 0 + 0.125 = (11.625)10 Decimal to binary conversion: (Double Dabble method) In this method the decimal number is divided by 2 progressively and the remainder is written after each division. Then the remainders are taken in the reverse order to form the binary number. E.g.: (12)10 = X2 (12)10 = (1100)2 E.g.: (21)2 = X2 (21)2 = (10101)2 2 B.Narayana Babu, Sankara College, Kanchipuram Fractions: The fraction is multiplied by 2 and the carry in the integer position is written after each multiplication. Then they are written in the forward order to get the corresponding binary equivalent. E.g.: (0.4375)10 = X2 2 x 0.4375 = 0.8750 => 0 2 x 0.8750 = 1.750 => 1 2 x 0. 750 = 1.5 => 1 2 x 0.5 = 1.0 => 1 (0.4375)10 = (0.0111)2 Octal Number System Octal number system has a base of 8 i.e., it has eight basic symbols. First eight decimal digits 0, 1,2,3,4,5,6,7 are used in this system. Octal to decimal conversion: In the octal number system each digit corresponds to the powers of 8. The weight of digital position in octal number is as follows 84 83 82 81 80 8-1 8-2 8-3 To convert from octal to decimal multiply each octal digit by its weight and add the resulting products. (48)8 = X10 48 = 4 x 81 + 7 x 80 = 32 + 7 = 39 (48)8 = (39)10 E.g.: (22.34)8 = X10 22.34 = 2 x 81 + 2 x 80 + 3 x 8-1 + 4 x 8-2 =16 + 2 + 3 x 1/8 +4 x 1/64 = (18.4375) (22.34)8 = (18.4375)10 3 B.Narayana Babu, Sankara College, Kanchipuram Decimal to octal conversion: Here the number is divided by 8 progressively and each time the remainder is written and finally the remainders are written in the reverse order to form the octal number. If the number has a fraction part, that part is multiplied by 8 and carry in the integer part is taken. Finally the carries are taken in the forward order. E.g.: (19.11)10 = X8 0.11 x 8 = 0.88 => 0 0.88 x 8 = 7.04 => 7 0.04 x 8 = 0.32 => 0 0.32 x 8 = 2.56 => 2 0.56 x 8 = 4.48 => 4 (19.11)10 = (23.07024)8 Octal to binary conversion: Since the base of octal number is 8, i.e., the third power of 2, each octal number is converted into its equivalent binary digit of length three. E.g.: (57.127)8 = X2 5 7 . 1 2 7 101 111 . 001 010 111 (57.127)8 = (101111001010111)2 Binary to octal: The given binary number is grouped into a group of 3 bits, starting at the octal point and each group is converted into its octal equivalent. E.g.: (1101101.11101)2 = X8 001 101 101.111 010 1 5 5 . 7 2 (1101101.11101)2 = (155.72) 8 4 B.Narayana Babu, Sankara College, Kanchipuram Hexadecimal Number System: The hexadecimal number system has a base of 16. It has 16 symbols from 0 through 9 and A through F. Decimal Hexadecimal Binary 0 0 0000 1 1 0001 2 2 0010 3 3 0011 4 4 0100 5 5 0101 6 6 0110 7 7 0111 8 8 1000 9 9 1001 10 A 1010 11 B 1011 12 C 1100 13 D 1101 14 E 1110 15 F 1111 Binary to hexadecimal: The binary number is grouped into bits of 4 from the binary point then the corresponding hexadecimal equivalent is written. E.g.: (100101110 . 11011) 2 = X16 0001 0010 1110 . 1101 1000 1 2 E . D 8 (100101110 . 11011) 2 = (12E . D8)16 Hexadecimal to binary: Since the base of hexadecimal number is 16, i.e., the fourth power of 2, each hexadecimal number is converted into its equivalent binary digit of length four. E.g.: (5D. 2A)16 = X2 5 D . 2 A 0101 1101 . 0010 1010 (5D. 2A)16 = (01011101.00101010)2 5 B.Narayana Babu, Sankara College, Kanchipuram Decimal to hexadecimal: The decimal number is divided by 16 and carries are taken after each division and then written in the reverse order. The fractional part is multiplied by 16 and carry is taken in the forward order. E.g.: (2479.859)) 10 = X 16 16 x 0.859 = 13.744 => 13 (D) 16 x 0.744 = 11.904 => 11 (B) 16 x 0.904 = 14.464 => 14 (E) 16 x 0.464 = 7.424 => 7 16 x 0.424 = 6.784 => 6 (2479.859)10 = (9AF.DBE76)16 Hexadecimal to decimal: Each digit of the hexadecimal number is multiplied by its weight and then added. E.g.: (81.21) 16 = X10 =8 x 161 + 1 x 160 + 2 x 16-1 + 1 x 16-2 =8 x 16 + 1 x 1 + 2/16 + 1/162 = (129.1289)10 (81.21) 16 = (129.1289)10 Binary Arithmetic Binary Addition: To perform the binary addition we have to follow the binary table given below. 0+0=0 0+1=1 1+0=1 1 + 1 = 0 => plus a carry-over of 1 Carry-overs are performed in the same manner as in decimal arithmetic. Since 1 is the 6 B.Narayana Babu, Sankara College, Kanchipuram largest digit in the binary system, any sum greater than 1 requires that a digit be considered over. E.g.: 111 1010 11.01 _110 _1101 101.11 1001 10111 1001.00 Binary Subtraction: To perform the binary subtraction the following binary subtraction table should be followed. 0–0=0 1–0=1 1–1=0 0 – 1 = 1 with a borrow of 1 is equivalent to 10 – 1 = 1 E.g.: 111 010 101 E.g.: 110.01 100.10 001.11 1’s complement: To obtain 1’s complement of a binary number each bit of the number is subtracted from 1. E.g.: Binary number 1’s Complement 0101 1010 1001 0110 1101 0010 0001 1110 Thus 1’s complement of a binary number is the number that results when we change each 0 to a 1 and each 1 to a 0. 1’s complement subtraction: Instead of subtracting the second number from the first, the 1’s complement of the second number is added to the first number. The last carry which is said to be a END AROUND CARRY, is added to get the final result. 7 B.Narayana Babu, Sankara College, Kanchipuram E.g.: 7 111 -----------------> 111 + 3 011 1’s complement 100 4 1011 + └→1 100 -> result If there is no carry in the 1’s complement subtraction, it indicates that the result is a negative and number will be in its 1’s complement form. So complement it to get the final result. E.g.: 8- 1000 -----------------> 1000 + 10 1010 1’s complement 0101 4 1101 1’s complement - 0010 result The following points should be noted down when we do 1’s complement subtraction. 1. Write the first number (minuend) as such. 2. Write the 1’s complement of second number(subtrahend) 3. Add the two numbers. 4. The carry that arises from the addition is said to be “end around carry”. 5. End-around carry should be added with the sum to get the result. 6. If there is no end around carry find out the 1’s complement of the sum and put a negative sign before the result as the result is negative. 2’s Complement: 2’s complement results when we add ‘1’ to 1’s complement of the given number i.e., 2’s complement =1’s complement + 1 Binary Number 1’s complement 2’s complement 1010 0101 0110 0101 1010 1011 1001 0110 0111 0001 1110 1111 2’s Complement Subtraction: Steps: 1. Write the first number as such 2. Write down the 2’s complement of the second number. 3. Add the two numbers. 4. If there is a carry, discard it and the remaining part (sum) will be the result (positive). 5. If there is no carry, find out the 2’s complement of the sum and put negative sign before the result as the result is negative. 8 B.Narayana Babu, Sankara College, Kanchipuram E.g.: 1) 10 - 1010 -----------------> 1010 + 8 1000 2’s complement 1000 2 10010 0010 -> result 2) 5- 0101 -----------------> 0101 + 12 1100 2’s complement 0100 4 1001 2’s complement – 0111-> result Binary multiplication: The table for binary multiplication is given below 0x0=0 0x1=0 1x0=0 1x1=1 E.g.: 1011 x 110 1011 x 110 0000 1011 1011 __ 1000010_ E.g.: 101.01 x 11.01 101.01 x 11.01 101 01 00000 10101 _10101__ 10001.0001 Binary division: The table for binary division is as follows. 0÷1=0 1÷1=1 As in the decimal system division by zero is meaning less. 9 B.Narayana Babu, Sankara College, Kanchipuram E.g.: 1) 1100 ÷ 11 100_ 11│1100 │11__ 0 2) 1001 ÷ 10 _100.1 10 │1001 │10__ 0010 10 0 BCD Addition Binary Coded Decimal(BCD) is a way to express each of the decimal digits with a binary code. There are only ten code groups in the BCD system. The 8421 code is a type of BCD code. In BCD each decimal digit , 0 through 9 is represented by a binary code of four bits. The designation of 8421 indicates the binary weights of the four bits (23,22,21,20). The largest 4-bit code is 1001. The numbers 1010, 1011, 1100, 1101, 1110, and 1111 are called forbidden numbers. The following table represents the decimal and 8421 equivalent numbers. Decimal digit 0 1 2 3 4 5 6 7 8 9 BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 8421 Addition: In 8421 addition, if there is a carry or if it results in a forbidden group, then 0110(6) should be added in order to bring the result to the 8421 mode again. E.g.: 8 + 1000 + 7 0111 15 1111 + 0110 0001 0101 10 B.Narayana Babu, Sankara College, Kanchipuram E.g.: 18 + 0001 1000 + 2 0000 0010 20 0001 1010 + 0000 0110 0010 0000 Alphanumeric code Computers, printers and the other devices must process both alphabetic and numeric information. Serial coding systems have been developed to represent alphanumeric information as a series of 1’s and 0’s. The characters to be coded are alphabets(26), numerals (10) and special characters such as +,-, /,*, $ etc, In order to code a character, string of binary digits is used. In order to ensure uniformity in coding, two standard codes have been used. 1. ASCII: American Standard Code for Information Interchange. 2. EBCDIC: Extended Binary Coded Decimal Interchange Code. It is an 8 bit code. ASCII is 7-bit code of the form X6, X5, X4, X3, X2, X1, X0 and is used to code two types of information. One type is the printable character such as alphabets, digits and special characters. The other type is known as control characters which represent the coded information to control the operation of the digital computer and are not printed. 11 B.Narayana Babu, Sankara College, Kanchipuram BOOLEAN ALGEBRA AND LOGIC GATES 1. AND gate A gate is simply an electronic circuit which operates a one or more signals to produce an output signal. The output is high only for certain combination of input signals. An AND gate (Figure 1.1) has a high output only when all inputs are high. The output is low when any one input is low. AND gate Boolean expression for AND gate operation is Y=A . B Truth table A B Y=A.B 0 0 0 0 1 0 1 0 0 1 1 1 OR gate An OR gate (Figure 1.2) produces a high output when any or the entire inputs are high. The output is low only when all the inputs are low. OR gate The Boolean expression for an OR gate is Y=A+B Truth table: A B Y=A+B 0 0 0 0 1 1 1 0 1 1 1 1 NOT gate: A NOT gate (Figure 1.3) is also called an inverter. The circuit has one input and one output. The output is the complement of the input. If the input signal is high, the output is low and vice versa. 12 B.Narayana Babu, Sankara College, Kanchipuram NOT gate The Boolean expression for NOT gate is Y=Ā Truth table: A -- Y=A 0 0 0 1 1 0 1 1 If two NOT gates are cascaded then the output will be same as the input and the circuit is called buffer circuit. NAND gate A NAND (Figure 1.4) gate has two or more input signals but only one output signal. All input signals must be high to get a low output. When one AND gate is combined with a NOT gate, a NAND gate is obtained. NAND gate Truth table: A B ---- Y=A.B 0 0 1 0 1 1 1 0 1 1 1 0 NOR gate: NOR gate (Fig. 1.5) has two or more input signals and one output signal. It consists of one OR gate followed by an inverter. A NOR gate produces a high output only when all the inputs are low. 13 B.Narayana Babu, Sankara College, Kanchipuram NOR gate Truth table: A B ----- Y=A+B 0 0 0 0 1 0 1 0 0 1 1 1 XOR gate XOR gate is an abbreviation of exclusive OR gate. It has two inputs and one output. For a two input XOR gate, the output is high when the inputs are different and the output is low when the inputs are same. In general, the output of an XOR gate is high when the number of its high inputs is odd. The Boolean expression of the XOR gate is _ _ Y = A.B + A.B a) Logic diagram 14 B.Narayana Babu, Sankara College, Kanchipuram b) Logic symbol: XOR gate Truth table: A B Y= A B 0 0 0 0 1 1 1 0 1 1 1 0 Uses of XOR gate: 1. Binary to Gray Converter Binary to Gray Converter The Figure 1.7 shows the way to convert binary number to gray number using XOR gates. Since mod-2 addition is involved in the conversion, XOR gate is used for this purpose. 2. Gray to Binary Converter: XOR gate is also used to convert gray code to a binary number. The circuit diagram for this operation is shown in the Figure Gray to Binary Converter 15 B.Narayana Babu, Sankara College, Kanchipuram 3. Parity checker: Parity checker can be designed using XOR gates as given in the below Figure. Here the parity of the word ABCD is checked. The circuit adds the bits of ABCD. A final sum of 0 implies even parity and a sum of 1 means odd parity. Parity checker Basic Laws of Boolean Algebra Commutative law: A+B=B+AB +A=A+B Associative law: A + (B + C) = (A + B) + C A. (B.C) = (A.B).C Distributive law A. (B + C) = A.B + A.C Other laws of Boolean algebra: 1. A + 0 = A 2. A + 1 = 1 3. A + A = A 4. A + Ā = 1 5. A .0 = 0 6. A .1 = A 7. A .A = A 8. A . Ā = 0 9. A = A 10. A + A.B =A 11. A.(A + B) = A 12. (A + B).(A+C) = A + B.C 13. A + Ā.B =A + B 14. A.(Ā +B) = A.B 15. (A + B).(Ā + C) = A.C + Ā.B 16. (A + C).(Ā + B) = A.B + Ā.C 16 B.Narayana Babu, Sankara College, Kanchipuram De Morgan’s Theorems: I Theorem statement: The complement of a sum is equal to the product of the complements. _____ _ _ A +B=A.B II Theorem Statement: The complement of a product is equal to the sum of the complements. ____ _ _ A . B= A+B Proof of first theorem: _____ _ _ To prove A + B = A . B Case 1: A=0, B=0 _____ _____ _ L.H.S => A + B = 0 + 0 = 0 = 1 _ _ _ _ R.H.S => A . B = 0 . 0 = 1 .1 = 1 Case 2: A=0, B=1 _____ _____ _ L.H.S => A + B = 0 + 1 = 1 = 0 _ _ _ _ R.H.S => A . B = 0 . 1 = 1 .0 = 0 Case 3: A=1, B=0 _____ _____ _ L.H.S => A + B = 1 + 0 = 1 = 0 _ _ _ _ R.H.S => A . B = 1 . 0 = 0 .1 = 0 Case 4: A=1, B=1 _____ _____ _ L.H.S => A + B = 1 + 1 = 1 = 0 _ _ _ _ R.H.S => A . B = 1 . 1 = 0 .0 = 0 17 B.Narayana Babu, Sankara College, Kanchipuram Truth table A B _____ _ _ A+B A.B 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 Proof of second theorem: ____ _ _ To prove A . B = A + B Case 1: A=0, B=0 ____ ___ _ L.H.S => A . B = 0 . 0 = 0 = 1 _ _ _ _ R.H.S => A + B = 0 + 0 = 1 + 1 = 1 Case 2: A=0, B=1 ____ ____ _ L.H.S => A . B = 0 . 1 = 0 = 1 _ _ _ _ R.H.S => A + B = 0 + 1 = 1 + 0 = 1 Case 3: A=1, B=0 ____ ____ _ L.H.S => A . B = 1 . 0 = 0 = 1 _ _ _ _ R.H.S => A + B = 1 + 0 = 0 +1 = 1 Case 4: A=1, B=1 ____ ____ _ L.H.S => A . B = 1 . 1 = 1 = 0 _ _ _ _ R.H.S => A + B = 1 + 1 = 0 +0 = 0 Truth table A B _____ _ _ A.B A+B 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 18 B.Narayana Babu, Sankara College, Kanchipuram GLOSSARY Alphanumeric : Consisting of numerals, letters, and other characters. ASCII : American Standard Code for Information Interchange. BCD : Binary Coded Decimal ; a digit code in which each of the decimal digits , 0 through 9, is represented by a group of four bits. Binary : Describes a number system that has a base of two and utilizes 1 and 0 as its digits. Boolean algebra : The mathematics of logic circuits. Gate : A logic circuit that performs a specified logic operation , such as AND, OR or NOT. Hexadecimal : Describes a number system with a base of 16 Octal : Describes a number system with a base of 8. Parity : Parity is based on the number of 1’s in a binary word. If the number of 1’s in a word is odd, then it is a odd parity word and if the number of 1’s is even, then it is an even parity word. Truth table : A table showing the inputs and corresponding output levels of a logic circuit. Universal gate : Either a NAND gate or a NOR gate. 19 B.Narayana Babu, Sankara College, Kanchipuram BOOLEAN EXPRESSIONS AND COMBINATIONA LOGIC CIRCUIT 1. Simplification of Boolean Expressions Sum of Products Product of Sums Canonical SOP and POS Forms Karnaugh Maps Implementing Boolean Expressions Using NAND Gates Implementing Boolean Expressions Using NOR Gates 2. Combinational Logic Circuits Half Adder Full Adder Half Subtractor Full Subtractor Parallel Binary Adder BCD Adder Encoders Decoders Multiplexers Demultiplexers 20 B.Narayana Babu, Sankara College, Kanchipuram 1. Simplification of Boolean Expressions: Simplification of Boolean functions is mainly used to reduce the gate count of a design. Less number of gates means less power consumption, sometimes the circuit works faster and also when number of gates is reduced, cost also comes down. There are many ways to simplify a logic design; some of them are given below. We will be looking at each of these in detail in the next few pages. Algebraic Simplification. Simplify symbolically using theorems/postulates. Requires good skills Karnaugh Maps. Diagrammatic technique using 'Venn - diagram'. Limited to not more than 6 variables Some of the examples are given here: 1. Simplify the Boolean expression XY′Z′+XY′Z′W+XZ′ The above expression can be written as XY′Z′ (1+W) +XZ′ =XY′Z′+XZ′ as 1+W=1 =XZ′ (Y′+1) =XZ′ as Y′+1=1 2. Simplify the Boolean expression X+X′Y+Y′+(X+Y′) X′Y The above expression can be written as X+X′Y+Y′+XX′Y+Y′X′Y =X+X′Y+Y′ as XX′=0, and YY′=0 =X+Y+Y′ as X+X′Y=X+Y =X+1 as Y+Y′=1 =1 as X + 1=1 21 B.Narayana Babu, Sankara College, Kanchipuram 3. Simplify the Boolean expression Z(Y+Z) (X+Y+Z) The above expression can be written as (ZY+ZZ)(X+Y+Z) = (ZY+Z) (X+Y+Z) as ZZ=Z =Z(X+Y+Z) as Z+ZY=Z =ZX+ZY+ZZ =ZX+ZY+Z as ZZ=Z, =ZX+Z as Z+ZY=Z =Z as Z+ZX=Z 4. Simplify the Boolean expression (X+Y)(X′+Z)(Y+Z) The above expression can be written as (XX′+XZ+YX′+YZ)(Y+Z) =(XZ+YX′+YZ) (Y+Z) as XX′=0 =XZY+YYX′+YYZ+XZZ+YX′Z+YZZ =XZY+YX′+YZ+XZ+YX′Z+YZ as YY=Y, ZZ=Z Rearranging the terms we get XZY+XZ+YX′+YX′Z+YZ as YZ+YZ=YZ =XZ(Y+1) +YX′+YZ (X′+1) as Y+1=1, X′+1=1 =XZ+YX′+YZ Now it seems that it cannot be reduced further. But apply the following trick: The above expression can be written as XZ+YX′+YZ(X+X′) as X+X′=1 =XZ+YX′+YZX+YZX′ Rearranging the terms we get XZ+YXZ+Y X′+YX′Z =XZ (1+Y) +YX′ (1+Z) =XZ+YX′ as 1+Y=1, 1+Z=1 22 B.Narayana Babu, Sankara College, Kanchipuram Sum of Products: A sum of products expression consists of several product terms logically added. A product term is a logical product of several variables. The variables may or may not be complemented. The following are the examples of sum of products expressions. 1. XY+X'Y+XY' 2. AB+ABC+BC' 3. A+AB'+B'C 4. ABC+A'B+AB'C+A'BC' Sometimes a product term may consist of a single variable. Products of Sums: A product of sums expression consists of several sum terms logically multiplied. A sum term is the logical addition of several variables. The variables may or may not be complemented. The following are examples of product of sums expressions: A) (A+B) (A'+B') B) A (B'+C') (B+C) c) (X+Y') (X+Y+Z) (Y+Z) Sometimes a sum term may consist of a single variable. Canonical SOP and POS Forms: When each term of a logic expression contains all variables, it’s said to be in the canonical form. When a sum of products form of logic expression is in canonical form, each product term is called minterm. Each minterm contains all variables. The canonical form of a sum of products expression is also called minterm canonical form or standard sum of products. Similarly, when a product of sums form of logic expression is in canonical form, each sum term is called a maxterm. Each maxterm contains all variables. The canonical form of a product of sums expression is also called maxterm canonical form or standard product of sums. When a logic expression is not in the canonical form, it can be converted into canonical form. In the canonical form there is uniformity in the expression, which facilitates minimization procedure The following are examples of the canonical form of sum of products expressions (or minterm canonical form): (i). Z = XY + XY′ (ii). F = XYZ′ + X′YZ + X′YZ′ + XY′Z + XYZ 23 B.Narayana Babu, Sankara College, Kanchipuram In case of 2 variables, the maximum possible product terms are 4, for 3 variables, the possible product terms are 8, for 4 variables 16, and for n variables, 2ⁿ. In the above examples the expression (ii) contains 5 out of 8 possible product terms. When the expression is in the canonical form all terms are mutually exclusive. It means that for a given set of values of the variables, when one of the terms is equal to 1, all others must be 0. Of course, it is possible that all terms may be 0. The following are examples of canonical form of product of sums expressions (or maxterm canonical form). (i). Z = (X + Y) (X + Y′) (ii). F = (X′ + Y + Z′) (X′ + Y + Z) (X′ + Y′ + Z′) The following table gives the minterms and maxterms for a three variable logical function where the number of minterms as well as maxterms is 2³ = 8. In general, for an n-variable logical function there are 2ⁿ minterms and an equal number of maxterms. Variables Minterms Maxterms A B C mi Mi 0 0 0 A' B' C' = m0 A + B + C = M0 0 0 1 A' B' C = m1 A + B + C' = M1 0 1 0 A' B C' = m2 A + B' + C = M2 0 1 1 A' B C = m3 A + B' + C' = M3 1 0 0 A B' C' = m4 A' + B + C = M4 1 0 1 A B' C = m5 A' + B + C' = M5 1 1 0 A B C' = m6 A' + B' + C = M6 1 1 1 A B C = m7 A' + B' + C' = M7 Minterms and Maxterms for Three variables As shown in the above table each minterm is represented by mi and each maxterm is represented by Mi where i is the decimal number equivalent of the natural binary number. With these shorthand notations logical functions can be represented as follows: 1. Y = A' B' C’ + A’ B’ C + A’ B C + A B C’ = m0 + m1 + m3 + m6 = ∑m( 0, 1, 3, 6 ) 2. Y = ( A + B + C’ ) ( A + B’ + C’ ) ( A’ + B’ + C ) = M1 + M3 + M6 = πM( 1, 3, 6 ) Where ∑ denotes sum of product while π denotes product of sum 24 B.Narayana Babu, Sankara College, Kanchipuram Conversion of Sum of Products Expressions into Canonical Form: The following examples will illustrate how logic expressions can be converted into canonical form. Example 1: Convert the expression X + XY’ into canonical form. The expression has two variables. The first term has only one variable. So to make it of two variables it can be multiplied by (Y + Y’), as Y + Y’ = 1. After multiplication the given logic expression can be written as X(Y + Y′) + XY′, as Y + Y′ = 1 or XY + XY′ + XY′ or XY + XY′ Conversion of Product of Sums Expression into Canonical Form: Before we proceed with such a conversion a few identities should be examined. We can write A = (A + B) (A + B′) This can be proved as follows: A = A +A + 0 = A( B + B′ ) + A.A + B.B′, as B + B′ =1, AA=A, BB′=1 = AB + AB′ + AA + BB′ = A (A +B) + B′ (A + B) = (A + B) (A + B′) Similarly, we can write A + B = (A + B +C) (A + B + C′). (A + B + C) (A + B + C′) = AA + AB + AC′ + AB + BB + BC′ + AC + BC + CC′ Rearranging the terms we get AA + BB + AC′ + BC′ + AC + BC + AB + AB, as CC′ = 0 = (A + B) + C′ (A + B) + C (A + B) + AB + AB [AA = A; BB = B] = (A + B) + (A + B) (C + C′) + AB + AB = (A + B) + (A + B) + AB + AB as C + C′ = 1 = A + B + AB + AB as (A + B) + (A + B) = (A + B) = A + AB + B + AB = A (1 + B) + B (1 + A) =A+B as 1 + B = 1, 1 + A =1 This technique can be extended to any number of variables such as 25 B.Narayana Babu, Sankara College, Kanchipuram (A + B′ + C) = (A + B′ + C + D) (A + B′ + C + D′) Example 1: Convert the following expression into canonical form: (A + B) (B + C) To convert the above expression into canonical form the following identity can be used: X + Y = (X + Y + Z) (X + Y + Z′) Applying the above identity, the given logic expression can be written as (A + B + C) (A + B + C′) (A + B + C) (A′ + B + C) = (A + B + C) (A + B + C′) (A′ + B + C) Karnaugh Maps Karnaugh maps provide a systematic method to obtain simplified sum-of-products (SOPs) Boolean expressions. This is a compact way of representing a truth table and is a technique that is used to simplify logic expressions. It is ideally suited for four or less variables, becoming cumbersome for five or more variables. Each square represents either a minterm or maxterm. A K-map of n variables will have 2 squares. For a Boolean expression, product terms are denoted by 1's, while sum terms are denoted by 0's. A K-map consists of a grid of squares, each square representing one canonical minterm combination of the variables or their inverse. The map is arranged so that squares representing minterms which differ by only one variable are adjacent both vertically and horizontally. Therefore XY'Z' would be adjacent to X'Y'Z' and would also adjacent to XY'Z and XYZ'. Minimization Technique Based on the Unifying Theorem: X + X' = 1 The expression to be minimized should generally be in sum-of-products form (If necessary, the conversion process is applied to create the sum-of-products form). The function is mapped onto the K-map by marking a 1 in those squares corresponding to the terms in the expression to be simplified (The other squares may be filled with 0's). Pairs of 1's on the map which are adjacent are combined using the theorem Y(X+X') = Y where Y is any Boolean expression (If two pairs are also adjacent, then these can also be combined using the same theorem). 26 B.Narayana Babu, Sankara College, Kanchipuram The minimization procedure consists of recognizing those pairs and multiple pairs ->These are circled indicating reduced terms. o Groups which can be circled are those which have two (21) 1's, four (22) 1's, and eight (23) 1's. ->Note that because squares on one edge of the map are considered adjacent to those on the opposite edge, group can be formed with these squares. ->Groups are allowed to overlap. The objective is to cover all the 1's on the map in the fewest number of groups and to create the largest groups to do this. Once all possible groups have been formed, the corresponding terms are identified. ->A group of two 1's eliminates one variable from the original minterm. ->A group of four 1's eliminates two variables from the original minterm. ->A group of eight 1's eliminates three variables from the original minterm, and so on. ->The variables eliminated are those which are different in the original minterms of the group. In any K-Map, each square represents a minterm. Adjacent squares always differ by just one literal (So that the unifying theorem may apply: X + X' = 1). For the 2-variable case (e.g.: variables X, Y), the map can be drawn as in Figure(a). Two variable map is the one which has got only two variables as input. Figure (a) 27 B.Narayana Babu, Sankara College, Kanchipuram Equivalent Labeling K-map need not follow the ordering as shown in the Figure (a). What this means is that we can change the positions of m0, m1, m2, m3 of the above figure as shown in the Figure (b) and Figure (c). Position assignment is the same as the default k-map positions. This is the one which we will be using throughout this unit. Figure (b) This figure is with changed positions of m0, m1, m2, m3. Figure (c) The K-map for a function is specified by putting a '1' in the square corresponding to a minterm, a '0' otherwise. Grouping/Circling K-maps The power of K-maps is in minimizing the terms, K-maps can be minimized with the help of grouping the terms to form single terms as shown in Figure (d). When forming groups of squares, observe/consider the following: 28 B.Narayana Babu, Sankara College, Kanchipuram Every square containing 1 must be considered at least once. A square containing 1 can be included in as many groups as desired A group must be as large as possible. Figure (d) If a square that is containing 1 which cannot be placed in a group, then leave it out to include in final expression. The number of squares in a group must be equal to 2(pair), 4(quad), 8(octet). The map is considered to be folded or spherical; therefore squares at the end of a row or column are treated as adjacent squares. The simplified logic expression obtained from a K-map is not always unique. Groupings can be made in different ways as shown in Figure (e). Before drawing a K-map the logic expression must be in canonical form. 29 B.Narayana Babu, Sankara College, Kanchipuram Figure (e) In the next few pages we will see some examples of grouping. 2-Variable K-Map: Example - F= X'Y+XY In this example we have the equation as input, and we have one output function. Draw the k-map for function F with marking 1 for X'Y and XY positions. Now combine two 1's as shown in Figure 2.2.4 (f) to form the single term. As you can see X and X' get canceled and only Y remains F = Y Figure (f) Example - X'Y+XY+XY' In this example we have the equation as input, and we have one output function. Draw the k-map for function F with marking 1 for X'Y, XY and XY positions. Now combine two 1's as shown in Figure (g) to form two single terms. F=X+Y Figure (g) 30 B.Narayana Babu, Sankara College, Kanchipuram 3-Variable K-Map There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8 cells in a 3-variable K-map. One important thing to note is that K-maps follow the gray code sequence, not the binary one. Using gray code arrangement ensures that minterms of adjacent cells differ by only one literal. Each cell in a 3-variable K-map has 3 adjacent neighbours. In general, each cell in an n- variable K-map has n adjacent neighbours as shown in Figure(h) Figure (h) There is wrap- around in the K-map X'Y'Z' (m0) is adjacent to X'YZ' (m2) XY'Z' (m4) is adjacent to XYZ' (m6) as shown in Figure(i) Figure (i) Example F = XYZ'+XYZ+X'YZ F = XY + YZ 31 B.Narayana Babu, Sankara College, Kanchipuram Example F(X, Y, Z) = (1, 3, 4, 5, 6, 7) F=X+Z 4-Variable K-Map There are 16 cells in a 4-variable (W, X, Y, Z) K-map as shown in the Figure (j). Figure (j) There are 2 wrap-arounds: a horizontal wrap-around and a vertical wrap-around. Every cell thus has 4 neighbours. For example, the cell corresponding to minterm m0 has neighbours m1, m2, m4 and m8 as shown in Figure(k). 32 B.Narayana Babu, Sankara College, Kanchipuram Example F (W, X, Y, Z) = (1, 5, 12, 13) Figure(k) F=WXY'+W'Y'Z Example F (W, X, Y, Z) = (4, 5, 10, 11, 14, 15) F = W'XY' + WY 33 B.Narayana Babu, Sankara College, Kanchipuram Don’t Care: In some digital systems, certain input conditions never occur during normal operations; therefore the corresponding output never appears. Since the output does not appear it is indicated by an X in the truth table. X is called don’t care condition. So don’t cares can be treated as 0’s and 1’s which ever is more convenient in the process of k-map simplification? Consider the following truth table in which the output is low for all input entries from 1001 and ‘X’ from 1010 through 1111. The don’t care conditions are denoted by ’X’. A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X Here three don’t cares are treated as 1’s to get a quad which eliminates two variables. The remaining don’t cares are treated as 0’s. Steps to be followed to apply don’t care conditions: 1. For the given truth table, draw a K-map with 0’s, 1’s and don’t cares. 2. Encircle the actual 1’s on the K-map in the largest groups, by treating the don’t cares as 1’s. 3. After the actual 1’s have been included in groups discard the remaining don’t cares visualizing them as 0’s. 34 B.Narayana Babu, Sankara College, Kanchipuram Implementing Boolean Expressions Using NAND Gates: The implementation of a Boolean function with NAND-NAND logic requires that the function be simplified in the sum of product form. The relationship between AND-OR logic and NAND-NAND logic is explained using the following example. Consider the Boolean function: Y = A B C + D E + F This Boolean function can be implemented using AND-OR logic as shown in Figure (a). Figure (a) AND-OR Figure (b) NAND-Bubbled OR Figure (b) shows the AND gates are replaced by NAND gates and the OR gate is replaced by a bubbled OR gate. The implementation shown in Figure(b) is equivalent to implementation in Figure(a), because two bubbles on the same line represent double inversion (complementation) which is equivalent to having no bubble on the line. In case of single variable, F, the complemented variable is again complemented by bubble to produce the normal value of F. 35 B.Narayana Babu, Sankara College, Kanchipuram Figure(c) NAND-NAND In Figure (c), the output NAND gate is redrawn with the conventional symbol. The NAND gate with same inputs gives complemented result; therefore F′ is replaced by NAND gate with F input to its both inputs. Thus all the three implementations of the Boolean function are equivalent. From the above example we can summarize the rules for obtaining the NAND-NAND logic diagram from a Boolean function as follows: 1. Simplify the given Boolean function and express it in sum of products form (SOP form). 2. Draw a NAND gate for each product term of the function that has two or more literals. The inputs to each NAND gate are the literals of the term. This constitutes a group of first-level gates. 3. If Boolean function includes any single literal or literals draw NAND gates for each single literal and connect corresponding literal as an input to the NAND gate. 4. Draw a single NAND gate in the second level, with inputs coming from outputs of first level gates. Implementing Boolean Expressions Using NOR Gates: The NOR function is a dual of the NAND function. For this reason, the implementation procedures and rules for NOR- NOR logic are the duals of the corresponding procedures and rules developed for NAND-NAND logic. 36 B.Narayana Babu, Sankara College, Kanchipuram The implementation of a Boolean function with NOR-NOR logic requires that the function be simplified in the product of sums form. In product of sums form, we implement all sum terms using OR gates. This constitutes the first level. In the second level all sum terms are logically ANDed using AND gates. The relationship between OR- AND logic and NOR-NOR is explained using following example Consider the Boolean function: Y = (A + B +C) (D + E) F The Boolean function can be implemented using OR-AND logic, as shown in the Figure (a) Figure (a) OR-AND Figure (b) NOR-Bubbled AND In Figure(b) the OR gates are replaced by NOR gates and the AND gate is replaced by a bubbled AND gate. The implementation shown in Figure(b) is equivalent to implementation shown in Figure(a) because two bubbles on the same line represent double inversion (complementation) which is equivalent to having no bubble on the line. In case of single variable, F, the complemented variable is again complemented by bubble to produce the normal value of F. 37 B.Narayana Babu, Sankara College, Kanchipuram Figure (c) NOR-NOR In Figure (c), the output NOR gate is redrawn with the conventional symbol. The NOR gate with same inputs gives complemented result, therefore, F is replaced by NOR gate with F input to its both inputs. Thus all the three implementations of the Boolean function are equivalent. From the above example, we can summarize the rules for obtaining the NOR-NOR logic diagram from a Boolean function as follows: 1. Simplify the given Boolean function and express it in product of sums form(POS form) 2. Draw a NOR gate for each sum term of the function that has two or more literals. The inputs to each NOR gate are the literals of term. This constitute a group of first level gates. 3. If Boolean function includes any single literal or literals, draw NOR gate for each single literal and connect corresponding literal as an input to the NOR gate. 4. Draw a single NOR gate in the second level, with inputs coming from outputs of first level gates 38 B.Narayana Babu, Sankara College, Kanchipuram Combinational Circuits A combinational circuit consists of input variables, logic gates and output variables. The logic gates accept signals from the input variables and generate output signals. This process transforms binary information from the given input data to the required output data. Below Figure shows the block diagram of a combinational circuit. As shown in the figure the combinational circuit accepts n input binary variables and generates m output variables depending on the logical combination of gates. In this section we shall discuss about the functions of Half Adder, Full Adder, Half Subtractor, Full Subtractor, Parallel Binary Adder, BCD Adder, Encoders, Decoders, Multiplexers and Demultiplexers. Half Adder Half adder is a logic circuit that finds the arithmetic sum of two binary digits at a time. Its logic circuit is shown in Figure(a). Figure(a) Half Adder The outputs of the XOR and AND gates produces the sum and carry respectively. THE TRUTH TABLE: A B SUM CARRY A B A.B 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 39 B.Narayana Babu, Sankara College, Kanchipuram Map for SUM Map for CARRY CARRY = A . B The input variables of half adder are augend and addend. The output variables are sum and carry. It is necessary to specify two output variables, because the sum of 1+1=10. Let A & B be input variables SUM and CARRY be output variables. The output ‘CARRY’ represents an AND function. The output SUM represents exclusive OR function. The Boolean functions of the two outputs are SUM =A B and CARRY = A . B Full Adder When two binary numbers are added a carry may be generated onto the subsequent bit positions. Hence, it is required to add three bits for the subsequent additions. A combinational circuit that finds the arithmetic sum of three bits is called a Full adder. A Full adder can be constructed using two half adders and an OR gate as shown in the Figure(a). Figure(a) Full Adder 40 B.Narayana Babu, Sankara College, Kanchipuram Truth table: A B C SUM CARRY 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 Thus a full-adder is a combinational circuit that performs the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables denoted by A, B represents the two significant bits to be added. The third input C represents the carry from the lower significant position. The two outputs are denoted by SUM and CARRY. The Boolean expressions for SUM and CARRY outputs are given below. Half Subtractor: A Half subtractor is a combinational logic circuit which is used to find the difference between two binary digits. Its logic circuit is shown in Figure(a). Figure (a) Half Subtractor 41 B.Narayana Babu, Sankara College, Kanchipuram TRUTH TABLE: A B BORROW DIFFERENCE 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 Map for DIFFERENCE: DIFFERENCE = A'B + AB' =A B Map for BORROW: BORROW = A'B A half subtractor consists of two input variables A and B (minuend and subtrahend) and two output variables DIFFERENCE and BORROW. The DIFFERENCE output is obtained by a 2-input XOR gate. The BORROW output is obtained by the expression A'B Hence DIFFERENCE = A B BORROW = A'B 42 B.Narayana Babu, Sankara College, Kanchipuram Full Subtractor: A full subtractor Figure (a) is a combinational circuit that performs a subtraction between two bits taking into account that a 1 may have been borrowed by a lower significant stage. Figure (a) Full Subtractor This circuit has three inputs and two outputs. The three inputs A, B and C denote the minuend, subtrahend and previous borrow respectively. The two outputs DIFFERENCE and BORROW represent the difference and borrow, respectively. The truth table for the circuit is as follows. A B C BORROW DIFFERENCE 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 43 B.Narayana Babu, Sankara College, Kanchipuram The Boolean functions for the two outputs of the full subtractor are derived in the K-map as shown below. Map for BORROW BORROW = A'C + A'B + B Map for DIFFERENCE Parallel Binary Adder: A parallel binary adder is a digital circuit that produces the arithmetic sum of two binary numbers in parallel. It consists of full adders connected in cascade, with the output carry from one full adder connected to the input carry of the next full adder. Figure shows the circuit diagram of a 4-bit parallel binary adder. Parallel Binary Adder The augend bits of A and the addend bits of B are designated by subscript number from right to left, with subscript 0 denoting the low-order bit. The carries are connected in a chain through the full adders. The input carry to the adder is C0 and the output carry is C4. The S outputs generate the required sum bits. An n-bit parallel 44 B.Narayana Babu, Sankara College, Kanchipuram binary adder requires n full adders. The following example illustrates the parallel binary addition 45 B.Narayana Babu, Sankara College, Kanchipuram BCD adder A BCD adder is a circuit that adds two BCD digits and produces a sum digit also in BCD. BCD numbers use 10 digits, 0 to 9 which are represented in the binary form 0000 to 1001, i.e. each BCD digit is represented as a 4-bit binary number. When we write BCD number say 526, it can be represented as 5 2 6 0101 0010 0110 Here, we should note that BCD cannot be greater than 9. The addition of two BCD numbers can be best understood by considering the two cases that occur when two BCD digits are added. Sum Equals 9 or less with carry 0 : Let us consider additions of 3 and 6 in BCD. 6 0110 BCD for 6 +3 0011 BCD for 3 _____ _____ 9 1001 BCD for 9 The addition is carried out as in normal binary addition and the sum is 1001, which is BCD code for 9. Sum greater than 9 with carry 0 : Let us consider addition of 6 and 8 in BCD 6 0110 BCD for 6 +8 1000 BCD for 8 _____ ______ 14 1110 Invalid BCD number The sum 1110 is an invalid BCD number. This has occurred because the sum of the two digits exceeds 9. Whenever this occurs the sum has to be corrected by the addition of six (0110) in the invalid BCD number, as shown below 46 B.Narayana Babu, Sankara College, Kanchipuram 6 0110 BCD for 6 +8 1000 BCD for 8 _______ ______ 14 1110 Invalid BCD number + 0110 add 6 for correction _____ 0001 0100 BCD for 14 After addition of 6, carry is produced into the second decimal position. Going through these two cases of BCD addition we can summarize the BCD addition procedure as follows: 1. Add two BCD numbers using ordinary binary addition. 2. If the 4-bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD form. 3. If the 4-bit sum is greater than 9 or if a carry is generated from the 4-bit sum, the sum is invalid. 4. To correct the invalid sum, add 01102 to the 4-bit sum. If a carry results from this addition, add it to the next higher-order BCD digit. Thus to implement BCD adder we require: A 4-bit binary adder for initial addition Logic circuit to detect sum greater than 9 and One more 4-bit adder to add 01102 if the sum is greater than 0 or carry is 1, shows the block diagram of a BCD adder. Figure BCD adder 47 B.Narayana Babu, Sankara College, Kanchipuram As shown in above Figure the two BCD numbers, together with input carry, are first added in the top 4-bit binary adder to produce a binary sum. When the output carry is equal to zero (i.e. when sum <=9 and Cout=0) nothing (zero) is added to the binary sum. When it is equal to one (i.e. when sum>9 or Cout=1), binary 0110 is added to the binary sum through the bottom 4-bit binary adder. The output carry generated from the bottom binary adder can be ignored. Encoders An encoder (Figure 2.3.7(a)) converts an active input signal into a coded output signal. There is n input lines of which only one is active. Internal logic within the encoder converts this active input to a coded binary output with m bits. Figure (a) Encoders Decimal to BCD Encoder The Figure(b) shows a common type of encoder such as a Decimal to BCD Encoder. The switches are push-button switches like those of a pocket calculator. When button 3 is pressed, the C and D OR gates receive high inputs. Therefore the output is ABCD=0011 If button 5 is pressed, the output becomes ABCD=0101 When switch 9 is pressed the output is ABCD=1001 Figure (b) Decimal to BCD Encoder 48 B.Narayana Babu, Sankara College, Kanchipuram Decoders A decoder is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of 2n unique output lines. The circuit in Figure (a) represents a 2-to-4 line decoder. Above Figure 2-to-4 decoder. The two inputs are decoded into 4 outputs each output representing one of the minterms of the 2-input variables. The two inverters provide the complement of inputs and each of the four AND gates generate one of the minterms. The following is the truth table of the 2-to-4 line decoder with two inputs and 4 outputs. A B D1 D2 D3 D4 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 Multiplexer A multiplexer is circuit with many inputs but only one output. By applying control signals, we can steer any one of the inputs to the output. Figure (a) illustrates the general idea. The circuit has n input signals, m control signals and one output signal. Figure (a) Multiplexer 49 B.Narayana Babu, Sankara College, Kanchipuram Figure(b) 4-to-1 Multiplexer A B Y 0 0 D1 0 1 D2 1 0 D3 1 1 D4 Figure (b) shows a 4-to-1 Multiplexer. A multiplexer is also called Data selector because the output bit depends on the input data bit that is selected. The input bits are labeled D0 through D4. Only one of these inputs is transmitted to the output, depending on the control inputs AB. For instance, when AB=00 the upper AND gate is enabled while all other AND gates are disabled. Therefore, data bit D0 is transmitted to the output, giving Y=D0. If D0 is low, Y is low; If D0 is high, Y is high. The point is that Y depends only on the value of D0. If control bits are changed to AB=11, all gates are disabled except the bottom AND gate. In this case D3 is the only bit transmitted to the output and Y= D3. As you can see, the control bits determine which of the input data bits is transmitted to the output. 50 B.Narayana Babu, Sankara College, Kanchipuram Demultiplexer A demultiplexer is a logic circuit with one input and may outputs. By applying control signals, we can steer the input signal to one of the output lines. Figure (a) illustrates the general idea. The circuit has 1 input signal, m control signals and n output signals. Figure (a) Demultiplexer Figure (b) 1x4 Demultiplexer Figure (b) shows a 1x4 Demultiplexer. The input bit is labeled as D. This data bit (D) is transmitted to the data bit of the output lines. This depends on the value of AB, the control inputs. When AB=00 the upper AND gate is enabled while all other AND gates are disabled. Therefore the data bit (D) is transmitted only to the Y0 output, giving Y0 = D. If D is low, Y0 is low. If D is high, Y0 is high. As you can see, the value of Y0 depends on the value of D. All other outputs are in the low state. If the control bits are changed to AB=11 all gates are disabled except the bottom AND gate. Then D is transmitted only to the Y3 output and Y3=D. 51 B.Narayana Babu, Sankara College, Kanchipuram Glossary BCD adder A logic circuit that adds two BCD digits and produces a sum digit also in BCD. Decoder is a combinational circuit that converts binary information from ‘n’ input lines to a maximum of 2n unique output lines. Demultiplexer A circuit with one input and many outputs. Don’t care conditions An input output condition that never occurs during normal operations. Since the condition never occurs, you can use X in the truth table. Encoder An circuit that converts an active input signal into coded output form. Full adder A logic circuit with three inputs and two outputs. The circuit adds three bits at a time, giving a sum and a carry output. Half adder A logic circuit with two inputs and two outputs. It adds two bits at a time, producing a sum and a carry output. Half subtractor A logic circuit that subtracts two bits and produce their difference. Full subtractor A logic circuit that performs a subtraction between two bits, taking into account borrowing by lower significant stage. It has three inputs and two outputs. Karnaugh map A map that shows all the fundamental products and the corresponding output values of a truth table. Multiplexer A circuit with many inputs but with only one output. Octet Eight adjacent 1s in a karnaugh map. Overlapping groups Using the same 1 more than once when looping the 1s of a karnaugh map. Pair Two horizontally or vertically adjacent 1s in a Karnaugh map.. Parallel binary adder A logic circuit with number of full adders connected in cascade. The carry output of each adder is connected to the carry input of the next higher adder. Product of sum equation The logical product of those fundamental sums that produce output 1s in the truth table. Quad Four horizontal, vertical, or rectangular 1s in a Karnaugh map. Redundant group A group of 1s in a karnaugh map that is a part of other groups. Sum of products equation The logical sum of those fundamental products that produce output 1s in the truth table. Truth table A table that shows all the input-output possibilities of a logic circuit. 52

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