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SiP TAP JTAG for SiP

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					               SiP-TAP : JTAG implementation for SiP designs
                                          Frans de Jong, Alex Biewenga
                   Philips Research, High Tech Campus 5, 5656 AE Eindhoven, The Netherlands
                             Frans.de.Jong@Philips.com, Alex.Biewenga@Philips.com

ABSTRACT.                                                      The second part is the documentation that belongs to a
The standard IEEE 1149.1’JTAG’ solution for test               SiP that must describe the two identities: A micro PCB
poses a challenge when used for System-in-a-                   for the supplier and a single device for the customer.
Package (SiP). Like MCM, a SiP brings an                       To get the proper answer on the first part we have to
additional hierarchy laye rin the JTAG structure of a          scrutinize the IEEE standard on a few points as listed
board design.                                                  here:
Without additional action, the JTAG implementation             An IEEE 1149.1 compliant device
applied on a SiP containing multiple digital dies will          1. Can have only one Test Access Port (TAP).
not conform to the IEEE standard when applied at                2. Shall have a BYPASS register with a length of
board level. This presentation discusses the problem               exactly one bit.
and shows a new solution. The implementation is low             3. Can have an optional ID register with a length of
cost and can be a general addition to the Test                     exactly 32 bits.
Acccess Port of all dies using the standard. The                4. Can have an optional TRST* pin that, when
consequences for SiP test preparation, software flow               activated, resets all TAP controller logic to the
and actual usage on a real SiP are discussed as well.              defined ‘test logic reset’ state (TLR).
                                                                5. Shall have a BSDL file describing the
1. INTRODUCTION.                                                   implementation details beyond the fixed standard
                                                                   issues.
In the SiP designs of today often more than one
digital IC (die) is used. This results in a miniature          3. KNOWN SOLUTIONS
printed circuit board (PCB) type of design. For the
use of such a SiP in a final application, our customers        Earlier work is extensively described by Jarwala [2] at
require the device to be compliant with the IEEE               the ITC 1994. This work mainly targets the issues
1149.1 standard [1].                                           around the BYPASS and ID register length for MCMs.
Testing of digital SiPs is not the same as testing a           More specific solutions were created by designers, for
PCB. It is not difficult to see that during application        the MCMs that were made in the consumer and mobile
debug all options for access will be needed, which             telecoms range. Essentially, these designs incorporated
includes the standardized Test Access Port (TAP). A            parts of the methods as mentioned above. Now with
second thought is equally important: The outsourced            SiP designs becoming a mainstream issue (many
volume production uses standardized test equipment,            designs, lower margin and even less time-to-volume),
also relying on the standard TAP.                              more attention is given to a generic solution. Our
                                                               proposed solution is: The SiP-TAP.
However, if the boundary scan implementation on the
SiP is implemented the same way as usually done on             4. THE SIP-TAP SOLUTION
a small PCB, the resulting SiP will NOT comply to
the IEEE 1149.1 standard. This is already known [2]            The actual implementation of the proposed solution is,
and discussed, but so far the solutions described were         as to be expected, a compromise between a simple and
not yet complete. Also the economics for creating a            a cost effective solution. Also focus has been on
SiP play a more important role than years ago, when            flawless functioning more than covering all wishes.
MCM type of designs were still ‘specials’. For this
reason, we will present a solution that is more                The SiP-TAP requirements
complete from a boundary scan point of view. The
economics for SiPs targeting the consumer and                  From the former discussions, requirements are
communications market segments (typically low cost             distilled. These form the guidelines for the SiP-TAP
and small size) are taken into account and discussed.          design. The list of our requirements is as follows:
Most importantly, an implementation is proposed and              1. The resulting SiP is conformant to IEEE 1149.1
exercised in detail, which lends itself for general                  Standard.
implementation and standardization as well.                      2. A resulting Single die should also be compliant
                                                                     when packaged as a standalone IC.
2. WHAT IS THE REAL PROBLEM?                                     3. The implementation should be usable as a general
                                                                     solution and fit for standardization.
The problem falls apart in two distinct areas. The first         4. The solution must be cheap and simple.
part is the conformance to the IEEE 1149.1 standard.




                                                           1
 5. The method should even be compatible with a                                                                                                                                                   Die
    mix of new and old (= not adapted but standard
    JTAG devices from legacy and third-parties)                                                                                                                 Internal
    devices, including the solution for TRST* pins.
                                                                                                                                                           Core Logic
 6. The solution potentially enables debugging for
    separate dies in a SiP.
 7. The documentation issue is brought down to a                                                                                  STDI
                                                                                                                                                                                                 TDO
    single BSDL file for the customers.                                                                                                                                                                        TDO
                                                                                                                                   TDI
                                                                                                                                                                   BYPASS

                                                                                                                                                                ID Register

The SiP-TAP design                                                                                                                                          Instruction Reg

                                                                                                                                               SiP-TAP Controller
                                                                                                                                               SiP-TAP Controller
The major part of the proposed solution is a                                                                                                    TMS TCK
                                                                                                                                                TMS TCK                                  POR
                                                                                                                                                                                          POR

secondary input, called STDI on every die that has a
TAP controller. This STDI is multiplexed with the                                                                    TMS
                                                                                                                     TCK
                                                                                                                                                                                                POR-output /TRST*

TDI on the TDI input of the TAP controller.
Having this extra STDI on every die allows us to
                                                                                                                     Figure 2 The TAP modifications for SiP-TAP
connect the STDI pads of all dies together with the
SiP’s top-level TDI. Selecting the STDI input with                                                         As a first rule we define that instructions always reach
the BYPASS instruction simply makes that only the                                                          all dies through the normal TDI-TDO path. This means
last die in the chain will have it’s one bit BYPASS                                                        that the SiP instruction register is always a complete
register connected between TDI and TDO of the SiP.                                                         concatenation of all instruction registers of all dies in
All bypass registers are selected, but only the last one                                                   the chain.
becomes connected. A similar action holds for the                                                          The data register shift will go through either TDI or
IDCODE instruction.                                                                                        STDI depending on the instruction that is active for
                                                                                                           each individual die.




                                                                                                                                                                                    S iP


                                                         D ie 1                                                   D ie 2                                                        D ie 3




                                   In te rn a l                                             In te rn a l                                                 In te rn a l

                                  C o re                                                   C o re                                                       C o re
                                  L o g ic                                                 L o g ic                                                     L o g ic


               S TD I                                                    STD I                                                      S TD I
        TD I                                                      TD O                                                     TD O                                                          TD O
                                                                                                                                                                                                        TD O
                TD I                                                      TD I                                                       TD I
                                      B YPA SS                                                 BYPASS                                                       BYPASS


                                  ID R e g is te r                                          ID R e g is te r                                            ID R e g is te r

                                In s tru c tio n R e g                                   In s tru c tio n R e g                                       In s tru c t io n R e g


                        S iP -T A P C o n t ro lle r                             S iP -T A P C o n t ro lle r                                S iP -T A P C o n t ro lle r
                        TM S TC K                         POR                    TM S TC K                        POR                        TM S TCK                            POR


       TM S
       TC K




                                                            Figure 1 Connecting SiP-TAP dies on a SiP




                                                                                              2
                                                                                                                                                    Special attention is required when merging ports of
                                                                                                                                                    different types (e.g. buffer with linkage). To be
                                                                                                                                    SiP
                                                                                                                                                    discussed in more detail in final version.
                                    Die 1                                       Die 2                                       Die 3




                    Internal                                    Internal                                    Internal
                                                                                                                                                    6. THE JTAG INFRASTRUCTURE TEST.
                   Core                                         Core                                        Core
                   Logic                                        Logic                                       Logic

                                                                                                                                                    When first samples come in, access is basically
                                                                                                                                                    electronic only. Our first action is to check the JTAG
                                                  STDI                                        STDI
 TDI                                        TDO                                         TDO                                         TDO
                                                                                                                                          TDO
       TDI                                         TDI                                         TDI
                      BYPASS

                    ID Register
                                                                   BYPASS

                                                                ID Register
                                                                                                               BYPASS

                                                                                                            ID Register
                                                                                                                                                    test architecture. This brings us back to the issue of
                  Instruction Reg                             Instruction Reg                             Instruction Reg
                                                                                                                                                    ‘Infrastructure testing’ [10].
              TAP Controller                             SiP-TAP Controller                          SiP-TAP Controller
             TMS TCK (TRST*)                             TMS TCK                POR                  TMS TCK                POR                     The infrastructure-testing scheme becomes slightly
TMS
TCK                                                                                                                                                 more elaborate because of the SiP-TAP additions.
                                                                                    NC

                                                                                                                                                    The following test steps are generated, that are
                                                                                                                                                    effective tests for diagnosis. The volume production
                                                                                                                                                    version could be slightly optimized. The steps:
                                  Figure 3 TRSTn Solution                                                                                           Step 1: Explicit reset.
                                                                                                                                                    Step 2: Instruction register shift.
One remark about this POR-output pad: It replaces                                                                                                   Step 3: Data register shift.
the TRST* pad but serves the same functionality                                                                                                     Step 4: Selective BYPASS instructions(design
inside the SiP. For this reason, the pad is not to be                                                                                               dependent)
mixed with a functional reset or other function of the
mission logic of the die. The input side of this pad                                                                                                7. THE SOFTWARE IMPLICATIONS
can still have a TRST* function.
                                                                                                                                                    The SiP-TAP scheme requires supporting software for
The IDCODE discussion.                                                                                                                              correct implementation and to automate the design and
…                                                                                                                                                   implementation process. For this we need the following
                                                                                                                                                    tools:
5. THE BSDL FILE.                                                                                                                                   A. Die level tools.
                                                                                                                                                    B. SiP level tools.
When creating a SiP, the BSDL file requires some
extra attention.                                                                                                                                    8. CONCLUSIONS AND FURTHER WORK
If we are creating and selling the SiP as a mini PCB,
a BSDL file is required for each die. Furthermore a                                                                                                  1. The SiP-TAP realizes full IEEE Std 1149.1
top-level netlist is required. The drawbacks of this                                                                                                    compliancy for SiP devices.
approach are:                                                                                                                                        2. The SiP-TAP concept solves the hierarchical
  1. Not user friendly (customer point of view)                                                                                                         issue of SiPs using JTAG.
  2. Hard to manage in the field (paragraph 2)                                                                                                       3. The SiP-TAP concept supports combinations with
                                                                                                                                                        legacy dies and or third-party JTAG devices.
On the other hand, when sold as a single device, a                                                                                                   4. The software to support the SiP-TAP concept
single BSDL file is needed to comply with the                                                                                                           shows the impact on the entire design flow.
standard. This results in more user-friendly approach                                                                                                5. The creation of the SiP level BSDL file can be
and is easier to manage.                                                                                                                                partially automated. Design specific manual
                                                                                                                                                        adaptation remains needed.
Basic bsdl merge issues
In order to create a SiP level BSDL file, the BSDL                                                                                                  Further study is needed for enhanced support of
files of the individual dies need to be merged in to                                                                                                debugging of SiPs in general.
one BSDL file. The two main areas of attention are:                                                                                                 The SiP-TAP concept is already implemented in two
  • Merging ports and cells                                                                                                                         designs and validated to be correct.
  • Merging registers and instructions.
In the following paragraphs the main issues will be                                                                                                 REFERENCES
highlighted.
                                                                                                                                                    [1] IEEE Computer Society. "IEEE Standard Test
Merging cells, ports and pins                                                                                                                       Access Port and Boundary-Scan architecture -
In the SiP BSDL file all the boundary scan register                                                                                                 IEEE Std. 1149.1-2001", IEEE, New York, 2001.
(BSR) cells connected to the SiP package pins are
listed unmodified. All other cells become internal                                                                                                  [2] N. Jarwala, ‘Designing “dual Personality” IEEE
cells. Care is required when defining safe-values for                                                                                               1149.1 Compliant Multi-Chip Modules’, IEEE
these internal cells because they may be connected to                                                                                               International Test Conference 1994, pp.446-455.
other dies in the SiP package or may control a mix of
cells (internal cells and cells connected to the                                                                                                    [3] D. Bhavsar, ‘An Architecture for Extending the
package).                                                                                                                                           IEEE Standard 1149.1 Test Access Port to System




                                                                                                                                                3
Backplanes’, IEEE International Test Conference
1991, pp.768-776.

[4] L. Whetsel, ‘A proposed Method of Accessing
1149.1 in a Backplane Environment’, IEEE
International Test Conference 1992, pp.206-216.

[5] N. Jarwala, C.W. Yau, ‘Achieving Board-level
BIST Using the Boundary Scan Master’, IEEE
International Test Conference 1991, pp. 649-658.

[6] National Semiconductor Corp., ‘SCANPSC110F
SCAN Bridge Hierarchical and Multidrop
Addressable JTAG Port (IEEE1149.1 System Test
Support)’, Data sheet DS100327, www.national.com.

[7] National Semiconductor Corp., ‘SCANSTA111
Enhanced SCAN bridge Multidrop Addressable IEEE
1149.1 (JTAG) Port’, Data sheet DS101245,
www.national.com.

[8] Texas Instruments, ‘SN74ACT8997 Scan Path
Linkers With 4-Bit Identification Buses Scan-
Controlled TAP Concatenators’, Data sheet
SCAS157D, www.ti.com.

[9] S. C. Hilla, ‘Boundary Scan Testing for
Multichip Modules’, IEEE International Test
Conference 1992, pp 224-231.

[10] de Jong, F.; van der Heyden, F. ,‘Testing the
Integrity of the Boundary Scan Test Infrastructure’,
IEEE International Test Conference 1991, pp 106-
112.

[11] L. van de Logt, F. van der Heyden, T. Waayers,
‘An Extension to JTAG for At-Speed Debug on a
System’, IEEE International Test Conference 2003,
pp. 123-130.




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