VIEWS: 52 PAGES: 74 POSTED ON: 4/4/2011 Public Domain
MOSFETs ECE 663 A little bit of history.. ECE 663 Operation of a transistor VSG > 0 n type operation VSG Gate VSD Insulator Source Channel Drain More electrons Substrate Positive gate bias attracts electrons into channel Channel now becomes more conductive Operation of a transistor VSG Gate VSD Insulator Source Channel Drain Substrate Transistor turns on at high gate voltage Transistor current saturates at high drain bias Start with a MOS capacitor VSG Gate VSD Insulator Source Channel Drain Substrate MIS Diode (MOS capacitor) – Ideal ECE 663 Questions What is the MOS capacitance? QS(yS) W What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG) Ideal MIS Diode n-type, Vappl=0 Assume Flat-band at equilibrium qfS EC EF Ei EV ECE 663 Ideal MIS Diode n-type, Vappl=0 Eg fms fm yB 0 2q ECE 663 Ideal MIS Diode p-type, Vappl=0 ECE 663 Ideal MIS Diode p-type, Vappl=0 Eg fms fm yB 0 2q ECE 663 Accumulation Pulling in majority carriers at surface ECE 663 But this increases the barrier for current flow !! n+ p n+ ECE 663 Depletion ECE 663 Inversion yB Need CB to dip below EF. Once below by yB, minority carrier density trumps the intrinsic density. Once below by 2yB, it trumps the major carrier density (doping) ! ECE 663 Sometimes maths can help… ECE 663 P-type semiconductor Vappl0 Convention for p-type: y positive if bands bend down ECE 663 Ideal MIS diode – p-type ( Ei' EF ) / kT np ni e ni e ( E qyE i F ) / kT np0e qy / kT np0ey CB moves towards EF if y > 0 n increases p p p p 0 e qy / kT p p 0e y VB moves away from EF if y > 0 p decreases q kT ECE 663 Ideal MIS diode – p-type At the semiconductor surface, y = ys ns np0ey s ps pp0e y s ECE 663 Surface carrier concentration ys ys ns np0e ps pp0e EC • ys < 0 - accumulation of holes EF • ys =0 - flat band • yB> ys >0 – depletion of holes • ys =yB - intrinsic concentration ns=ps=ni • ys > yB – Inversion (more electrons than holes) ECE 663 Want to find y, E-field, Capacitance • Solve Poisson’s equation to get E field, potential based on charge density distribution(one dimension) d E E / k 0 / s 1 D dx dy E dx d 2y 2 / s dx ( x ) q(ND N A p p n p ) ECE 663 • Away from the surface, = 0 ND N A n p 0 p p 0 • and p p n p p p 0e y n p 0e y d 2y p p 0 (e y 1) n p 0 (e y 1) q dx 2 s ECE 663 Solve Poisson’s equation: d 2y p p 0 (e y 1) n p 0 (e y 1) q dx 2 s E = -dy/dx d2y/dx2 = -dE/dx = (dE/dy).(-dy/dx) = EdE/dy d 2y EdE/dy 2 p p 0 (e y 1) n p 0 (e y 1) q dx s ECE 663 Solve Poisson’s equation: • Do the integral: • LHS: x x2 dy xdx x 0 2 dx • RHS: x x x e dx, dx 0 0 • Get expression for E field (dy/dx): kT qp p 0 y 2 e y 1 e y 1 np 0 y E 2 q 2 s field pp0 ECE 663 Define: kT s s Debye Length LD pp 0q 2 qp p 0 1 n y, p 0 e y y 1 p 0 e y y 1 2 n F pp0 pp0 Then: E>0 2kT np0 y>0 Efield F y, qLD pp 0 E<0 + for y > 0 and – for y < 0 y<0 ECE 663 Use Gauss’ Law to find surface charge per unit area 2kT n Qs s ES y s , p 0 F qLD pp0 1 2kT y e y s 1 e y s 1 2 np 0 y Qs S s qLD pp0 ECE 663 Accumulation to depletion to strong Inversion • For negative y, first term in F dominates – exponential • For small positive y, second term in F dominates - y n p 0 e y • As y gets larger, 1 second exponential gets big pp0 yB = (kT/q)ln(NA/ni) = (1/)ln(pp0/√pp0np0) (np0/pp0) = e-2yB yS > 2yB ECE 663 Questions What is the MOS capacitance? QS(yS) What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG) Charges, fields, and potentials • Charge on metal = induced surface charge in semiconductor • No charge/current in insulator (ideal) metal insul semiconductor depletion inversion QM Qn qN AW QS ECE 663 Charges, fields, and potentials Electric Field Electrostatic Potential ECE 663 Depletion Region Electric Field Electrostatic Potential kT qp p 0 y 2 e y 1 e y 1 np 0 y E 2 q 2 s field pp0 ECE 663 Depletion Region Electric Field Electrostatic Potential y = ys(1-x/W)2 Wmax = 2s(2yB)/qNA yB = (kT/q)ln(NA/ni) ECE 663 Questions What is the MOS capacitance? QS(yS) What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG) Couldn’t we just solve this exactly? Exact Solution U = y US = yS UB = yB dy/dx = -(2kT/qLD)F(yB,np0/pp0) U dU/F(U) = x/L D US F(U) = [eUB(e-U-1+U)-e-UB (eU-1-U)]1/2 Exact Solution = qni[eUB(e-U-1) – e-UB(eU-1)] US dU’/F(U’,U ) = x/L B D U F(U,UB) = [eUB(e-U-1+U) + e-UB (eU-1-U)]1/2 Exact Solution NA = 1.67 x 1015 Qinv ~ 1/(x+x0)a x0 ~ LD . factor Questions What is the MOS capacitance? QS(yS) What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG) Threshold Voltage for Strong Inversion • Total voltage across MOS structure= voltage across dielectric plus ys QS VT (strong _ inversion) Vi y S 2y B Ci 2 s y s (inv ) QS (SI ) qN AWmax qN A 2 s qN A (2y B ) qN A 2 s qN A (2y B ) VT 2y B Ci ECE 663 Notice Boundary Condition !! oxVi/tox = sys/(W/2) Before Inversion After inversion there is a discontinuity in D due to surface Qinv Vox (at threshold) = s(2yB)/(Wmax/2)Ci = 2 s qN A (2y B ) VT 2y B Ci ECE 663 Local Potential vs Gate voltage VG = Vfb + ys + (kstox/kox)√(2kTNA/0ks)[ys + eys-2yB)]1/2 yox ys Initially, all voltage drops across channel (blue curve). Above threshold, channel potential stays pinned to 2yB, varying only logarithmically, so that most of the gate voltage drops across the oxide (red curve). Look at Effective charge width ~Wdm/2 ~tinv Initially, a fast increasing channel potential drops across increasing depletion width Eventually, a constant potential drops across a decreasing inversion layer width, so field keeps increasing and thus matches increasing field in oxide Questions What is the MOS capacitance? QS(yS) What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG) Charge vs Local Potential Qs ≈ √(20kskTNA)[ys + eys-2yB)]1/2 Beyond threshold, all charge goes to inversion layer How do we get the curvatures? Add other terms and keep Leading term EXACT Inversion Charge vs Gate voltage Q ~ eys-2yB), ys- 2yB ~ log(VG-VT) Exponent of a logarithm gives a linear variation of Qinv with VG Qinv = -Cox(VG-VT) Why Cox? Questions What is the MOS capacitance? QS(yS) What are the local conditions during inversion? yS,cr How does the potential vary with position? y(x) How much inversion charge is generated at the surface? Qinv(x,yS) Add in the oxide: how does the voltage divide? yS(VG), yox(VG) How much gate voltage do you need to invert the channel? VTH How much inversion charge is generated by the gate? Qinv(VG) What’s the overall C-V of the MOSFET? QS(VG) Capacitance y 1 y np0 1 e pp0 s e s QS CD S y 2LD np0 F y S , pp0 For ys=0 (Flat Band): x2 x3 Expand exponentials….. e 1 x ........ x 2! 3! S CD (flat _ band ) LD ECE 663 Capacitance of whole structure • Two capacitors in series: Ci - insulator CD - Depletion 1 1 1 Ci CD OR C C Ci CD Ci CD i Ci d ECE 663 Capacitance vs Voltage ECE 663 Flat Band Capacitance • Negative voltage = accumulation – C~Ci • Zero voltage – Flat Band V 0 y 0 C CFB i d LD 1 1 1 1 1 s d i LD s CFB Ci CD i s i s i d LD i CFB d LD i s ECE 663 CV • As voltage is increased, C goes through minimum (weak inversion) where dy/dQ is fairly flat • C will increase with onset of strong inversion • Capacitance is an AC measurement • Only increases when AC period long wrt minority carrier lifetime • At “high” frequency, carriers can’t keep up – don’t see increased capacitance with voltage • For Si MOS, “high” frequency = 10-100 Hz ECE 663 CV Curves – Ideal MOS Capacitor i C ' d Wmax min i s ECE 663 But how can we operate gate at today’s clock frequency (~ 2 GHz!) if we can’t generate minority carriers fast enough (> 100 Hz) ? ECE 663 MOScap vs MOSFET ECE 663 MOScap vs MOSFET Gate Gate Insulator Insulator Channel Source Channel Drain Substrate Substrate Minority carriers generated by Majority carriers pulled in RG, over minority carrier lifetime from contacts (fast !!) ~ 100ms So Cinv can be << Cox if fast gate Cinv = Cox switching (~ GHz) ECE 663 Example Metal-SiO2-Si • NA = 1017/cm3 • At room temp kT/q = 0.026V • ni = 9.65x109/cm3 • s = 11.9x1.85x10-14 F/cm N 4 s kT ln A 11.9 x8.85 x10 14 X 0.026 ln1017 9.65 x109 ni Wmax 2 1.6 x10 19 X 1017 q NA Wmax 10 5 cm 0.1mm ECE 663 Example Metal-SiO2-Si • d=50 nm thick oxide=10-5 cm • i=3.9x8.85x10-14 F/cm i 3.9 x8.85 x10 14 Ci 5 6.9 x10 7 F / cm 2 d 10 2kT N A 1017 y s (inv ) 2y B ln 2 x0.026 x ln 0.84Volts q ni 9.65 x109 i 3.9 x8.85 x10 14 C ' 9.1x10 8 F / cm 2 d Wmax 5 x10 7 3.9 11.910 5 min i s ' Cmin 0.13 Ci qN AWmax 1.6 x10 19 x1017 x10 5 VTH 2y B 7 y s (inv ) 0.23 0.84 1.07Volts Ci 6.9 x10 ECE 663 Real MIS Diode: Metal(poly)-Si-SiO2 MOS • Work functions of gate and semiconductor are NOT the same • Oxides are not perfect – Trapped, interface, mobile charges – Tunneling • All of these will effect the CV characteristic and threshold voltage ECE 663 Band bending due to work function difference VFB fms ECE 663 Work Function Difference • qfs=semiconductor work function = difference between vacuum and Fermi level • qfm=metal work function • qfms=(qfm- qfs) • For Al, qfm=4.1 eV • n+ polysilicon qfs=4.05 eV • p+ polysilicon qfs=5.05 eV • qfms varies over a wide range depending on doping ECE 663 ECE 663 SiO2-Si Interface Charges ECE 663 Standard nomenclature for Oxide charges: QM=Mobile charges (Na+/K+) – can cause unstable threshold shifts – cleanliness has eliminated this issue QOT=Oxide trapped charge – Can be anywhere in the oxide layer. Caused by broken Si-O bonds – caused by radiation damage e.g. alpha particles, plasma processes, hot carriers, EPROM ECE 663 QF= Fixed oxide charge – positive charge layer near (~2mm) Caused by incomplete oxidation of Si atoms(dangling bonds) Does not change with applied voltage QIT=Interface trapped charge. Similar in origin to QF but at interface. Can be pos, neg, or neutral. Traps e- and h during device operation. Density of QIT and QF usually correlated-similar mechanisms. Cure is H anneal at the end of the process. Oxide charges measured with C-V methods ECE 663 Effect of Fixed Oxide Charges ECE 663 ECE 663 Surface Recombination Lattice periodicity broken at surface/interface – mid-gap E levels Carriers generated-recombined per unit area ECE 663 Interface Trapped Charge - QIT • Surface states – R-G centers caused by disruption of lattice periodicity at surface • Trap levels distributed in band gap, with Fermi-type distributed: ND 1 ND 1 g D e ( E F ED ) / kT • Ionization and polarity will depend on applied voltage (above or below Fermi level • Frequency dependent capacitance due to surface recombination lifetime compared with measurement frequency • Effect is to distort CV curve depending on frequency • Can be passivated w/H anneal – 1010/cm2 in Si/SiO2 system ECE 663 Effect of Interface trapped charge on C-V curve ECE 663 a – ideal b – lateral shift – Q oxide, fms c – distorted by QIT ECE 663 Non-Ideal MOS capacitor C-V curves • Work function difference and oxide charges shift CV curve in voltage from ideal case • CV shift changes threshold voltage • Mobile ionic charges can change threshold voltage as a function of time – reliability problems • Interface Trapped Charge distorts CV curve – frequency dependent capacitance • Interface state density can be reduced by H annealing in Si-Si02 • Other gate insulator materials tend to have much higher interface state densities ECE 663 All of the above…. • For the three types of oxide charges the CV curve is shifted by the voltage on the capacitor Q/C 1 1 d VFBoxide _ ch arg e x( x )dx Ci d 0 • When work function differences and oxide charges are present, the flat band voltage shift is: Qf Qm Qot VFB fms Ci ECE 663 Some important equations in the inversion regime (Depth direction) VT = fms + 2yB + yox Gate Insulator yox = Qs/Cox Source Channel Drain Qs = qNAWdm Substrate Wdm = [2S(2yB)/qNA] x VT = fms + 2yB + ([4SyBqNA] - Qf + Qm + Qot)/Cox Qinv = Cox(VG - VT)