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TELECOMMUNICATIONS Dr. Hugh Blanton ENTC 4307/ENTC 5307 Dr. Blanton - ENTC 4307 - Phase Lock Loop 2 Phase-Locked Loops • A phase-locked loop (PLL) uses a feedback control circuit to allow a voltage- controlled oscillator to precisely track the phase of a stable reference oscillator, with the important feature that the output oscillator can be made to run at a multiple of the reference oscillator frequency. Dr. Blanton - ENTC 4307 - Phase Lock Loop 3 • Phase-locked loops are used • as FM demodulators, • in carrier recovery circuits, and • as frequency synthesizers for modulation and demodulation. • Phase-locked loops have very good frequency accuracy and phase noise characteristics, but suffer from the fact that settling times (between changes in frequency) can be long. Dr. Blanton - ENTC 4307 - Phase Lock Loop 4 • The basic circuit of a phase-locked loop consists of • a reference oscillator, • a phase detector • produces an output voltage proportional to the difference in phase of the inputs, • a loop amplifier and filter, • a voltage-controlled oscillator (VCO), and • operating at the desired output frequency • a frequency divider. Dr. Blanton - ENTC 4307 - Phase Lock Loop 5 • In operation, the output of the VCO is divided by N to match the frequency of the reference oscillator. • The phase detector produces a voltage proportional to the difference in phase of these two signals, and is used to make small corrections in the frequency of the VCO in order to align the phase of the VCO with that of the reference source. • The output of the phase-locked loop thus has a phase noise characteristic similar to that of the reference source, but operates at a higher frequency. • If a programmable frequency divider is used, it is possible to synthesize a large number of closely spaced frequencies with a relatively simple circuit. • This makes the phase-locked loop very useful for commercial wireless applications, especially those involving mu ltiple channels. Dr. Blanton - ENTC 4307 - Phase Lock Loop 6 • Phase-locked loops can be implemented in either digital or analog form, but we will only discuss analog PLLs because they are the only type capable of operating at RF and microwave frequencies. Dr. Blanton - ENTC 4307 - Phase Lock Loop 7 • There are several characteristics of phase- locked loops that are important in practice. • The capture range is the range of input frequency for which the loop can acquire locking. • The lock range is the input frequency range over which the loop will remain locked; • this is typically larger than the capture range. • The settling time is the time required for the loop to lock on to a new frequency. Dr. Blanton - ENTC 4307 - Phase Lock Loop 8 Practical Synthesizer Circuits • The AMPS cellular system requires a local oscillator in the 800 MHz band to receive one of several hundred voice channels having 30 kHz spacing. • Using a standard phase locked loop would require a reference source operating at 30 kHz and a VCO operating near 870 MHz, with a programmable divider providing a division ratio of more than 24,000. • This would be impractical because of the large number of addresses required as well as the high frequency at which the divider would have to operate. Dr. Blanton - ENTC 4307 - Phase Lock Loop 9 • Instead, a phase-locked loop supplemented with a mixer and frequency multiplier is used Dr. Blanton - ENTC 4307 - Phase Lock Loop 10 • In this synthesizer the VCO operates at the frequency fo, which ranges from 217.5 to 222.5 MHz. • The VCO output is frequency multiplied by four to achieve the desired synthesizer output in the range of 870 MHz. • Part of the VCO output is mixed with a fixed reference crystal oscillator at f1 = 228.02250 MHz. • The filtered difference frequency of 6 to 11 MHz is low enough to be digitally divided with an inexpensive programmable counter. • The division ratio is selected with a 10-bit address to lie between 737 < N < 1402, according to the desired channel. Dr. Blanton - ENTC 4307 - Phase Lock Loop 11 • The output of the divider is compared to a stable 7.5 kHz oscillator, f2 , and the phase error is used to control the VCO. • When the loop is in lock, the output frequency is fout = 4(f1 f2). • Thus the output can be stepped in increments of 4 f2 = 30 kHz. • The stability of the output is set by the stability of the reference sources f1 and f2. Dr. Blanton - ENTC 4307 - Phase Lock Loop 12 • If it is desired to produce an output frequency of fout = 870.180 MHz. for example, then we solve the equation 870.180 MHz = 4(f1 N f2) = 4[228.02250 N(0.0075)] • This yields N = 1397. which is the required setting of the programmable divider. Dr. Blanton - ENTC 4307 - Phase Lock Loop 13 Phase Detectors • A phase detector provides an output voltage that is dependent on the phase difference between two input signals. • Two input signals of nominally the same frequency (wo), but different phases (q1 and q2), are applied to the input ports of a 90 hybrid coupler. Dr. Blanton - ENTC 4307 - Phase Lock Loop 14 • The output voltages developed across the mixer diodes can be written as w w v1 (t ) cos( ot q 1 ) cos( ot q 2 90 ) w cos( ot q 1 ) sin(w ot q 2 ) w w v2 (t ) cos( ot q 2 ) cos( ot q 1 90 ) w cos( ot q 2 ) sin(w ot q 1 ) Dr. Blanton - ENTC 4307 - Phase Lock Loop 15 • If we assume a square-law response for the mixer diodes, and retain only the quadratic terms, the diode currents can be written as: i1 (t ) Kv1 (t ) 2 K cos2 (w ot q 1 ) 2 cos( ot q 1 ) sin(w ot q 2 ) sin 2 (w ot q 2 ) w i2 (t ) Kv2 (t ) 2 K cos2 (w ot q 2 ) 2 cos( ot q 2 ) sin(w ot q 1 ) sin 2 (w ot q 1 ) w • The negative sign of i2 accounts for the reversed diode polarity. Dr. Blanton - ENTC 4307 - Phase Lock Loop 16 • After combining the diode currents and low- pass filtering, the output voltage can be expressed as vo (t ) i1 (t ) i2 (t ) K d sin(q 1 q 2 ) K d (q 1 q 2 ) Dr. Blanton - ENTC 4307 - Phase Lock Loop 17 • This result shows that the output voltage of the phase detector is proportional to the sine of the difference in phase of the two input signals. • If this difference is small, then the sine function can he approximated by its argument, so that the phase detector output is proportional to the phase difference. • This is referred to as the linearized phase detector model. Dr. Blanton - ENTC 4307 - Phase Lock Loop 18 • The constant K, is the phase detector gain factor, and accounts for the diode square-law constants and current-to- voltage conversion. • It has dimensions of volts/radian. Dr. Blanton - ENTC 4307 - Phase Lock Loop 19 Transfer Function for the Voltage-Controlled Oscillator • We can assume that the VCO has an output frequency wo that is offset from its free- running frequency, wc,by an increment Dw: w o w c Dw w c K o vc • where the offset frequency is controlled by the control voltage vc applied to the VCO. • The constant Ko is the VCO gain factor, and has dimensions of HZ/V. Dr. Blanton - ENTC 4307 - Phase Lock Loop 20 • We define the phase of the offset frequency of the VCO as q o (t ) Dwt K o vct • Writing frequency as the time derivative of phase then gives dq o (t ) Dw K o vc dt Dr. Blanton - ENTC 4307 - Phase Lock Loop 21 • The integral yields the output phase in terms of the control voltage: t q o (t ) K o vc ( )d 0 • The Laplace transform yields: Ko o ( s) Vc ( s) s Dr. Blanton - ENTC 4307 - Phase Lock Loop 22 • Assume a reference input voltage given by: vi (t ) cos(w ot q i ) • where qi is the phase of the input waveform. Dr. Blanton - ENTC 4307 - Phase Lock Loop 23 • The output voltage of VCO can be written as vo (t ) cos(Nw ot q o ) • where qo is the phase of the output waveform. • Note that the output frequency is N times the input (reference) frequency, due to the use of the frequency divider in the loop feedback path. Dr. Blanton - ENTC 4307 - Phase Lock Loop 24 • The phase detector output voltage can be expressed in the Laplace transform domain as: vo (t ) K d (q 1 q 2 ) Vd ( s ) K d ( i ( s ) f ( s )) Dr. Blanton - ENTC 4307 - Phase Lock Loop 25 • Since the divider divides the frequency by N, and phase is the derivative of frequency, the phase will also be divided by N. • So the relation between the feedback phase qf and the output phase, qo, is 1 f ( s) o ( s) N Dr. Blanton - ENTC 4307 - Phase Lock Loop 26 • The control voltage, Vc(s), applied to the VCO is Vc ( s ) H ( s )Vd ( s ) Dr. Blanton - ENTC 4307 - Phase Lock Loop 27 • The transfer function is: Ko Ko Vc ( s ) Vd ( s ) H ( s ) o (s) s s i ( s ) Vd ( s ) ( s ) Vd ( s ) o ( s ) f Kd Kd N Ko Vd ( s) H ( s) o ( s) s K o K d H (s) i ( s) Ko Vd ( s) H ( s) s K o K d H ( s) Vd ( s) s N Kd N Dr. Blanton - ENTC 4307 - Phase Lock Loop 28 N K o K d H ( s) o ( s) K o K d H ( s) N i ( s) s K o K d H ( s) s K o K d H ( s) N N N K o K d H ( s) o ( s) N NKH ( s) i ( s) s K o K d H ( s) s KH ( s) N Ko Kd K N Dr. Blanton - ENTC 4307 - Phase Lock Loop 29 NKH ( s ) o (s) i (s) s KH ( s ) Dr. Blanton - ENTC 4307 - Phase Lock Loop 30 • The VCO control voltage is then found as sK d H ( s) Vc ( s ) i ( s) s KH ( s) • The loop phase error is: s ( s) i ( s ) s KH (s) Dr. Blanton - ENTC 4307 - Phase Lock Loop 31 • Consider a step change Dw in the frequency, so that the input voltage is: vi (t ) cos(w ot q i ) cos(w ot Dwt ) • The input phase function is q i (t ) DwtU (t ) • where U(t) is the unit step function. Dr. Blanton - ENTC 4307 - Phase Lock Loop 32 • The Laplace transform is: D w 1 D w i ( s) 2 s s s Dr. Blanton - ENTC 4307 - Phase Lock Loop 33 First-Order Loop • First consider the simplest case of a PLL with no loop filter. • Then H(s) = 1, and the VCO control voltage for a step change in frequency, reduces to sK d H ( s ) sK d H ( s) Dw Dw K d Vc ( s ) i (s) s KH ( s) s KH ( s ) s 2 s s K DwK d DwK d 1 1 Vc ( s ) s s K K s sK • due to partial fraction expansion. Dr. Blanton - ENTC 4307 - Phase Lock Loop 34 • Since there is a maximum of one pole, the system is a first-order loop. L -1 c (s) vc (t ) L -1 V DwK d 1 1 DwK d 1 e Kt U (t ) K s s K K • This result shows how the VCO control voltage varies in response to a step change in the input frequency. • At t = 0, vc(t) = 0. • The output frequency is w0 = wc,the free-running VCO frequency. • In the limit as t→, the control voltage exponentially converges to Dw K d Dw N vc (t ) K Kd Dr. Blanton - ENTC 4307 - Phase Lock Loop 35 • Then the output voltage of the VCO is, after locking, given by: vo (t ) cos(Nw ot q o ) cos N (w o Dw )t • which shows that the output frequency has tracked the input step in frequency, and is multiplied by N. Dr. Blanton - ENTC 4307 - Phase Lock Loop 36 • The time required for the output of the PLL to respond to the step change in input frequency is called the acquisition time. Dr. Blanton - ENTC 4307 - Phase Lock Loop 37 Dr. Blanton - ENTC 4307 - Phase Lock Loop 38 Dr. Blanton - ENTC 4307 - Phase Lock Loop 39