SIMPLE TEST BENCH USING VHDL
TO THE DEPARTMENT OF
ELECTRONICS AND COMMUNICATIONS ENGINEERING
NATIONAL INSTITUTE OF SCIENCE & TECHNOLOGY
A Simple test bench is written for a design to observe the output for different possible
combination of input. A Test bench can be written using various hardware description
languages like VHDL(VHSIC HDL or very-high-speed-integrated-circuit hardware
description language) or Verilog HDL. Test bench can also be used to verify the
functional correctness as well as to observe the system response to various combinations
of input. With the complexity of design increasing day by day, the use of test bench is
highly essential in order to make the design functionally correct at the design level itself
Here a simple test bench for 4:1 MUX is written using VHDL and the software used is
XILINX ISE 9.2i.
I thank Mr. Sukanta Kumar Swain , NIST, for his valuable guidance and support
throughout the duration of the VLSI lab.
I would also like to thank Mr. Raghu Nandan Swain & Mr. Asisa Kumar Panigrahi,
NIST for having been the ultimate source of inspiration and moral support.
I would also like to extend my heartfelt gratitude to my parents and friends for their
unflinching support and help in the completion of the course.
TABLE OF CONTENTS
TEST BENCH STRUCTURE…………………………………………………………6
4.XILINX ISE 9.2I… ………………………………………………………….…….10
When modeling systems with VHDL, a comprehensive method of testing must be
developed which will test the aspects of the design completely. VHDL models are tested
using an enclosing model called a Test Bench. A VHDL test bench can be defined as an
executable VHDL model which instantiates a model under test (MUT) and provides the
capability to drive the MUT with a set of test vectors and compare the response with the
expected response. The test bench is at the top level in the model hierarchy. It is the
entity that is simulated when testing a model.. At higher levels of abstraction, the primary
purposes of simulation are to provide executable specifications and to verify the
functionality of the design. In addition, at lower levels of abstraction, simulation is used
to verify that a set of tests will detect common hardware faults. This is accomplished by
exercising the design using a number of stressing test cases. Thus Test benches provide
the user with the capability to test the MUT thoroughly through simulation
2. TEST BENCH
A test bench is a model that is used to exercise and verify the correctness of a hardware
model. The expressive power of the VHDL language provides us with the capability of
writing test bench models in the same language. A test bench has three main purposes:
1. To generate stimulus for simulation(waveforms)
2. To apply this stimulus to the entity under test and collect the output responses
3. To compare output responses with expected values.
Stimulus is automatically applied to the entity under test by instantiating the entity in the
test bench model and then specifying the appropriate interface signals. Test bench is a
part of the circuits specification. Stimulus and Response can be obtained from the
testbench. Tests should be developed to verify the functionality of the system completely.
This includes tests of components of a design as well as tests for the design as a whole.
A VHDL test bench typically consists of an architecture body containing an
instance of the component to be tested and processes that generate sequences of values on
signals connected to the component instance. The architecture body may also contain
processes that verify that the component instance produces the expected values on the
output signals. Alternatively, we may use the monitoring facilities of the simulator to
observe the outputs visually.
A Test Bench should be reusable without difficult modifications. The structure of the TB
should be simple enough so that other people understand its behavior. A Good test bench
propagates all the generics and constants into DUT.
Test Bench Structures:
TB should be reusable without difficult modifications.The structure of the TB should be
simple enough so that otherpeople understand its behaviour.Good test bench propagates
all the generics and constants intoDUT.The components that will be there in a vhdl test
Test inputs: A sequence of test inputs are applied over time to the DUT, with a
predefined time value (or external triggering event) defined as the condition for
Process statement: To apply stimulus to the design, your testbench you will
probably be written using one or more sequential process. A process that is
intended for testing will normally have no sensitivity list. Instead it will have a
series of signal assignments wait statements. The wait statements provide a
specific amount of delay between each new combination of inputs for the DUT to
stabilize between the assignments of test inputs. This process statement will be
used to apply a sequence of input values (the actual stimulus) to a low-level
circuit and (if desired) check the state ot that circuit's outputs at various points in
Transport statements: There are two ways to write stimulus vectors: using wait
statement (as just explained) or using transport statements. Transport-based test
benches are smaller and easier to read than wait-based test-benches, but wait-
based test benches are easier to understand when single stepped through
simulation to debug it.
Assert statements: Assert statements are used to verify that the DUT is operating
correctly for each combination of inputs. In case of fallacy operation, the text you
have specified in the optional report statement clause is displayed on your
VHDL stands for Very High Speed Integrated Circuit Hardware Description Language.
Department of Defense of US developed this language; in 1983.VHDL is the most
robust, versatile and complete language. This is a language used by Electronics Designer
for designing modeling and synthesizing of semi-custom Integrated Circuit. This is the
only language of IEEE standard. The first version of 1076 standard was approved in
1993.The initial version of VHDL included a wide range of data type,including
numerical(integer and real),logical(bit and boolean),character and time plus arrays of bit
called bit_vector and of character called string.
VHDL is a fairly general-purpose language although it requires a simulator on which to
run the code. It can read and write files on the host computer. So o VHDL program can
be written that generates another VHDL program to be incorporated in the design being
developed. Because of this general purpose nature it is possible to use VHDL to write a
testbench that verifies the functionality of the design using files on the host computer to
define stimuli, interacts with the user and compares results with those expected. The key
advantage of VHDL when used for system design is that it allows the behavior of the
required system to be described (modelled) and verified (simulated) before synthesis
tools translate the design into real hardware (gates and wires).
3.1 Working Environment of VHDL
All designs are done in a user-defined library. The default library is work
The most commonly used library is IEEE library that needs to be added before
designing any system.
One library consists of number of packages. While using one library in another,
we must write which package of the library is to be used.
When component, function, procedures are defined in a package then their
descriptions are generally defined in body of the package.
3.2 Important Processes Involved in VHDL Designing
Simulation is the process by which when a system is designed, it is functionality
is first verified or checked.
Everything, which is designed, has to be simulated to see its functionality, if not
satisfied modifications are made and again simulated. The functionally is checked
using timing diagrams.
Literally “synthesis” means process of integration to get an entity. Here it means
realization of the hardware, which can do the job what the software program has
All the synthesis is done using a device called CPLD or FPGA.
It is the process where we can virtually implement the program in device and can
find out various reports related to the design like, speed of the system, area
consumed by the system, power consumed by the system, the number of input and
output pad etc.
In this process the bit file generated is downloaded to the real physical
The design can be downloaded to devices like xillinx. XC4005 FPGA chip and
can test our design.
3.3 Design Entity
The design entry in VHDL consists of the following things:
In this description, the input and output of a system is specified.
An entity relation accomplishes it.
The entity declaration must have a name, input, output port and it should specify
what is type of input and output the system deals with.
This description consists the information “how the system works?”
The description is done with a declaration of architecture.
There can be more than one type of architecture to the same entity.
We can add previously designed units or systems to a new one.
Used to write the sequential statement.
The process statement appears inside an architecture body.
The basic statements like if, case, loop can only appear inside a process.
4. XILINX ISE 9.2i
The Xilinx ISE 9.2i system is a development tool that consists of an integrated set of
software and hardware tools to create simulate and implement digital designs in a FPGA
or CPLD. All the tools use a graphical user interface (GUI) that allows all programs to be
executed from toolbars, menus or icons.
Xilinx ISE 9.2i includes significant design improvements:
Xilinx FPGAs and CPLDs can be designed and verified quickly.
Design can be changed without any penalty, because device is software-
configured and software-programmed.
It supports Virtex-II Pro, Spartan3, Spartan3E, Spartan2, Spartan2E etc.
Incremental Design offering faster overall design completion when facing late-
arriving design changes.
PACE for quick and easy management of device pins and area layout. 
4.1 Creating a new project
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type <project name> in the Project Name field.
3. Enter or browse to a location (directory path) for the new project.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:
Product Category: All
Speed Grade: -5
Top-Level Source Type: HDL
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)
Preferred Language: Verilog (or VHDL)
Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
7. Click Next to proceed to the Create New Source window in the New Project Wizard.
At the end of next section ,the new project will be complete.
4.2 Creating an VHDL source:
Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name <file name>
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. In this window input and output signals are specified. Press next
7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete
the new source file template.
8. Click Next, then Next, then Finish.
4.3 Verifying Functionality of the design Using Test Bench
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a test
Create the test bench waveform as follows:
1. Create a new test bench source by selecting Project > New Source.
2. In the New Source Wizard, select VHDL Test Bench as the source type.
3. Click Next.
4. The Associated Source page shows that you are associating the test bench waveform
with the <source file name>. Click Next.
5. The Summary page shows that the source will be added to the project, and it displays
the source directory. Write the required test bench code.
6. Save the test bench file.
10. In the Sources window, select the Behavioral Simulation view to see that the test
bench waveform file is automatically added to your project.
4.4 Simulating Design Functionality:
Verify that the counter design functions as you expect by performing behavior simulation
1. Verify that Behavioral Simulation and test bench file are selected in the Sources
2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and
double-click the Simulate Behavioral Model process.
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
ENTITY mux_testbench IS
ARCHITECTURE behavior OF mux_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
d0 : IN std_logic;
d1 : IN std_logic;
d2 : IN std_logic;
d3 : IN std_logic;
s : IN std_logic_vector(1 downto 0);
y : OUT std_logic
signal d0 : std_logic := '0';
signal d1 : std_logic := '0';
signal d2 : std_logic := '0';
signal d3 : std_logic := '0';
signal s : std_logic_vector(1 downto 0) := (others => '0');
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- Instantiate the Unit Under Test (UUT)
uut: mux4_1 PORT MAP (
d0 => d0,
d1 => d1,
d2 => d2,
d3 => d3,
s => s,
y => y
-- Stimulus process
wait for 20ns;
wait for 20ns;
wait for 20ns;
wait for 20ns;
wait for 20ns;
The test bench code for 4:1 MUX was written and successfully simulated.Thus the
importance of test bench in vhdl language was learnt successfully.