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Xilinx Tutorial – Hardware Guide

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					CS141                                                          Xilinx Tutorial – Hardware




                      Xilinx Tutorial – Hardware Guide
                                    Lukasz Strozek

                                     October 5, 2005




1   Introduction

The XSA-50 is a system that lets you design your own circuits without the inconvenience
of wiring and obtaining all separate components. It’s an FPGA, which means that it is an
array of gates that can be reprogrammed by a computer to create any design you wish.
It’s a snazzy idea – XSA-50 can become anything from a simple AND gate to something
so complicated as a microprocessor. The only limit is your imagination (and the number of
gates, but we won’t worry about that yet).



2   Parts of the Board

FPGA. The Spartan-II FPGA contains 50,000 gates and can be dynamically programmed
to execute circuits that you build in the Xilinx Software.

CPLD manages configuration of the FPGA through the parallel port. This way, you can
use specialist software (we’re using Xilinx) to reprogram the board.

SDRAM. The 8 Mbytes of SDRAM stores data for the FPGA based designs. Connections
between the SRAM and the FPGA are made on the board. To facilitate the use of SDRAM,
use the SDRAM controller module in your projects. This module acts as an interface between
the FPGA and the SDRAM and makes the SDRAM appear to be SRAM. By using this
module, the user does not have to handle RAS, CAS, and refreshing the memory cells.
Right now, this paragraph probably doesn’t make any sense to you. Don’t worry about it –
we will go over it in the later weeks.

Parallel Port. The parallel port connection allows you to download programs to the board
with the help of the XSLOAD utility. You can also download test signals to a program on
the board by driving inputs via the associated parallel port pins and the utility XSPORT.
However, we make testing your programs easier by providing you with the CS141 Xilinx
Interface.

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CS141                                                            Xilinx Tutorial – Hardware



7-segment LED. The seven-segment display is a convenient way to view the output of your
programs. Each segment is connected to one of the pins of the FPGA. The LED segments are
active high, which means that when the appropriate pin output a high signal, the segment
will be turned on. LED will become your best friend, since it really is the only way to see
what your design is doing. Forget about gdb – right now you have one nibble (storing a
number between 0 and 15) of debugging information!

Programmable Oscillator. This oscillator makes it possible to have an internal clock.
This internal clock is connected to the clock input (GCK1) of the FPGA via pin 13. In
general, you will not need to use this clock as you will drive the timing of your programs via
the CS141 Xilinx Interface.

Flash. FPGA is volatile, which means that all programs stored on the board are lost when
power is disconnected and needs to be reprogrammed on every power up. If however, you
want to be able to use the board without having to download the program through the
parallel port each time you power up, you can store a program in the 128 Kbytes of Flash.
When you power up the board, the program in the Flash will be serially loaded into the
FPGA.

DIPswitch. A 4-position switch passes settings to the board and controls upper address
bits of Flash.



3   Bread Board Interface

XSA-50 Board has a breadboard interface that makes wiring to the XSA-50 pins easy. Pins
in the same row of the breadboard are connected and the long channel grooves across the
top and running in columns through the board are connected. The figure below shows the
internal connections in the board. A line means that all of the holes above the line are
connected together.

Orient the board so that the parallel socket is at the top. This way the LED is in the upright
position. Connect the parallel port cable to the XSA board. Now connect the adapter to
the power supply and plug the board in (the socket is just above the LCD display) and run
the program xs init.bat located on the Desktop (and available from the course website).
The demo will test your connection. You should see a line saying ”Your XSA-50 passed the
test!”. Then run xs demo.bat to see something interesting on the LED. Close the window
to end the demo.




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CS141                                                            Xilinx Tutorial – Hardware




If you board behaves funny, follow those couple of troubleshooting steps:


    • Disconnect the power supply and reconnect it.

    • Run xs init.bat to reset the board

    • If you’re still having trouble, make sure you connected the parallel cable properly

    • On rare occasions you may need to restart your computer.




4    The Logic Probe

Get used to using the logic probe. It is the fastest way to check the value of a signal on
one of Xilinx’ pins. Simply connect the logic probe’s black lead to GND and its red lead to
VCC. You should find these pins easily on the Xilinx board.

Set the probe’s mode to ”NORMAL” and ”TTL/LS”. Find the pin corresponding to bit 0
on the parallel port input. What’s the state of this bit? Now run CS 141 Interface and
toggle bit 0 (click on the button ’0’ or press the key ’0’) and see what’s happening to the

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CS141                                                            Xilinx Tutorial – Hardware



bit. Then move the slider to the second division. The field to the right of the slider should
say ’25Hz’ and the probe should make funky noises. If you want disco, change the mode of
the probe to ”PULSE” and enjoy! Finally, with the probe still in the ”PULSE” mode, touch
the probe with one hand and touch the table with another. What’s going on?



5   XSA-50 Signals

The XSA-50 can be controlled directly through the Parallel Port. This means that some of
Xilinx’ pins are mapped to the Parallel Port bits. The table below illustrates the mapping.

                            bit    6   5 4 3 2 1 0
                            pin   58   51 65 47 42 48 50


The most significant bit (bit 7) of the parallel port is also mapped, but it is known to reset
the FPGA, so we won’t use it. You will notice that The CS141 Interface has this bit
greyed out. You can re-enable it, but use this with caution as it may reset your board.

The LED is also mapped to XSA-50 pins. The diagram below illustrates the mapping.

                                            49
                                       57         46

                                            60

                                       62         39
                                            67         44


The DIP switches can also act as inputs. The switches are numbered DIP4, DIP3, DIP2 and
DIP1 and mapped to pins 56, 63, 64, 54, respectively. Moreover, you can use the pushbutton
(located in the lower left corner of the board), mapped to pin 93. Note that both the
pushbutton and the DIP switches are active-low – when the pushbutton is not pressed, it is
set to low, and when it’s pressed, it’s set to high. Similarly, if the DIP switches are in the
on position, they are set to low.

The Xilinx clock is mapped to pin 88. Its frequency is 50MHz.

If you need some free pins for input/output, you can use pins 77, 78, 79, 80, 83, 84, 85, 86
and 87.

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CS141                                                              Xilinx Tutorial – Hardware




6    CS 141 Interface

The most up-to-date version of the Xilinx Interface is version 2.11. This program lets you
control the seven parallel port input bits in an easy and intuitive way. It has a number of
features which make it a very powerful application.




    • To simply toggle some of the bits, either press one of the keys “0” through “6” on
      the keyboard, or click the respective button. You will see the current bit value change
      below the button.
    • At startup, the program’s “Immediate” option is checked. This means that every bit
      change re-sends all seven bits to the board. To change the state of many bits at once,
      and then batch upload all seven, uncheck the “Immediate” option. When you do that,
      nothing will get sent to the board until you press the “Send” button.
    • The reason why bit 7 is greyed out is that on XSA-50 it happens to map to the signal
      that resets the board (if set to 0). If you know what you are doing, you can check the
      “Extended” option and thus gain control of bit 7.
    • Pressing the “Increment” button (or, more simply, pressing the space bar) will treat
      bits 7 through 0 as one binary number, and increment the number by one. This is
      useful if your board interprets the bits 7 through 0 as one binary number.
    • To change only the least significant bit, check the “Only bit 0” option. From now on,
      pressing “Increment” will only change bit 0.
    • The “Reset” button sets all the bits to 0 (with the exception of bit 7, which stays at
      1, unless you check “Extended”, in which case bit 7 will also be zeroed
    • You can tell the application to automatically increment the bits. To do that, move
      the slider (initially in the “Halt” position) to the desired frequency. This is equivalent
      to pressing the “Increment” button that many times a second (in fact, the frequency
      displayed might not match the actual frequency due to the Windows process spawning
      latency).

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CS141                                                            Xilinx Tutorial – Hardware



  • The final feature is a very sophisticated batch uploading feature. Originally designed
    for uploading programs to the Xilinx board, it can be used to automate any data
    uploading process. When you press the “Load ANT” button, you will be asked to select
    a file with the .ant extension. This file should contain 8-bit hexadecimal numbers (each
    preceded by 0x), one per line, with possible whitespace. The pound sign is treated as
    a comment and everything after it until the end of the line will be ignored. The listing
    below shows an example of a valid ant file:

          # This is my first ANT file
          0x1b # This is just a comment
          0x34
          0xff
          # This is also a comment
          0x00

    When you load the file, some options will be greyed out – the application is ready
    to send the hexadecimal data over the parallel port. As before, you either press the
    “Strobe” button (or press the space bar) to send one chunk of data, or specify the
    speed with which to send the data automatically. The “Reset” button will switch the
    application back in its normal mode. When all data is transferred, the application will
    switch back to normal mode.
    If you press the “Send All” button, the application will send over all the data as fast
    as it can, and then switch back to normal mode.
    How is the data transferred? Well, because we can only send 7 bits at once, the
    application sends the hexadecimal data in 4-bit chunks. The chunks are sent as bits
    6 down to 3 (where bit 6 is the most significant of the four bits, and bit 3 – the least
    significant). The chunks of each number are sent in big endian order, with bits 7-4
    sent first, and then bits 3-0. The application sends the following control signals:

        1. First, bit 2 is set to 1 (all other bits set to 0)
        2. Then, with bit 2 still set, bits 6–3 are sent containing bits 7–4 of the first hex-
           adecimal number
        3. Bit 0 is set to 1, all other bits remain unchanged
        4. Buts 6–3 are sent containing bits 3–0 of the first hexadecimal number and bit 0
           is set back to 0
        5. Bit 0 is set to 1, all other bits remain unchanged
        6. Steps 2 through 5 are repeated for all other numbers in the ant file

    Effectively, bit 0 acts as a clock for synchronizing the incoming data.



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