FPGA and Xilinx ISE FPGA Basics

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					                                                                        FPGA Basics
                                                                     What is FPGA
                                                                        Field Programmable Gate Array
                                                                        An FPGA is a regular structure of logic cells (modules) and
                                                                        interconnect, which is under the designer’s complete control.
FPGA and Xilinx ISE                                                     An FPGA is really some programmable logic
                                                                        with a whole bunch of programmable wires

                                                                     How to program
                                                                            SRAM-Based, reprogrammable
                                                                        Non volatile
                                                                            Anti-fuse, one time programmable

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         Inside FPGA                                                            Virtex-II Architecture
All Xilinx FPGAs contain some basic resources                       Block SelectRAM™                                   I/O Blocks (IOBs)
  Slices (grouped into Configurable Logic Blocks (CLBs))            resource
      Contain combinatorial logic and register resources
  IOBs                                                                                                                 Programmable
      Interface between the FPGA and the outside world                                                                 interconnect
  Programmable interconnect                                           Dedicated
  Other resources                                                     multipliers
      Memory                                                                                                            Configurable
      Multipliers                                                                                                       Logic Blocks
      Processors                                                                                                        (CLBs)
      Clock management
                                                                     architecture’s core
                                                                                                      Clock Management
                                                                     voltage                          (DCMs, BUFGMUXes)
                                                                     operates at 1.5V
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         Slices and CLBs                                                                           Simplified Slice Structure
Each Virtex™-II CLB contains                         COUT       COUT
                                                                                       Each slice has
four slices                                  BUFT
                                             BUF T
                                                                                         Two 4-input look-up tables
  Local routing provides feedback                                                        (LUTs)
                                                            Slice S3                                                        Slice 0
  between slices in the same                                                                 Any 4-input logic functions
  CLB, and it provides routing to                                                        Four outputs                                            PRE
                                                                                                                           LUT        Carry    D     Q
  neighboring CLBs                                          Slice S2                         Two registered outputs,        LUT        Carry   CE

                                    Switch   SHIFT                                           two non-registered outputs
  A switch matrix provides access                                                                                                               CLR
                                    Matrix                                               Carry logic
  to general routing resources
                                                                                             Fast arithmetic logic
                                              Slice S1
                                                                                         Other controls
                                                                                             e.g. set/reset                LUT        Carry    D PRE
                                              Slice S0
                                                                                                                            LUT        Carry   CE    Q
                                                                       Local Routing

                                                     CIN        CIN

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         Virtex-II Pro Features                                                                    VIrtex-II-Pro Datasheet
Up to 24 RocketIO™ Multi-Gigabit Transceiver (MGT)
  Serializer and deserializer (SERDES)
  Fibre Channel, Gigabit Ethernet, XAUI, Infiniband compliant
  transceivers, and others
  8-, 16-, and 32-bit selectable FPGA interface
  8B/10B encoder and decoder
PowerPC™ RISC processor blocks
  Thirty-two 32-bit General Purpose Registers (GPRs)
  Low power consumption: 0.9mW/MHz
  IBM CoreConnect bus architecture support

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         FPGA Design Flow
                                                                                        Design Entry
          (Xilinx ISE)
                                                                             Plan and budget
                           Create Code/           HDL RTL
                                                                             Two design-entry methods: HDL or schematic
   Plan & Budget
                            Schematic            Simulation                  Whichever method you use, you will need a tool to generate a
       Implement                                                             netlist for implementation
                                                                                Netlist: A text file that describes the actual circuit to be implemented at
                               Functional        Synthesize
       Translate                                                                very low (gate) level
                               Simulation      to create netlist
                                                                             Simulate the design to ensure that it works as expected!

     Place & Route
                                                                                 Plan & Budget              Create Code/                HDL RTL
     Attain Timing               Timing               Create                                                 Schematic                 Simulation
        Closure                Simulation             BIT File
                                                                                            ...                Functional               Synthesize
                                                                                                               Simulation            to create netlist

                                                                   Page 9                                                                                 Page 10

         Xilinx Implementation                                                          What is Implementation?
Once you generate a netlist,                                                 Implementation includes many phases
you can implement the design                                                    Translate: Merge multiple design files into a single netlist
There are several outputs of                  Translate          ...            Map: Group logical symbols from the netlist (gates) into physical
implementation                                                                  components (slices and IOBs)
                                                Map                             Place & Route: Place components onto the chip, connect the
                                                                                components, and extract timing data into reports
  Timing simulation netlists
  Floorplan files                           Place & Route                    Each phase generates files that allow you to use other
  FPGA Editor files
                                                                             Xilinx tools
                                                  .                             Floorplanner, FPGA Editor, XPower
  and more!

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         Timing Closure                                                                   Download
                                                                                 Once a design is implemented, you must create a file
                                                                                 that the FPGA can understand
                                                                                    This file is called a bitstream: a BIT file (.bit extension)
                                                                                 The BIT file can be downloaded directly into the FPGA,
                                                                                 or the BIT file can be converted into a PROM file, which
                                                                                 stores the programming information

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         JTAG and Boundary Scan
                                                                                          Boundary Scan
In the 1980s, the Joint Test Action Group (JTAG)
developed a specification for boundary-scan testing that
was standardized in 1990 as the IEEE Std 1149.1, and
later revised in 1993 (titled 1149.1a).
Boundary-scan architecture
  Each boundary-scan cell including a multiplexer and latches is
  assigned to each pin on the device
  Boundary-scan cells can capture data from pin or core logic
  signals, or force data onto pins.
      The captured data is serially shifted out and externally compared to
      the expected results
      Forced data is serially shifted into the boundary-scan cells
  Boundary-scan cells form a serial data path called the scan path
  or scan chain.
                                                                                 To know more details: Boundary Scan Tutorial, http://www.asset-

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