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FPGA Design with Xilinx ISE

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					       Graduate Institute of Electronics Engineering, NTU




FPGA Design with Xilinx
        ISE

 Presenter: Shu-yen Lin
Advisor: Prof. An-Yeu Wu
        2005/6/6


                                ACCESS IC LAB
ACCESS IC LAB       Graduate Institute of Electronics Engineering, NTU




                   Outline
 vConcepts of Xilinx FPGA
 vXilinx FPGA Architecture
 vIntroduction to ISE
 vCode Generator
 vConstraints and Reports
 vConfiguration
 vDemo and Lab


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       Graduate Institute of Electronics Engineering, NTU




Concepts of Xilinx FPGA




                                ACCESS IC LAB
ACCESS IC LAB   Graduate Institute of Electronics Engineering, NTU



        Electronic Components




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                          FPGA Benefits
                           Full-Custom       Cell-Based         Gate Arrays             FPGA
                                ICs              ICs
         Speed                ●●                   ●                  ●                  ●
   Integration Density        ●●                   ●                  ●                  ●
High-Volume Device Cost       ●●                 ●●                   ●                  ●
Low-Volume device Cost                                                ●                 ●●
    Time to Market                                                    ●                 ●●
    Risk Reduction                                                                      ●●
  Future Modification                                                                   ●●
   Development Tool            ●                   ●                  ●                 ●●
  Educational Purpose                                                                   ●●


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        Full Xilinx Design Support




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                Xilinx Products
 v CPLDs and FPGAs




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        Graduate Institute of Electronics Engineering, NTU




Xilinx FPGA Architecture




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  The Conceptual CPLD Architecture




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        The Conceptual FPGA Architecture

v Field-programmable
v Re-programmable
v In-circuit design verification
v Rapid prototyping
v Fast time-to-market
v No IC-test & NRE cost
v H/W emulation instead of S/W




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 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)




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 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (2/6)
v Logic and Routing - the CLB tile




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Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)
 vLogic and Routing – Simplified CLB Structure




   v Two slices in each CLB
   v Each slice contains 2 LUT, 2 Register and 2 Carry Logic.
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Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)

v Logic and Routing – Look-Up Tables (LUTs)
   v Combinational logic is stored in Look-up Tables
     (LUTs) in a CLB.
   v Capacity is limited by number of inputs, not
     complexity.
   v Delay through CLB is constant.




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 ACCESS IC LAB               Graduate Institute of Electronics Engineering, NTU



   Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (4/6)
   v System Interface – Select IOTM




v Supports multiple voltage and signal standards simultaneously
v Eliminate costly bus transceivers
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  Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (5/6)
v System Memory – Distributed RAM, Block RAM and External Memory




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  Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/6)
v System clock management - DLLs
  v Clock Mirror
  v Multiplication
      Ø 1 DLL for 2x
      Ø Combine 2 DLL for 4x
  v Division
      Ø Selectable division values - 1.5, 2, 2.5,
        3, 4, 5, 8, or 16
  v Phase Shift
      Ø 0, 90, 180, 270




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 Spatran-3, VirtexII FPGA Architecture (1/7)




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 Spatran-3, VirtexII FPGA Architecture (2/7)
v Logic and Routing - the CLB tile




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 Spatran-3, VirtexII FPGA Architecture (3/7)
vSystem Interface – Select IOTM                                  23 different
                                                                  standards
                                                                 supported !




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Spatran-3, VirtexII FPGA Architecture (4/7)
v System Memory –External Memory supports DDR memory




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Spatran-3, VirtexII FPGA Architecture (5/7)
 v System clock management – DCMs




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Spatran-3, VirtexII FPGA Architecture (6/7)
 v System clock management – DCMs




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 Spatran-3, VirtexII FPGA Architecture (7/7)
 v Embedded multiplexer




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    VirtexII Pro FPGA Architecture




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   Programmable Logic Evolution




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     Graduate Institute of Electronics Engineering, NTU




Introduction to ISE




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                     ISE Philosophy
 v ISE 6.1i
    v Future Xilinx devices
    v Proactive Timing Closure
    v ECS & HDL Bencher & XST
 v Platform
    v Unix: Solaris 2.7/2.8
    v PC: Win 2000/XP
 v Service Pack
    v http://support.xilinx.com
 v ISE WebPage
    v http://www.xilinx.com/ise

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          Design Flow in ISE (1/2)
                                          Design                  A&B=C


                                                                  A
                                         Synthesis                                C
                                                                  B

                                                                          CLB
                                                         A
                                        Implement                 LUT           Reg   C
                                                          B



                                        Download              A
                                                              B
                                                                      C




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          Design Flow in ISE (2/2)




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 Introduction to Projection Navigator (1/4)




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 Introduction to Projection Navigator (2/4)
 v Source Windows




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 Introduction to Projection Navigator (3/4)
 vProcesses for current source




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 Introduction to Projection Navigator (4/4)
 v Processes for current source




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           Create New Project




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ACCESS IC LAB    Graduate Institute of Electronics Engineering, NTU




           Create New Source




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                HDL Source File




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                Text Entry




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          Language Templates




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                Synthesis (1/4)
 v XST




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                Synthesis (2/4)
 v XST Flow




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                Synthesis (3/4)
 v Synthesis Step




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                Synthesis (4/4)
 v RTL view




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                  Implementation (1/8)

Translate - Merge multiple design
files into a single netlist
Map - Group logical symbols from the
netlist (gates) into physical components
(CLBs and IOBs)
Place & Route - Place components
onto the chip, connect them, and
extract timing data into reports




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ACCESS IC LAB      Graduate Institute of Electronics Engineering, NTU



            Implementation (2/8)




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ACCESS IC LAB      Graduate Institute of Electronics Engineering, NTU



            Implementation (3/8)
                                                             Translate




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ACCESS IC LAB      Graduate Institute of Electronics Engineering, NTU



            Implementation (4/8)
                                                                  Map




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                  Implementation (5/8)
v Map Property
  v Trim Unconnected Signals
     Ø If you check this item, the mapping tool will remove the unconnected
       wire that let the tracing back become hardly.
  v Generate Detailed Map Report
     Ø If more detailed report is needed, you can check it. (Recommending
       check it)
  v Use Guide Design File (.ncd)
     Ø You can refer the last mapping solution so that you maybe get better
       solution.
  v Use RLOC Constraints
     Ø Constraints of CLB (default check).
  v Pack I/O Registers/Latches into IOBs
     Ø If the value chosen Default that pack the register nearby I/O into I/O
       block. You can also chose only for input or only for output or off.


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            Implementation (6/8)
                                                             Place and
                                                               Route




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                    Implementation (7/8)
v Place and Route Property (1/2)
   v Place & Route Effort Level (Overall)
       Ø Effort Level means the P&R effect result. Using the Higher get the
         better solution, but spend more time.
   v Starting Placer Cost Table (0-100)
       Ø Specify a placement initialization value with which to begin P&R
         attempts. Each subsequent attempt is assigned an incremental
        value based on the placement initialization value.
   v Place and Route Mode
       Ø Quick means without timing constraints; Route Only and Re-entrant
         Route mean P&R must have been run at last once to use this option.
   v Guide File
       Ø Include the .ncd file.


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                   Implementation (8/8)
v Place and Route Property (2/2)
   v Use Timing Constraints
      Ø Include the .ucf file.
   v Use Bonded I/Os
      Ø If it is checked, signals will be connected to I/O pads.
   v Generate Detailed PAR Report
      Ø Check the value to generate a detailed PAR report.
   v Generate Post-Place & Route Static Timing Report
      Ø Check the value to generate post-place & route static timing report.
   v Generate Post-Place & Route Simulation Model
      Ø Check it for generating required simulation files for ModelSim (*.v and
        *.sdf).



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                Download (1/2)




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                Download (2/2)




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   Graduate Institute of Electronics Engineering, NTU




Code Generator




                            ACCESS IC LAB
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                What are Cores?




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        Benefits of Using Cores




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    Invoking the CORE Generator GUI




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 Xilinx Code Generator System GUI




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        Core Customize Window




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                Core Data Sheet




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     Core Generator Design Flow




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    Link with CodeGen IP (Verilog)




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       Graduate Institute of Electronics Engineering, NTU




Constraints and Reports




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                      Topics
 vAssign Package Pins (PACE)
    vAssigning Pins
 vCreate Timing Constraints
    vThe PERIOD Constraints
    vThe Pad-to-Pad Constraints
    vThe OFFSET Constraints
    vThe Constraints Editor
 vRead Report


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            Constraints GUI (1/2)




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            Constraints GUI (2/2)




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         Assign Package Pins (1/6)
 vStart PACE Editor




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         Assign Package Pins (2/6)
 vPACE Editor GUI




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         Assign Package Pins (3/6)
 vMethod #1 to assign package pins




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         Assign Package Pins (4/6)
 vMethod #2 to assign package pins




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ACCESS IC LAB      Graduate Institute of Electronics Engineering, NTU



         Assign Package Pins (5/6)
 vMethod #3 to assign package pins




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         Assign Package Pins (6/6)
 vMethod #4 to assign package pins
vUse text editor to
 edit .ucf files
vNET is port name
vLOC assign pins to
 specific location




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          The PERIOD Constraint




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        The Pad-to-Pad Constraint




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          The OFFSET Constraint




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      The Constraint Editor (1/3)




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         The Constraint Editor (2/3)
 v Enter PERIOD and Pad-to-Pad Constraint




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         The Constraint Editor (3/3)
 v Enter OFFSET Constraint




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                Read Report (1/12)
 v Create Report Files




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                Read Report (2/12)




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                Read Report (3/12)
 v Example of MAP Report (1/2)




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                Read Report (4/12)
 v Example of MAP Report (2/2)




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ACCESS IC LAB         Graduate Institute of Electronics Engineering, NTU



                Read Report (5/12)




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ACCESS IC LAB         Graduate Institute of Electronics Engineering, NTU



                Read Report (6/12)
 v Example of PAR Report (1/2)




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                Read Report (7/12)
 v Example of PAR Report (2/2)




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                Read Report (8/12)




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ACCESS IC LAB          Graduate Institute of Electronics Engineering, NTU



                Read Report (9/12)
 v Example of Timing Report (1/4)




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ACCESS IC LAB          Graduate Institute of Electronics Engineering, NTU



              Read Report (10/12)
 v Example of Timing Report (2/4)




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ACCESS IC LAB          Graduate Institute of Electronics Engineering, NTU



              Read Report (11/12)
 v Example of Timing Report (3/4)




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              Read Report (11/12)
 v Example of Timing Report (4/4)




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          Post-layout Simulation




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   Graduate Institute of Electronics Engineering, NTU




Configuration




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          What is configuration?
 v Process for loading into the FPGA




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         Configuration Mode (1/4)




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          Configuration Mode (2/4)
 v Serial Mode




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         Configuration Mode (3/4)
 vSelectMAP Mode




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         Configuration Mode (4/4)
 v JTAG or Boundary Scan




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                     IMACT (1/3)




Must double clock “Generate Programming File”
before programming FPGA
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                IMACT (2/3)




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                IMACT (3/3)




                                                                        pp. 100

				
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