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Graduate Institute of Electronics Engineering, NTU
FPGA Design with Xilinx
ISE
Presenter: Shu-yen Lin
Advisor: Prof. An-Yeu Wu
2005/6/6
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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Outline
vConcepts of Xilinx FPGA
vXilinx FPGA Architecture
vIntroduction to ISE
vCode Generator
vConstraints and Reports
vConfiguration
vDemo and Lab
pp. 2
Graduate Institute of Electronics Engineering, NTU
Concepts of Xilinx FPGA
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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Electronic Components
pp. 4
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
FPGA Benefits
Full-Custom Cell-Based Gate Arrays FPGA
ICs ICs
Speed ●● ● ● ●
Integration Density ●● ● ● ●
High-Volume Device Cost ●● ●● ● ●
Low-Volume device Cost ● ●●
Time to Market ● ●●
Risk Reduction ●●
Future Modification ●●
Development Tool ● ● ● ●●
Educational Purpose ●●
pp. 5
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Full Xilinx Design Support
pp. 6
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Xilinx Products
v CPLDs and FPGAs
pp. 7
Graduate Institute of Electronics Engineering, NTU
Xilinx FPGA Architecture
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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
The Conceptual CPLD Architecture
pp. 9
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
The Conceptual FPGA Architecture
v Field-programmable
v Re-programmable
v In-circuit design verification
v Rapid prototyping
v Fast time-to-market
v No IC-test & NRE cost
v H/W emulation instead of S/W
pp. 10
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)
pp. 11
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (2/6)
v Logic and Routing - the CLB tile
pp. 12
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)
vLogic and Routing – Simplified CLB Structure
v Two slices in each CLB
v Each slice contains 2 LUT, 2 Register and 2 Carry Logic.
pp. 13
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)
v Logic and Routing – Look-Up Tables (LUTs)
v Combinational logic is stored in Look-up Tables
(LUTs) in a CLB.
v Capacity is limited by number of inputs, not
complexity.
v Delay through CLB is constant.
pp. 14
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Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (4/6)
v System Interface – Select IOTM
v Supports multiple voltage and signal standards simultaneously
v Eliminate costly bus transceivers
pp. 15
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Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (5/6)
v System Memory – Distributed RAM, Block RAM and External Memory
pp. 16
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/6)
v System clock management - DLLs
v Clock Mirror
v Multiplication
Ø 1 DLL for 2x
Ø Combine 2 DLL for 4x
v Division
Ø Selectable division values - 1.5, 2, 2.5,
3, 4, 5, 8, or 16
v Phase Shift
Ø 0, 90, 180, 270
pp. 17
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Spatran-3, VirtexII FPGA Architecture (1/7)
pp. 18
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-3, VirtexII FPGA Architecture (2/7)
v Logic and Routing - the CLB tile
pp. 19
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-3, VirtexII FPGA Architecture (3/7)
vSystem Interface – Select IOTM 23 different
standards
supported !
pp. 20
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-3, VirtexII FPGA Architecture (4/7)
v System Memory –External Memory supports DDR memory
pp. 21
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-3, VirtexII FPGA Architecture (5/7)
v System clock management – DCMs
pp. 22
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-3, VirtexII FPGA Architecture (6/7)
v System clock management – DCMs
pp. 23
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Spatran-3, VirtexII FPGA Architecture (7/7)
v Embedded multiplexer
pp. 24
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
VirtexII Pro FPGA Architecture
pp. 25
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Programmable Logic Evolution
pp. 26
Graduate Institute of Electronics Engineering, NTU
Introduction to ISE
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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
ISE Philosophy
v ISE 6.1i
v Future Xilinx devices
v Proactive Timing Closure
v ECS & HDL Bencher & XST
v Platform
v Unix: Solaris 2.7/2.8
v PC: Win 2000/XP
v Service Pack
v http://support.xilinx.com
v ISE WebPage
v http://www.xilinx.com/ise
pp. 28
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Design Flow in ISE (1/2)
Design A&B=C
A
Synthesis C
B
CLB
A
Implement LUT Reg C
B
Download A
B
C
pp. 29
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Design Flow in ISE (2/2)
pp. 30
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Introduction to Projection Navigator (1/4)
pp. 31
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Introduction to Projection Navigator (2/4)
v Source Windows
pp. 32
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Introduction to Projection Navigator (3/4)
vProcesses for current source
pp. 33
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Introduction to Projection Navigator (4/4)
v Processes for current source
pp. 34
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Create New Project
pp. 35
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Create New Source
pp. 36
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HDL Source File
pp. 37
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Text Entry
pp. 38
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Language Templates
pp. 39
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Synthesis (1/4)
v XST
pp. 40
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Synthesis (2/4)
v XST Flow
pp. 41
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Synthesis (3/4)
v Synthesis Step
pp. 42
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Synthesis (4/4)
v RTL view
pp. 43
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Implementation (1/8)
Translate - Merge multiple design
files into a single netlist
Map - Group logical symbols from the
netlist (gates) into physical components
(CLBs and IOBs)
Place & Route - Place components
onto the chip, connect them, and
extract timing data into reports
pp. 44
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Implementation (2/8)
pp. 45
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Implementation (3/8)
Translate
pp. 46
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Implementation (4/8)
Map
pp. 47
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Implementation (5/8)
v Map Property
v Trim Unconnected Signals
Ø If you check this item, the mapping tool will remove the unconnected
wire that let the tracing back become hardly.
v Generate Detailed Map Report
Ø If more detailed report is needed, you can check it. (Recommending
check it)
v Use Guide Design File (.ncd)
Ø You can refer the last mapping solution so that you maybe get better
solution.
v Use RLOC Constraints
Ø Constraints of CLB (default check).
v Pack I/O Registers/Latches into IOBs
Ø If the value chosen Default that pack the register nearby I/O into I/O
block. You can also chose only for input or only for output or off.
pp. 48
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Implementation (6/8)
Place and
Route
pp. 49
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Implementation (7/8)
v Place and Route Property (1/2)
v Place & Route Effort Level (Overall)
Ø Effort Level means the P&R effect result. Using the Higher get the
better solution, but spend more time.
v Starting Placer Cost Table (0-100)
Ø Specify a placement initialization value with which to begin P&R
attempts. Each subsequent attempt is assigned an incremental
value based on the placement initialization value.
v Place and Route Mode
Ø Quick means without timing constraints; Route Only and Re-entrant
Route mean P&R must have been run at last once to use this option.
v Guide File
Ø Include the .ncd file.
pp. 50
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Implementation (8/8)
v Place and Route Property (2/2)
v Use Timing Constraints
Ø Include the .ucf file.
v Use Bonded I/Os
Ø If it is checked, signals will be connected to I/O pads.
v Generate Detailed PAR Report
Ø Check the value to generate a detailed PAR report.
v Generate Post-Place & Route Static Timing Report
Ø Check the value to generate post-place & route static timing report.
v Generate Post-Place & Route Simulation Model
Ø Check it for generating required simulation files for ModelSim (*.v and
*.sdf).
pp. 51
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Download (1/2)
pp. 52
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Download (2/2)
pp. 53
Graduate Institute of Electronics Engineering, NTU
Code Generator
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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
What are Cores?
pp. 55
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Benefits of Using Cores
pp. 56
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Invoking the CORE Generator GUI
pp. 57
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Xilinx Code Generator System GUI
pp. 58
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Core Customize Window
pp. 59
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Core Data Sheet
pp. 60
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Core Generator Design Flow
pp. 61
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Link with CodeGen IP (Verilog)
pp. 62
Graduate Institute of Electronics Engineering, NTU
Constraints and Reports
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Topics
vAssign Package Pins (PACE)
vAssigning Pins
vCreate Timing Constraints
vThe PERIOD Constraints
vThe Pad-to-Pad Constraints
vThe OFFSET Constraints
vThe Constraints Editor
vRead Report
pp. 64
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Constraints GUI (1/2)
pp. 65
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Constraints GUI (2/2)
pp. 66
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Assign Package Pins (1/6)
vStart PACE Editor
pp. 67
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Assign Package Pins (2/6)
vPACE Editor GUI
pp. 68
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Assign Package Pins (3/6)
vMethod #1 to assign package pins
pp. 69
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Assign Package Pins (4/6)
vMethod #2 to assign package pins
pp. 70
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Assign Package Pins (5/6)
vMethod #3 to assign package pins
pp. 71
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Assign Package Pins (6/6)
vMethod #4 to assign package pins
vUse text editor to
edit .ucf files
vNET is port name
vLOC assign pins to
specific location
pp. 72
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The PERIOD Constraint
pp. 73
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
The Pad-to-Pad Constraint
pp. 74
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
The OFFSET Constraint
pp. 75
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
The Constraint Editor (1/3)
pp. 76
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
The Constraint Editor (2/3)
v Enter PERIOD and Pad-to-Pad Constraint
pp. 77
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
The Constraint Editor (3/3)
v Enter OFFSET Constraint
pp. 78
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Read Report (1/12)
v Create Report Files
pp. 79
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Read Report (2/12)
pp. 80
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Read Report (3/12)
v Example of MAP Report (1/2)
pp. 81
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Read Report (4/12)
v Example of MAP Report (2/2)
pp. 82
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Read Report (5/12)
pp. 83
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Read Report (6/12)
v Example of PAR Report (1/2)
pp. 84
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Read Report (7/12)
v Example of PAR Report (2/2)
pp. 85
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Read Report (8/12)
pp. 86
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Read Report (9/12)
v Example of Timing Report (1/4)
pp. 87
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Read Report (10/12)
v Example of Timing Report (2/4)
pp. 88
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Read Report (11/12)
v Example of Timing Report (3/4)
pp. 89
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Read Report (11/12)
v Example of Timing Report (4/4)
pp. 90
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Post-layout Simulation
pp. 91
Graduate Institute of Electronics Engineering, NTU
Configuration
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What is configuration?
v Process for loading into the FPGA
pp. 93
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Configuration Mode (1/4)
pp. 94
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Configuration Mode (2/4)
v Serial Mode
pp. 95
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Configuration Mode (3/4)
vSelectMAP Mode
pp. 96
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Configuration Mode (4/4)
v JTAG or Boundary Scan
pp. 97
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
IMACT (1/3)
Must double clock “Generate Programming File”
before programming FPGA
pp. 98
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IMACT (2/3)
pp. 99
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
IMACT (3/3)
pp. 100
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