Chapter 7 Flip-Flops Dr. Fahim Arif
(NUST)
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7.1 Latches • The latch is a type of temporary storage devices that has two stable states ( bi-stable ). • Latches are similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement, in which the outputs are connected back to the opposite inputs. • The main difference between the latches and flipflops is in the method used for changing their state.
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The S-R ( Set-Reset) Latch – A type of bi-stable logic device or Multivibrator. – Active-HIGH input S - R Latch is formed with two cross-coupled NOR gates as shown in Fig. 7-1(a) – Active-LOW input S - R Latch is formed with two cross-coupled NAND gates as shown in Fig. 7-1(b) – The output of each gate is connected to an input of the opposite gate 3
Figure 7-1 Two versions of Set-Reset (S-R) latches.
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- The output of each gate is connected to an input of the opposite gate. - The re-generative feedback is characteristic of all latches and flip-flops NAND gate S - R latch Negative-OR gate S - R latch Fig. 7-2 * S, R and Q = HIGH Initially * Q → G2 , R = HIGH ⇒ G2 = Q = LOW * G2 = Q → G1 , S=HIGH ⇒ Q = HIGH
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Figure 7-2
Negative-OR equivalent of the NAND gate S-R latch in Figure 7-1(b).
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There are three basic S-R latch operation (1) Set operation = the output Q = HIGH S=LOW, R=HIGH Q = HIGH Fig. 7-3(a) (2) Reset operation = The output Q = LOW S=HIGH, R=LOW Q = LOW Fig. 7-3(b) (3) No-change condition = Q/Q unchanged S=HIGH, R=HIGH Q/Q unchanged Fig.7-3(c) Invalid condition S = LOW, R = LOW
Q=?
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Figure 7--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition
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Summarizes the logic operation in truth table Table 7-1 Truth table for an active-LOW inputs S-R latch
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• Logic symbols for both the active-HIGH input and active-LOW input Latches are shown in Fig. 7-4 • An IC Set-Reset Latch 74LS279 – Quad S-R latch represented by the logic diagram of Fig.7-7
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Fig. 7-4 Logic symbols for the S - R and S - R Latch
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The Gated S-R Latch • Fig. 7-7 • An enable input EN EN = HIGH, the output is controlled by the state of S and R inputs. • When S = R = HIGH invalid state occurs. • When EN = LOW, the latch is not change.
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Figure 7-8
A gated S-R latch
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The gated D latch Fig. 7-10 • It has only one input D in addition to EN • D = HIGH, EN = HIGH Q = HIGH the latch is SET • D = LOW, EN = HIGH Q = LOW the latch is RESET The output Q follows the input D when EN is HIGH • When EN = LOW, the latch is not change
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Figure 7-10 A gated D latch
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• An IC D latch 74LS75 (Quad gated D latches) Fig. 7-12(a) • The truth table for each latch is shown in Fig. 7-12(b)
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Figure 7-12 The 74LS75 quad gated D latches
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7-2 Edge-Triggered Flip-Flops – Flip-Flops are synchronous bi-stable devices – The synchronous means that the output changes state only at a specified point on a triggering input called the Clock (CLK) which is designed as a control input. – An edge-triggered flip-flop change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the pulse. – Three type of edge-triggered flip-flops: S - R , D, and J - K. Fig. 7-13 18
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Figure 7-13 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered).
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The Edge-triggered S-R Flip-Flips The basic operation of a positive edge-triggered flip-flop is illustrated in Fig. 7-14 (a) S = HIGH, R = LOW Q (output) = HIGH on the triggering edge of the clock pulse. the flip-flop is SET (b) S = LOW, R = HIGH Q = LOW The flip-flop is RESET (c) S = LOW, R = LOW Q (output) does NOT change. (d) S = HIGH, R = HIGH an invalid condition exists. 20
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Fig. 7-14 Operation of a positive edge-triggered S-R flip-flop
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– The flip-flop cannot change state except on the triggering edge of a clock pulse. – Table 7-2 The truth table for this flip-flop
– The S and R inputs can be changed at any time when the clock input is LOW or HIGH.
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A Method of Edge-Triggering
• An edge-triggered S-R flip-flop is shown in Fig.7-17(a) • A pulse transition detector produces a very shortduration spike on the positive-going transition of the clock pulse Fig.7-17(b) • In a negative edge-triggered flip-flop the clock pulse is a narrow spike on the negative-going edge • In Fig.7-17(a) the circuit is partitioned into two sections, one labeled steering gates and the other labeled latch 23
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Fig.7-17(a) the circuit is partitioned into two sections, one labeled Steering gates and the other labeled Latch
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Fig.7-17(b) A pulse transition detector produces a very short-duration spike on the positive-going transition of the clock pulse
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• Assume the flip-flop is in RESET state ♦ Q=LOW, S = R = CLK = LOW ⇒ the outputs of gates G1 and G2 are both HIGH ♦ Q = LOW → input of G4 ⇒ Q = HIGH ⇒Table 7-2 (1) ♦A pulse is applied to the CLK ⇒ the outputs of gates G1 and G2 remain HIGH there is no change in the state of the flip-flop ⇒ Q = LOW and Q = HIGH = RESET state
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Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse shown in Fig. 7-18 ♦ S = HIGH and R=LOW , and apply a CLK S = HIGH and when CLK goes positive ⇒ the output of G1 = LOW for a very short time (positive spike) ⇒ causes the output Q = HIGH ♦ Both inputs to gate G4 are HIGH ⇒ Q = LOW ⇒ Q = HIGH and Q = LOW = Set state Table 7-2 (3)
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Figure 7-18 Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse
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Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse shown in Fig. 7-19 ♦ S = LOW and R= HIGH , and apply a CLK R = HIGH and when CLK goes positive ⇒ the output of G2 = LOW for a very short time ( positive spike) ⇒ causes the output Q = HIGH ♦ Both inputs to gate G3 are HIGH ⇒ Q = LOW ⇒ Q = HIGH and Q = LOW = Reset state Table 7-2 (2)
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Figure 7-19 Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.
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The Edge-triggered D Flip-Flop – The D flip-flop is useful when a single data bit is to be stored. – The addition of an inverter to an S-R flip-flop creates a basic D flip-flop. Fig. 7-20 – D = HIGH (S = HIGH and R = LOW) the flip-flop will SET on the positive-going edge of the clock pulse. – D = LOW ( S = LOW and R = HIGH) the flip-flop will RESET on the positive-going edge of the clock pulse.
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The logic operation of the positive edge-triggered D flip-flop is summarized in Table 7-3
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The Edge-triggered J-K flip-flop • The J-K flip-flop is versatile and is a widely used type of flip-flop • The function of J-K flip-flop is identical to that of S-R flip-flop in the SET, RESET, and no-change conditions operation. • The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop.
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The logic diagram of a positive edge-triggered J-K flip-flop is shown in Fig. 7-22 (1) J = HIGH, K = LOW the flip-flop changes to the SET state. (2) J = LOW, K = HIGH the flip-flop changes to the RESET state. (3) J = LOW, K = LOW the flip-flop will stay( No change) in its present state when a clock pulse occurs. (4) J = HIGH, K = HIGH the flip-flop changes to the opposite state.
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Figure 7-22 A simplified logic diagram for a positive edgetriggered J-K flip-flop.
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Assume flip-flop is RESET initially Fig.7.23 Q = LOW and Q = HIGH (1) The flip-flop is SET J = HIGH , when a clock pulse occurs ⇒ a positive spike → G1 ⇒ a negative spike → G3 ⇒ Q = HIGH K = LOW , when a clock pulse occurs ⇒ a positive spike → G2 ⇒ The output of G2 is HIGH and Q = HIGH → G4 ⇒ Q = LOW the flip-flop changes to the SET state. 36 Table 7-4 (3)
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(2) The flip-flop is RESET J = LOW , when a clock pulse occurs ⇒ a positive spike → G1 ⇒ The output of G1 is HIGH and Q = HIGH → G3 ⇒ Q = LOW K = HIGH , when a clock pulse occurs ⇒ a positive spike and Q = HIGH → G2 ⇒ a negative spike → G4 ⇒ Q = HIGH the flip-flop changes to the RESET state. Table 7-4 (2) 37
(3) The flip-flop is no change J = LOW , when a clock pulse occurs ⇒ a positive spike → G1 ⇒ The output of G1 is HIGH → G3 ⇒ Q = Negation of Q = Q K = LOW , when a clock pulse occurs ⇒ a positive spike → G2 ⇒ The output of G2 is HIGH → G4 ⇒ Q = Negation of Q = Q the flip-flop stay in its present state. Table 7-4 (1)
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(4) The flip-flop is Toggle (Change) J = HIGH , when a clock pulse occurs ⇒ a positive spike and Q = HIGH → G1 ⇒ a negative spike and Q = HIGH → G3 ⇒ The output of G3 = Q = HIGH K = HIGH , when a clock pulse occurs ⇒ a positive spike and Q = LOW → G2 ⇒ the output of G2 = HIGH and Q = HIGH → G4 ⇒ Q = LOW Table 7-4 (4) 39
Fig. 7-23 Transitions illustrating the toggle operation when J= HIGH =1 and K= HIGH = 1
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The logic operation of the positive edge-triggered JK flip-flop are summarized in Table 7-4
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7.3 Master-Slave Flip-Flops (pulse-triggered) Data are entered into the flip-flop at the leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge – The master-slave flip-flop does not allow data to change while the clock pulse is active. – A basic master-slave J-K flip-flop is shown in Fig. 7-32. There are two sections : the master section and the slave section.
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Figure 7-32 Basic logic diagram for a master-slave J-K flip-flop
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– The master section will assume the state determined by the J-K inputs beginning at the leading edge of the clock pulse. – The states of the master section is then transferred to the slave section on the trailing edge of the clock pulse. – At the trailing edge of the clock pulse, the state of the slave then appears on the Q and Q outputs.
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The logic operation is summarized in Table 7-5.
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The Logic symbols for the J-K pulse-triggered (master-slave) flip-flop are shown in Fig. 7-33 (a) Active-HIGH clock :Data are clocked in on positive- going edge of clock pulse and transferred to output on the following negative-going edge. (b) Active-LOW clock :Data are clocked in on negative- going edge of clock pulse and transferred to output on the following positive-going edge.
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Fig. 7-33 Pulse-triggered (master-slave) J-K flip-flop logic symbols.
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Fig. 7-34 The master-slave J-K flip-flop with active- LOW clock
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7.4 Flip-flop operation characteristics Propagation Delay times – The interval of time required after an input signal has been applied for the resulting output change to occur. 1. t PLH – as measured from the triggering edge of the clock pulse to LOW-to-HIGH transition of the output Fig. 7-35(a) 2. t PHL – as measured from the triggering edge of the clock pulse to HIGH-to-LOW transition of the output Fig. 7-35(b)
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Figure 7-35 Propagation delays, clock to output.
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3. t PLH – as measured from the preset input to the Low-to-HIGH transition of the output Fig. 7-36(a) 4. t PHL – as measured from the clear input to the HIGH-to-Low transition of the output Fig. 7-36(b)
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Figure 7-36 Propagation delays, preset input to output and clear input to output.
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Set-up Time (ts) – The minimum interval required for the logic levels to be maintained constantly on the inputs ( J and K, or S and R, or D ) prior to the triggered edge of the clock pulse. – Fig. 7-37 Hold-Time (th) – The minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse. – Fig. 7-38 53
Figure 7--37 Set-up time (ts). The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry.
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Figure 7--38 Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry.
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Maximum Clock Frequency (f max) – The highest rate at which a flip-flop can be reliably triggered. Pulse width (t w) – Minimum pulse width (t w) for reliable operation are specified by the manufacturer for the clock, preset , and clear inputs. – The clock is specified by its minimum HIGH time and its minimum LOW time.
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Power Dissipation – The total power consumption of the device. Comparison of specific flip-flops of four CMOS and TTL flip-flops is shown in Table 7-6
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Homework 7- 4 7- 12 7- 20 7- 29 7- 30
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