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Monolithic RFIC Design Chapter 08 Oscillator Design & Phase Noise Issues (B.Razavi, RF Microelectronics, Ch.7) 1. Introduction : General models, basic topologies, VCO 2. General Considerations : oscillation frequency, pushing / pulling, turning range, VCO gain/sensitivity output power, and phase noise. 3. Performance Evaluation Parameters : Power consumption, tuning range, VCO gain (Kvco) phase noise (PN), pushing/pulling figure. 4. Introduction to “Quadrature Signal Generation”. Introduction General Considerations: •Oscillator generates a periodic output. needs self-sustaining oscillation mechanism; Transfer Function of a Linear Feedback System : Y(s) H(s) X(s) 1 H(s) If H(s) =+1, oscillating Fig.1 Feedback oscillator system. •A real oscillator in the viewpoint of feedback: two-port model: Barkhausen' s criteria : (1) the loop gain : H(j0 ) 1, (2) the totalphase shift around the loop : H(j0 ) 0 or 360. * if the loop in DC is negative, then H(j0 ) has to be 180 (that is, a negative feedback) (analysis) One-port model : One-port circuit for the LC tank. r L2 •R1 : negative Rp Rs (in real case, positive) A concept of oscillation’s start-up : The small-signal loop gain must be somewhat greater than one. oscillation grows up by noise; but to achieve a stable amplitude, the average loop gain must return to unity. Self-sustaining oscillation. power constrained / saturation limitation Automatic Level Control (ALC) Topology: •Pros : enhance the “linearity” of the oscillator; thus less AM-to-PM modulation property •Corns : introduce noise into the core. (a rectifier) (noise) Reference Paper : (IEEE Int. Symp. ISCAS2005, pp.2691-2694) Ideal Waveform -- Square Wave or Sinusoidal Wave? •Discontinuous due to the threshold voltage (VT); •Square wave is better for the switching purpose; •Sinusoidal wave is cleaner in the spectrum •Non-linearity of MOSFET self-mixing noise; •Need trade-off between using Square wave and Sinusoidal Wave. Basic LC Oscillator Topologies: •Discrete RF Oscillator Design: -- to minimize the noise (∵high-Q available) -- to lower the cost •Why usually use “only one active device” in discrete VCO design? -- Low noise, (a matched device pair is necessary for differential topology.) -- Low cost, (BOM – Bill of Materials) -- Smaller package size. Positive Feedback for Oscillation: •Low (load) impedance •Drop the loop gain •Tank’s Q degrades. feedback path feedback path 1/ gm Implementation approach: •Transformer feedback •Increase (load) impedance •Enhance Q –factor. n2 gm (with Cap., Colpitts osc.) Implementation approach: (cont.) [更正, 12/18] C L (1 1 ) 2 / g m (1 2 ) 2 / g m C2 L1 More components, side-effects, seldom use. Enlarge L or C of a tank? Rp r L 2 Rs Assumed L and R s scale proportionally : R p,final r mL2 mR p (Q is enhanced) mRs •Enlarge “L” for better signal swing (S/N ↗) •Trade-offs: self-resonant frequency and tuning range decrease (for a fixed osc. frequency). Noise Consideration: (in Colpitts or Hartley oscillators) •BJT : base resistance, collector shot noise. •MOS : gate noises, drain 1/f noise, channel resistance. • Voltage Swing should avoid to “saturate” the active devices. Negative Resistance in One-Port View: MOS model: Vgs Vx Vgs + I x I gs and I d g m Vgs ; I C2 g m v gs id 1 / sC1 1 / sC 2 - I x I d I C2 (negative resistance) Vx g 1 1 g 1 1 2 m 2 m I x s C1C2 sC1 sC 2 C1C2 sC1 sC2 (imaginary part) Voltage Controlled Oscillator Topology: •Bias circuit not shown; •In (a), a discrete oscillator; •In (b), an on-chip, Colpitts oscillator; •In (c), the bias ckt (not shown) will degrades tank’s Q less use. (上頁colpitts osc 有一端接地) Voltage Controlled Oscillator Topology : (cont.) •Many communication systems use “channels” concept for data exchange. •Frequency-tunable oscillator is needed VCO. Voltage Controlled Oscillator: (cont.) Mathematical Model : oscillator output : y(t) A cos(RF t (t )) t where, (t ) KVCO Vcont (t )dt if only Vcont (t ) constant V0 , Note: in a VCO, the phase error then is accumulative.) y(t) A cos(( RF KVCOV0 ) t 0 ) •Concept: VCO’s function is a “phase modulator” rather than a “frequency generator”. Phase Noise: •Noise injection causes (a) frequency variation; and (b) amplitude variation. and vice versa. •Analog Phase noise •Digital Jitters Noise Skirt: [Noise Shaping] Ideal Oscillator Actual Oscillator c c △ω Phase Noise Calculation – an example: PN (dBc/Hz @ △ω offset) = △ (in dB) – 10 log (BW) = Output S0 (in dB) – Noise level (in dB) @ △ω – 10 log (BW) Ideal Oscillator Actual Oscillator △ c c △ω Leeson’s Equation of Phase Noise: 1 FkT f c fo 2 L(fm ) f 1 ( 2Q f ) 1 2 Po m L m where L( ) : phase noise; f m : offset frequency; F : fitting parameter; Po : output power; f c : corner frequency(1/f effect on VCO ckt) f o : output frequency; Q L : Q factor of the resonator. Possible PN curves: 1/f3 PN (dBc/Hz) 1/f3 PN (dBc/Hz) PN (dBc/Hz) 1/f2 1/f Offset freq. Offset freq. Offset freq. Low-QL Medium-QL High-QL Phase Noise Mechanisms: Discrete Frequency Noise: •Noise generated by a certain kind of periodic noise source。 Ex. PLL’s spur due to the reference frequency fREF. Power-Law (階次方) Noise: •Random noise with a probability distribution: Power-Law Noises: Effect of Phase Noise on RF Transceivers: •For Rx chain: (blocking effect) “reciprocal mixing”: Dirty LO signal makes S/N ratio degrades. •For Tx Chain: (S/N degradation) Effect of “Pure” Phase Noise: •Diverse in a constellation circle. •BER (bit error rate) increases. The constellation plot: [Measurement] Definition of Q-factor: Pstored per cycle 0 d Q 2 Pdissipated per cycle 2 d Q how much the energy is lost as it is transferr ed from the capacitor to the inductor and vice versa. •For a resonant circuit: Vx 1 Colpitts Oscillator: sL // // R p I in sCeq where C1C2 Ceq and (C1 C2 ) (1 C1 / C2 ) 2 RP gm If C1 C2 s g m , the voltage applied to the sourceend of M1 is : C2 Vs Vx [ ] (C1 C2 ) Vs the drain currentof M1 is : C2 I out g mVx (C1 C2 ) Colpitts Oscillator: (cont.) 1 x3 x5 x7 tan x x 3 5 7 (open-loop I out C2 sL // 1 transfer (s) g m // R p function) I in C1 C2 sCeq L ( ) tan 1 2 R p (1 2 LCeq ) 1 at 0 , LCeq d Rp 2Ceq R p Q 0Ceq R p d 0 0 L (並聯) Sources of Phase Noises: Noise in Signal Path: from the noise viewpoint : Y(s) H(s) X(s) 1 H(s) where if 0 , and 0 dH H ( j ) H ( j0 ) d 0 Since at 0 , H ( j0 ) 1 ... (at resonant) Y ( j (0 )) H ( j (0 )) H ( j 0 ) X ( j (0 )) 1 H ( j (0 )) dH 1 [ H ( j0 ) ] d 0 1 1 dH dH 1 [1 ] d d 0 0 Noise in Signal Path: (cont.) 2 voltage gain power Y 2 X 2 Y 1 X ( j (0 )) 2 dH ( ) 2 d Let is the j ( ) Let H( ) H e phase of the open-loop dH dH d j ( jH )e transfer function. d d d Since H constant, d d 2 2 2 dH 2 H ...H 1 at resonant. d d d Noise in Signal Path: (cont.) d 2 2 2 Y 1 dH X ( j (0 )) and dH 2 d d ( ) 2 d at 0 , Added intentionally! the Noise Gain is 0 1 0 2 2 Y 2 1 X ( j ) 2 4 0 d 2 2 4Q ( ) 2 d * This noise gain is due to the transferfunction! Noise in Control Path: •Be directly converted as follow: Phase Noise Measurement: L Note: due to the transfer 1/ f 3 -30dB/decade function effect 2 1/f -20dB/decade 1 10log FkT 2 P Zin 1 1 s Z (0 ) GL 1 j 2Q 1/ f 3 o log 2Q L 0 vout (o w) H (o w) 1 o j (after closed-loop) I in (o w) 1 H (o w) GL 2QL 1 H ( ) in / f 2 2 V 2 0 2 L{} 10 log noise 10 log 2 10 log[ 2 FkT ] 2 Vsig 1 Vo 2 Ps 2Q 2 Leeson’s Equation: 2 FkT 1 / f 3 2 L 10 log 1 2Q 1 0 Ps L where LΔω the phase noise @ Δω offset k the Boltzmann' s constant T the absolute temperature Ps the signal power QL the loaded Q ω1/f 3 the corner frequencyof 1/f 3 F a fitting parameter Noise_Power Tradeoff: V2 P I 2R I* N I R Pnoise N Pnoise S/N increases. Effect of Frequency Division and Multiplication on Phase Noise: •Divider contributes the noise much less (can be neglected); •Phase noise are also decreased by N factor. •From narrow band FM approximation, the phase noise power is divided by N2. •Frequency multiplication raises the phase noise magnitude by the same factor. Divide-by-two : 20 log(2-1 ) 6dB (divider, enhancement) 20 log(21 ) 6dB (multiplie r, degradation) Pushing & Pulling Effects: [Injection pulling by an interference] •Power Supply : pushing effect •Load / Interference : pulling effect •Both effects cause the frequency shift. •In general, pulling effect slows down the oscillation. •For VCO, the regulator LDO is necessary! Pulling by Interference in Rx: Pulling by PA (Load Variation) in Tx: [to be continued] Oscillator Types and Features : (a) Negative-Gm / LC-resonant oscillator (b) Interpolative oscillator (two oscillators) (c) Relaxation oscillator / ring oscillator (d) Standing Wave Oscillator (a) LC-tuned: -R Colpitts using active buffer! Oscillator Types and Features : (cont.) •Capacitive divider •Optimized at the current level where the transistor noise is lowest; but still can optimized with the largest voltage swing! Oscillator Types and Features : (cont.) Oscillator Types and Features : (cont.) * Push-Push (2x Harmonic) Oscillator 2x fosc PN: -97 dBc/Hz @ 1MHz (reg.) -102 dBc/Hz @ 1MHz (Micro.) Oscillator Types and Features : (cont.) •Parasitics •Q-factor degrades Oscillator Types and Features : (cont.) (b) Interpolative Oscillator: •Wide tuning range; •Poor phase noise, in general case. Overall transfer function: H(s)=α1H1(s) + α2H2(s) Oscillator Types and Features : (cont.) (b) Interpolative Oscillator: Oscillator Types and Features : (cont.) (c) Ring & Relaxation Oscillators: •Odd stages (single end) •Odd and Even (differential) Oscillator Types and Features : (cont.) (d) Wave-Based Oscillator: Millimeter-Wave Applications Quadrature Signal Generation: Importance : image-rejection; SSB Mixing Div-by-2n; Div-by-2n+1 ? An new example, LO generator: Let f = 1,350 (MHz), 1,350 x 2 / 3 = 900 MHz 1,350 x 4 / 3 = 1,800 MHz Quadrature Signal Generation: •Havens’ Technique: •RC-CR: Quadrature Signal Generation: (cont.) •Frequency Division: •Div-by-two, 50 % duty cycle naturally. •Easy to implement 2N divider. Quadrature Signal Generation: (cont.) •Frequency Division: •Div-by-3, important to UWB application. •Challenge: to build 50% duty-cycle, quadrature outputs. Basic Unit Cell: current-switched D-type flip-flop. Important References for div-by-three circuits: 1. J.-R. Yuan and C. Svensson, “Fast CMOS Nonbinary Divider and Counter”, Electronics Letter, vol.29, no.13, pp.1222-1223, June 1993. 2. R. Magoon and A. Molnar, “RF Local Oscillator Path for GSM Direct Conversion Transceiver with True 50% Duty Cycle Divide by Three and Active Third Harmonic Cancellation,” in IEEE Radio Frequency Integrated Circuits symposium, pp.23-26, June 2002. 3. http://www.rfdesign.com/ ; “Frequency divider design strategies,” by Louis Fan Fei, Broadband Technology, pp.18-26, March 2005. 4. S.-C. Tseng, Chinchun Meng, and W.-Y Chen, “True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers,” IEICE Trans. Electron., vol.E89-C, no.6, June 2006. 5. C.-F. Liang, S.-I. Liu, Y.-H Chen, T.-Y. Yang, and G.-K. Ma, “A 14-band Frequency Synthesizer for MB-OFDM UWB Application,” in IEEE Int. Solid-State Circuit Conference, 6.7, 2006. Patents: 1. Bo Sun, “Divide-by-three Circuit,” US Patent NO. 6,389,095. 2. S. J. Clendening and T. D. Adams, “Divide by Three Clock Divider with Symmetrical Output,” US Patent NO. 4,366,394. •Differential type Div-by-3 •Frequency Division: (div-by-3, 50% duty cycle, differential) •Frequency Division: (div-by-3, 50% duty cycle, quadrature ! ) Concept: Phase alignment Is necessary! Quadrature Divide-by-Three: Timing Diagram: 66% 66% Div-by-3 66% Duty Cycle 50% Delay Generator AND gate 50% duty-cycle, div-by-three circuit: A new Quadrature 50% duty-cycle, Divide-by-Three circuit using TSPC technique: A A B B A B A B B A A New Quadrature Div-by-3 Circuit using TSPC technique: (cont.) • Experiments: a. Original [1]; b. Self-link; c. Cross-link c. a. b. 1. Cross-links between I – IB and Q – QB : 30° phase difference! Input clock Differential pair (ref. clock) Differential pair (lagging 30°) 2. Under Correct Connection: Timing Diagram at each inter-stage node: Input clock 33.3% Pulse width 66.7% Pulse width 50% Pulse width 3. Under Correct Connection: Timing Diagram at each output node: 120.58 Differential pair (ref. clock) 115.64 135.44 120.58 – 115.64 (s) ________________ Differential pair 135.44 – 115.64 (s) (lag/lead 90°) ≒ 25% 3. Under Correct Connection: Timing Diagram at each link node: Input link Waveform 33.3% @ I-block @ IB-block @ Q-block 66.7% @ QB-block Single-Side Band (SSB) Generation: cos A cos B 1 cos(A B) cos(A B) 2 sin A sin B cos(A B) cos(A B) 1 2 •Three SSB Mixers; •3,168 MHz x 2 = 6,336 MHz [the end]