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A New Family of Soft-Switching DC-DC PWM Converters Using a True

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					                   A New Family of Soft-Switching DC-DC PWM Converters
                          Using a True ZCZVT Commutation Cell

                                         Hélio L. Hey and Carlos M. de O. Stein
                                               Federal University of Santa Maria
                                                     UFSM - CT - DELC
                                            97105-900 - Santa Maria - RS - BRAZIL
                                                  hey@pequim.ctlab.ufsm.br

Abstract – In this paper is introduced a new family of DC-DC        II. A FAMILY OF DC-DC ZCZVT PWM CONVERTERS
PWM converters using a true Zero Current and Zero Voltage
Transition (ZCZVT) commutation cell. The soft-switching             A. Common Equivalent Circuit of DC-DC PWM Converters
technique utilized provides Zero Current Switching (ZCS) and           An common equivalent circuit of DC-DC converters was
Zero Voltage Switching (ZVS) simultaneously, at both turn-on        proposed in [9] and it is shown in Fig. 1.a. It represents all
and turn-off of the main switch and ZVS for the main diode. The     types of non isolated DC-DC converters, which are obtained
family of ZCZVT PWM converters is obtained from an common           by connection of the input (Vi) and output (Vo) voltage
equivalent circuit of ZCZVT PWM converters and the ZCZVT
                                                                    sources and the smoothing capacitor C, when it exists. The
PWM boost converter is analyzed, simulated and implemented.
It is demonstrated the construction of state-plane diagram,
                                                                    connection scheme of these elements is shown in Fig. 1.b. In
which is obtained by using a proper state variable                  the case of buck, boost and buck-boost converters, where the
transformation. Based on the commutation analysis and the           c terminal is not connected, the L1 inductor can be suppress.
relations between the most important circuit parameters, it is         a                                          a
                                                                                                                                       Components Connection
presented a design guidelines and a design example.
Experimental results are presented, taken from a laboratory                   S
                                                                                                                                                       Vi          Vo      C
prototype rated at 1 kW, input voltage of 155 V, output voltage                                 L
                                                                                                                  b             Buck                   a-d         b-d      
340 V and operating at 40 kHz. The measured efficiency at full
                                                                                                L1                              Boost                  a-b         a-d      
load was 97.9 %.                                                                                                  c
                                                                                                                              Buck-boost               a-b         b-d      
                                                                                                                                 Cúk                   a-b         c-d     a-d
                                                                              DRL
                    I. INTRODUCTION                                                                                             Sepic                  a-b         c-d     a-c
                                                                                                                                 Zeta                  a-b         c-d     b-d
   A wide variety of soft-switching techniques have been               d                                          d
proposed to improve the energy conversion efficiency of the                               (a)                                (b)
PWM converters. These techniques consist in to become                             Fig. 1. Equivalent circuit of DC-DC PWM converters.
possible Zero Voltage Switching – ZVS and/or Zero Current                            (a) Circuit; (b) Components connection scheme
Switching – ZCS on the power semiconductors devices [1-8].          B. ZCZVT PWM Commutation Cell
   The choice of the soft-switching technique, i.e., ZCS or            The ZCZVT PWM commutation cell proposed in [10], is
ZVS, it taken into account the technology of the                    shown in Fig. 2. It is composed by two resonant capacitors
semiconductor device that will be used. For example, Power          CR1 and CR2, a resonant inductor LR, a bi-directional auxiliary
Mosfet presents a better performance when is commutated             switch SA-DA1 and two auxiliary diodes DS and DA2 form this
under ZVS, since it exhibits turn-on capacitive losses when         auxiliary circuit.
operating in ZCS increasing the switching losses and EMI. On                                                                                 x
the other hand, the IGBT presents better results when is                               a1
commutated under ZCS, which can avoid its lathup and the                                                  +
turn-off losses caused by its tail current.                                                  DS               CR2
                                                                                                                                             +
                                                                                                                                                 CR1
   In [10] was proposed a ZCZVT commutation cell applied a                                                              SA
                                                                                                                                 LR
PWM boost converter. This cell provides ZCS and ZVS                                    a2                                                                     a3
                                                                                                                                                 DA2
simultaneously, at both turn-on and turn-off of the main                                                              DA1
switch and ZVS for the main diode. The shunt resonant                                        Fig. 2. ZCZVT PWM Commutation Cell.
network of the ZCZVT commutation cell is placed out the             C. Equivalent Circuit of ZCZVT DC-DC PWM Converters
power path and therefore, there is no voltage stresses on
                                                                       Figure 3 shows the equivalent circuit of ZCZVT DC-DC
power semiconductor devices. Furthermore, it is activated
                                                                    PWM converters, which is achieved by incorporation of the
during the main switch transitions only and is composed by
                                                                    ZCZVT commutation cell, shown in Fig. 2, in the equivalent
fewer auxiliary devices, rated at small power.
                                                                    circuit of DC-DC PWM converters, shown in Fig. 1.a.
The aim of this paper is to introduce a family of DC-DC                       a                                                                                     a
PWM converters using the ZCZVT commutation cell                                                               +                          x
                                                                                                                                                               ZCZVT
                                                                                                     DS               CR2
proposed in [10]. The generation of this family is presented in                                                             SA
                                                                                                                                  LR     +
                                                                                                                                             CR1             commutation
                                                                                            S                                                                   cell
section II. In section III is obtained the state plane diagram of                                                       DA1                      DA2
the ZCZVT boost converter, using a proper state variable                                                                          L
                                                                                                                                                                    b
transformation. The commutation analysis is presented in                                                                          L1
section IV. Design guidelines and a design example are                                                                                                              c

presented in section V. In section VI are presented the                                     DRL
simulation and experimental results, taken from a laboratory
prototype rated at 1 kW, input voltage of 155 V, output                       d                                                                                     d
voltage 340 V and operating at 40 kHz. The measured                         Fig. 3. Equivalent circuit of DC-DC ZCZVT PWM converters
efficiency at full load was 97.9 %.                                        The family of ZCZVT PWM converters is obtained using



0-7803-4503-7/98/$10.00       1988 IEEE                         1030
the connection scheme shown in Fig. 1.b. The x terminal can
                                                                                                                                                                                                                LR ,      LR
be connected in the input voltage source, in the output voltage                                                                           Zx                     Stages                                Z1 =          Z2 =
source or in the common point between them. The operation                                                                                 Z1            1, 2, 3, 7, 8, 9 and 10                                 CR1       CR 2
of these configurations differs only by the voltage across the                                                                            Z2              4, 5, 6, 12 and 14
                                                                                                                                                                                                              LR ,       C R1C R 2
resonant capacitor CR1. Figure 4 shows the configuration of                                                                               Ze                  11 and 13                            Ze =            Ce =
                                                                                                                                                                                                              Ce        C R1 + C R 2
ZCZVT DC-DC PWM converters obtained by the connection
of the x terminal in the input voltage source.                                                                                        To illustrate the procedure used for the obtainment of the
               DS          +
                            CR2 S                   C                            DS      +
                                                                                            CR2 S               C                  state variable transformation, normalization and equations for
          S                       A LR             + R1                                           A LR         + R1
                                                                            S                                                 Vi
                                           L
                                                                                                                                   each circuit stage, will be utilized the stage 4 (t3, t4).
Vi                             DA1                   DA2             Vo                      DA1         L         DA2
                                                                                                                                   A. State Variable Transformation and Normalization of the
      DRL                                                       Vo         DRL                                                        Initial Conditions:
                                                                                                                                                                         i L (t 3 ) I
                                     (a)                                                           (b)                                                     in (t 3 ) = R           = in = 1               (5)
           DS         +
                       CR2 S                    CR1                        DS     +
                                                                                      CR2 S               C                                                                 I in    I in
                             A LR                                                           A LR         + R1

                                                                                                                                                          vC (t 3 ) − vC (t 3 ) V − V
      S                                        +            Vi        S                                                  Vi

                                                                                                                                               vn (t 3 ) = R 2
                          DA1          L           DA2                                DA1          L         DA2
                                                                                                   L1                         C
                                                                                                                                                                               R1
                                                                                                                                                                                     = o          i
                                                                                                                                                                                                    = Vn′ (6)
 DRL                                                        Vo                                                                                                       I in Z x            I in Z 2       3

                                                                     DRL                                                 Vo        where Vn′ is the normalized voltage in the instant t3 and Z2 is
                                                                                                                                                    3

                                     (c)                                                           (d)                             the characteristic impedance of the stage 4.
          DS      +
                    CR2 S                   C                              DS     +
                                                                                      CR2 S               C                        B. Current normalization.
 S                        A LR             + R1            Vi         S                     A LR         + R1            Vi
                                     L
                                                                 C
                                                                                                   L
                                                                                                                                      The equation (7) defines the resonant inductor current
                      DA1                      DA2                                    DA1                    DA2
                                     L1                                                            L1                              during the stage 4 and is given by:
                                                                                                                                                       diL (t ) vC (t ) − vC (t )
DRL                                                        Vo        DRL                                                 Vo
                                                                                                                              C                           R
                                                                                                                                                               = R2         R1
                                                                                                                                                                                        (7)
                                                                                                                                                         dt            LR
                      (e)                                    (f)
                      Fig. 4. DC-DC ZCZVT PWM converters                                                                                                                         L   Iin                  DRL
           (a) Buck; (b) Boost; (c) Buck-boost; (d) Cúk; (e) Sepic; (f) Zeta                                                                                                      SA
                                                                                                                                                                    DA2              LR
           CONSTRUCTION OF THE STATE PLANE
           III.
                                                                                                                                                                        + DA1                 S           + CR2
                           DIAGRAM
                                                                                                                                                               Vi        CR1                           DS                 Vo
   To analyze the operation of the proposed ZCZVT DC-DC
PWM converters was selected the ZCZVT PWM boost
converter. Figure 5 shows the ZCZVT PWM boost converter                                                                                                        Fig. 5. ZCZVT PWM boost converter.
represented in the conventional topological form. It differs
                                                                                                                                                Iin                                     Iin                                       Iin
from the boost converter presented in Fig. 4.b only by the
components placement. The operation stages are represented                                                                                                                            SA          LR                      DA2 SA        LR
                                                                                                                                                                 DRL
in Fig. 6. A complete analysis of the operation principles of                                                                      Vi
                                                                                                                                                                 Vo                + C                    DRL V                                DRL
                                                                                                                                                                            Vi        R1                       i
this converter was presented in [10] and will be suppressed in                                                                                                                                            Vo s                                 Vo
this paper.                                                                                                                              stage 1 - t0, t1                          tage 2 - t1, t2                         stage 3 - t2, t3
   Since the ZCZVT commutation cell contains three reactive                                                                                     Iin                                     Iin                                       Iin
components (CR1, CR2 and LR), during one switching cycle                                                                                DA2 SA           LR                      DA2 SA           LR                      DA2 SA        LR
there are three resonant frequencies and third order equations
                                                                                                                                                              + C
[10]. Therefore, the state plane analysis of these converters by                                                                   Vi                            R2 Vi                                    DS         Vi                       S
conventional techniques are difficult and so that, the state                                                                                                                                                    s
                                                                                                                                         stage 4 - t3, t4                          tage 5 - t4, t5                         stage 6 - t5, t6
plane will be obtained using a proper state variable
                                                                                                                                                Iin                                     Iin                                       Iin
transformation. A similar analysis applied to a multi-resonant
converters was reported in [11].                                                                                                            DA1          LR                                                                      SA     LR
   The state variable transformation is done considering as the                                                                                                             Vi                            S
                                                                                                                                          + C                                                                                  + C            S
                                                                                                                                   Vi        R1                 S                                                    Vi           R1
state variables, the inductor resonant current and the                                                                                                                                                          s
difference between the voltage of the resonant capacitors as                                                                             stage 7 - t6, t7                          tage 8 - t7, t8                         stage 9 - t8, t9
follows:                                                                                                                                        Iin                                     Iin                                       Iin
                            i(t ) = iL (t )                 (1)                                                                                SA        LR                           SA          LR                      DA2 SA        LR
                                      R

e                   v(t ) = v C (t ) − v C (t )             (2)                                                                           + C                                      + C                 + C                                   + C
                                R2          R1                                                                                     Vi        R1                 DS          Vi        R1                  R2         Vi                         R2

  The normalization is done with base in the input current Iin                                                                                                                                                  s
                                                                                                                                        stage 10 - t9, t10                        tage 11 - t10, t11                      stage 12 - t11, t12
and the generic characteristic impedance Zx as follows:
                                                                                                                                                                      Iin                                      Iin
                                i ( t ) i LR ( t )
                     i n (t ) =        =                (3)                                                                                                         DA1      LR
                                 I in      I in                                                                                                                                               Vi                          + C
                                                                                                                                                                                                                             R2
                                                                                                                                                               + C                + C
                       v(t ) v CR 2 (t ) − v C R1 (t )
                                                                                                                                                        Vi        R1                 R2

                               =      v n (t ) =       (4)
                                                                                                                                                             stage 13 - t12, t13
                                                                                                                                                                                                                                  s
                      I in Z x       I in Z x                                                                                                                                                          tage 14 - t13, t0
  The value of the generic characteristic impedance Zx
depends on the reactive components enveloped in each stage.                                                                                 Fig. 6. Operation stages of ZCZVT PWM boost converter.
Then:                                                                                                                              Then, this normalized current is:



0-7803-4503-7/98/$10.00                                          1988 IEEE                                                     1031
                  din (t ) d iLR (t ) vC R 2 (t ) − vC R1 (t )                                                    plane diagram of the ZCZVT boost converter as shown in Fig.
                          =               =                                    (8)                                7. The discontinuous jumps in the normalized voltage are
                    dt       dt I in                 I in LR
                                                                                                                  caused by changes in the values of the characteristic
Substituting ( 4 ) in ( 8 ):                                                                                      impedance Zx. In the state plane diagram, the normalized
                              din (t ) vn (t )Z 2                                                                 equations represents a point, when the input filter inductor is
                                         =                                     (9)
                                 dt            LR                                                                 adding/transferring energy from/to load, a straight, when the
C. Voltage Normalization.                                                                                         resonant inductor LR or the resonant capacitor CR2 are be
   The equations (10) and (11), define the voltage across the                                                     charging or discharging linearly, or a semi-arc, when the stage
resonant capacitors and are given by:                                                                             is resonant.
                                 dvC (t )
                                       R1
                                              =0                             ( 10 )
                                      dt
                          dvC ( t ) Iin − i L ( t )
                               R2
                                        =          R
                                                                             ( 11 )
                              dt                CR 2                                                                                   t4

Then, the normalized voltage is given by:
        dv n (t ) d  v CR2 (t ) − v CR1 (t ) I in − i LR (t )
                 =                              =                      − 0 ( 12 )                                                    t5                t10                       t9                                    t3
           dt       dt         I in Z 2        
                                                         C R 2 I in Z 2                                                                                                                                            t2


Substituting ( 3 ) in ( 12 ):                                                                                                Ce
                              dvn (t ) 1 − in (t )
                                                                                                                                                 t11
                                                                                                                             CR2
                                         =                                   ( 13 )                                     in
                                                                                                                                            t6     t12                             t13
                                 dt         CR 2 Z 2                                                                                                                                                     t 7, t 8            t 0, t 1

D. Stage Equation.
   The equation that define the stage 4 is obtained by division
   of ( 9 ) by ( 13 ), as follows:
   din (t )      v (t )     or (1 − in (t ) ).din (t ) = vn (t ).dvn (t ) ( 14 )
            = n
   dvn (t ) 1 − in (t )
                                                                                                                                                                  vn
   By mathematical manipulation and substituting the initial
                                                                                                                        Fig. 7. State plane diagram of the ZCZVT PWM boost converter.
values, the equation (14) can expressed by (15), which define
the stage 4.                                                                                                                   IV. COMMUTATION ANALYSIS
                            vn + (in − 1) = Vn′
                               2             2          2
                                                                     3
                                                                             ( 15 )                               A. Main Switch
   The equations of each operation stage can be obtained                                                             In order to achieve commutation under ZVS and ZCS
using the same procedure, which are shown below.                                                                  simultaneously for both turn-on and turn-off of the main
Stage 1(t0, t1):   in (t ) = 0        vn (t ) = Vn  ( 16 )                                                        switch S is necessary that the diode DS is conducting during
                                                  1
                                             2           2                   2                                    these commutations. To assure this condition, some
Stage 2(t1, t2):                         vn + in = Vn                                                    ( 17 )
                                                                         1                                        restrictions must be guaranteed.
Stage 3(t2, t3):                   i n = I n + V n ω 1 (t − t 2 )                                        ( 18 )   - Main Switch Turn-on: As shown in Fig. 8, the condition
                                            2                2
                                                                                                                  mentioned above is guaranteed if the normalized resonant
                                     vn + (in − 1) = Vn′
                                        2                        2                       2
Stage 4(t3, t4):                                                                 3
                                                                                                         ( 19 )   inductor current is greater than unity at the end of stage 4.
Stage 5(t4, t5):                   i n = I n + V n ω 2 (t − t 4 )                                        ( 20 )   This condition can be expressed as follows:

                                                                                                                                                                       (                     )
                                            4                4                                                                                                                                   2

                                    i n = 1 + V n ω 2 (t − t 5 )                                                                                         Vn′ 2 = I n − 1                                 + Vn                2
Stage 6(t5, t6):                                                                                         ( 21 )                                                                                                                             ( 30 )
                                                      4                                                                                                      3                 4                                         4


Stage 7(t6, t7):
                                            2
                                        vn + i
                                                       2
                                                                 = Vn′
                                                                             2
                                                                                                         ( 22 )   isolating I n :                      I n = Vn′ 2 − Vn                              2
                                                                                                                                                                                                              + 1≥ 1                        ( 31 )
                                                     n                   6                                                         4                     4                 3                 4

Stage 8(t7, t8):          in (t ) = 0                                vn (t ) = Vn                        ( 23 )   then:                                            Vn′ ≥ Vn                                                                 ( 32 )
                                                                                             8
                                                                                                                                                                           3                 4
                                            2            2                   2
Stage 9(t8, t9):                        vn + in = Vn                                                     ( 24 )        Substituting the normalized voltages Vn′ and Vn in (32), is
                                                                         8
                                                                                                                                                                                                          3                             4
                                                 2           2                   2
Stage 10(t9, t10):                          vn + in = Vn                                                 ( 25 )   defined the following restriction:
                                                                             8
                                                     2                                               2                                         Vo ≥ 2Vi                                                                                     ( 33 )
                             C                 C 
Stage11(t10,t11): vn +  in − e  = Vn′ + 1 − e 
                    2                      2
                                            C                                                        ( 26 )
                            CR 2      10
                                                  R2 
                                                                                                                  or                           kv ≥ 2                      ( 34 )
Stage 12(t11, t12):   vn + (in − 1) = Vn′ + I n − 1
                        2           2
                                        11
                                           2
                                               11
                                                     2
                                                                                     (           )       ( 27 )   where                       kv =
                                                                                                                                                    Vo
                                                                                                                                                    Vi
                                                                                                                                                                           ( 35 )
                                                             2                                       2
                                           C                 C                                                represents the DC voltage ratio of the converter.
Stage 13(t12, t13): Vn′            +  in − e  = Vn′ +  e 
                               2                           2
                                                             C                                       ( 28 )
                          11
                                           CR 2       12
                                                                R2                                              - Main Switch Turn-off: As shown in Fig. 9, the main switch
Stage 14(t13, t0):                    v n = Vn′ + ω 2 (t − t14 )
                                                     ( 29 )                                                       turn-off under ZCS and ZVS is achieved if the diode Ds is
                                13
                                                                                                                  conducting during the stage 10. The existence of the stage 10
   Vn and I n are the normalized voltage and the normalized                                                       is guaranteed if the normalized resonant capacitor voltage is
      i         i
current in the instant ti respectively, and Vn′ is the normalized                                                 greater than zero at the end of stage 9. This condition can be
                                                                                     i                            expressed as follows:
voltage in the instant ti referred to the characteristic
                                                                                                                                                                 Vn′ = Vn                    2
                                                                                                                                                                                                     +1                                     ( 36 )
impedance of the stage (i+1).                                                                                                                                      6                     9
  Using these equations is possible to construct the state



0-7803-4503-7/98/$10.00                      1988 IEEE                                                        1032
isolating Vn :                                    Vn = Vn′ 2 − 1 ≥ 0                                       ( 37 )   ratio between the resonant capacitors CR2 and CR1, as function
                 9                                   9                      6                                       of parameter kc1 for a given value of voltage ratio kv, which
then:                                                             Vn′ ≥ 1                                  ( 38 )   assure the existence of stage 13. In Fig. 10 is shown a graph
                                                                        6
                                                                                                                    that define the mean value to the ratio between the resonant
  Substituting the normalized voltage Vn′ in (38), results:                                                         capacitors CR2 and CR1 ratio, named kc2, as a function of the
                                                                                     6
                                                            V                                                       kc1 and kv parameters.
                                                        Z1 ≥ i                                             ( 39 )
                                                            Iin                                                            V. DESIGN GUIDELINES AND EXAMPLE
                                                                                     2
                                                         I                                                           In this section, a design procedure and an example to
or:                                             CR1 ≥ LR  in max                                         ( 40 )   determine the component values of the proposed ZCZVT
                                                          Vi min 
                                                                                         2                          PWM boost converter is given.
                                     I                                                                            a) The input specifications consists of :
                        CR1 = kc1 LR  in max          ( 41 )
                                      Vi min                                                                         Output Power                            Po = 1000 W
where Iin max is the maximum value of the input inductor filter                                                        Output Voltage                          Vo = 340 V
current, Vi min is the minimum value of the input voltage                                                              Input Voltage                           Vi = 155 V (± 10%)
source and kc1 ≥ 1 is a factor that guarantee the                                                                      Approximate efficiency                  η ≥ 95 %
                                                                                                                       Ripple of the input filter inductance   ∆IL% = 50 %
inequality ( 38 ).
                                                                                                                    b) DC voltage conversion ratio: from the input specifications
                                                                                                                       it is possible to obtain the DC voltage conversion ratio,
        (Vn4   , In
                   4   )                                                                                               which is given by:
                                                                                                                                                    V     340
                                                                                                                                               kv = o =       ≈ 2.2           ( 42 )
                 t4
                                                             Vn′
                                                                                                                                                     Vi 155
                                      Vn′                         3
                                        3
                                                                                                                    c) From the output power and output voltage, is defined the
          In − 1
            4
                                                                                               (V ′ , 1)
                                                                                                   n3
                                                                                                                       output current:
                                Vn
                 t5               4                                                                                                              P 1000
                                                                                              t3                                           Io = o =        = 2.94 A           ( 43 )
                                                                                                                                                Vo     340
                                                                                                                    d) The output diode: Taking into account the output current
                                                                                                                       and voltage was chosen the hyperfast RHRP870 (700 V, 8
                 t6                                                                                                    A) from Harris Semiconductor, which present a reverse
  in
                                                                                                                       recovery time of 65 ns for a current of 8A and
                                                        vn                                                             di = 100 A .
         Fig. 8. Partial State plane diagram – stages 4, 5 and 6.                                                         dt         µs
                                                                            (V , 1)
                                                                                n9
                                                                                                                    e) The resonant inductance LR: It is calculated to control the
                                            t10                       t9                                               di/dt rate and therefore, to minimize the reverse recovery of
                                                         Vn                                                            the output diode. This value was chosen equal to 40 A µs ,
                                                              9

                                                                                                                       and then:
                (V ′ , 0)
                  n6
                                                    1             Vn′
                                                                       6
                                                                                                                                       Vo − Vi min 340 − (0.9 ⋅ 155 )
                                                                                                                               LR =                =                     ≈ 5 µH ( 44 )
  in                                                                                                                                       di              40 ⋅ 10 6
                           t6                                                        t7, t8                                                   dt
                                       Vn′                                                                          f) From the input specifications is defined the input current
                                            6

                                                                                                                       value, as follows:
                                                                                                                                               P      1000
                                                                                                                                       I in = o =                = 6.79 A       ( 45 )
                                                                                                                                              ηVi 0.95 ⋅ 155
                                                                                                                    g) Maximum DC input current: Taking into account the
                                                                                                                       minimum input voltage and the ripple of the input filter
                                                     vn
        Fig. 9. Partial State plane diagram – stages 7, 8, 9 and 10.                                                   inductance is defined the maximum value of DC input
                                                                                                                       current, as follows:
B. Auxiliary Switch                                                                                                                                    1000
                                                                                                                                  I in max = 1.25                    = 9.43 A   ( 46 )
- Auxiliary Switch Turn-on: As presented in [10], the auxiliary                                                                                   0.95 ⋅ (0.9 ⋅155)
switch is activated two times by period. The auxiliary switch                                                       h) The resonant capacitance CR1: choosing kc1 = 1.3 and from ( 41
turn-on under ZCS is achieved without restrictions, thanks to
the presence of the resonant inductor LR in series with this                                                           ), the CR1 value is defined by:
                                                                                                                                                               2
switch.                                                                                                                                                 9.43 
- Auxiliary Switch Turn-off: On the other hand, to achieve the
                                                                                                                                 C R1 = 1.3 ⋅ 5 ⋅10 −6              = 29.7 nF   ( 47 )
                                                                                                                                                        0.9 ⋅155 
auxiliary switch turn-off under ZCS and ZVS, the auxiliary
                                                                                                                       Commercial value utilized: 33 nF. Therefore, kc1 = 1.44 .
diode DA1 must be conducting during these commutations. To
the first turn-off, this condition is satisfied if the stage 7                                                      i) The resonant capacitance CR2: with the values of the kc1
exists. Since this stage always occur in a normal operation                                                            and kv, from Fig. 10 the kc2 value is equal to 1.05. Then:
there isn’t any restriction. To the second turn-off, is necessary                                                              C R 2 = k c 2 C R 2 = 1.05 ⋅ 33 ⋅ 10 −9 = 34.65 nF ( 48 )
that the stage 13 exists. Unfortunately, due the complexity of                                                         Commercial value: 33 nF. Then, k c 2 = 1 .
the equations, a close-form solution that guarantee the
existence of stage 13 cannot be found analytically. By several
simulations of the converter in the Matlab software and
using an iterative process, was obtained a boundary values to



0-7803-4503-7/98/$10.00                                  1988 IEEE                                              1033
         1.7
                                                                                                                                      m) The active switches: the active switches were implemented
         1.6
                                                                                                                                        with a UFS (UltraFast Switches) series IGBTs from Harris
         1.5
         1.4
                                                                                                                                        Semiconductor, which present built-in an anti-parallel
                                                                              CR2
         1.3
                                                                     k c2 =                                                             hyperfast diodes. The main switch was a HGTP7N60C3D
                                                                              C R1
         1.2
                                                                                                                                        (600 V, 7 A) and the auxiliary switch was a
                                                                                                                                        HGTP3N60C3D (600 V, 3 A).
  kc2 1.1
         1.0
         0.9
                                                                                                                                                   VI. EXPERIMENTAL RESULTS
         0.8                                                                                                     kv=2.0                  Following the design example shown in preceding section,
                                                                                                                 kv=2.2
         0.7                                                                                                     kv=2.5               a 40 kHz, 1 kW ZCZVT PWM boost converter prototype has
                                                                                                                 kv=3.0
         0.6                                                                                                     kv=4.0               been implemented to verify the feasibility of the proposed
         0.5
            1.0        1.1     1.2   1.3        1.4      1.5       1.6     1.7         1.8         1.9         2.0
                                                                                                                                      ZCZVT PWM converters. The power stage circuit is shown in
                                                       kc1                                                                            Fig. 12.
               Fig. 10. Average relation between two resonant capacitors.                                                                Figure 13 shows the experimental waveforms. They
                                                                                                                                      confirm the previously mentioned analysis. As can be seen in
j) Maximum switching frequency: It is interesting that the
                                                                                                                                      Fig. 13.a, the commutations of the main switch S occur truly
   sum of the resonant time intervals involve a small fraction
                                                                                                                                      without losses, i.e., under ZCS and ZVS simultaneously. It is
   of the switching period. By simulations realized in Matlab
                                                                                                                                      a very interesting feature of this proposed ZCZVT
   software, with the calculated parameters, this sum is equal
                                                                                                                                      commutation cell. The maximum voltage of the main switch
   to 4.1697 µs. In this example design this sum has been                                                                             is equal to the output voltage.
   defined equal to 20 % of the switching period. Therefore,                                                                                                              L                        RHRP870
   the maximum switching frequency is given by                                                                                                                           1 mH
                                                                                                                                                                                SA                     D
                            20                                                                                                                         RHRP870                       LR
              fC ≤                        = 47965 Hz
                   100 ⋅ 4.1697 ⋅ 10− 6     (              ( 49 )
                                                                     )                                                                                      DA2
                                                                                                                                                                    HGTP3N60C3D
                                                                                                                                                                                             S

   The switching frequency was assumed equal to 40 kHz.                                                                                          Vi          CR1                                       CR2
                                                                                                                                                                                                                      Cf       RL
                                                                                                                                                                                                                    330 µF
k) Effective duty cycle: The effective duty cycle can be                                                                                                                      HGTP7N60C3D
   defined as the fraction of the switching period which the
   main switch is conducting. Without taking into account the
   converter losses, the effective duty cycle of the converter is
                                                                                                                                                                         Fig. 12. Power stage circuit.
   given by:
                                                                                                                                         Figure 13.b shows that the auxiliary switch SA is turned
                                        F 1
                              De = 1 − −                   ( 50 )                                                                     on under ZCS and turned off under ZCS and ZVS. Since
                                        T kv                                                                                          the resonant inductor LR control the di/dt rate of the output
    where F is the sum of the time of the resonant stages                                                                             rectifier, it helps to minimize the reverse recovery losses of
    which the main switch is not conducting and is obtained                                                                           this diode. From Fig. 13.c, it can be seen that the maximum
    by Fig.11. Then:                                                                                                                  voltage of the output rectifier is equal to output voltage and
                          2.12 ⋅10 −6    1                                                                                            it is commutated under ZVS at turn-on and ZCS and ZVS
                 De = 1 −             −     = 0.46         ( 51 )
                           25 ⋅10 −6    2.2                                                                                           at turn-off.
   Using the approximate efficiency of the converter equal to                                                                            The experimental results show that the converter operate
    95 %, is possible to calculate the new effective duty cycle:                                                                      with very low ringings and with slow di/dt and dv/dt reducing
                               0.46                                                                                                   its EMI emission. Owing to this, in the breadboarded
                         De =        = 0.48                ( 52 )
                               0.95                                                                                                   converter was not necessary to use any clamped circuit.
         2.6


         2.5                                                                                                              kv=3.0           vS                                                           iL R
F (µs)                                                                                                                                                                                      vSA
         2.4
                                                                                                                                                                   iS
                                                                                                                          kv=2.5
         2.3
                                                                                                                          kv=2.2
         2.2                                                                                                              kv=2.0

                                                                                                                                            ZCS; ZVS                     ZCS; ZVS                ZCS                         ZCS    ZCS; ZVS
         2.1
                                                                                                                                                                                                             ZCS; ZVS

         2.0


         1.9
               1.0      1.1    1.2    1.3        1.4         1.5     1.6         1.7         1.8         1.9         2.0                                      (a)                                                (b)
                                                         kc1
                                                                                                                                          vDRL                                              vCR2
                              Fig. 11. Determination of the F factor.                                                                                                                                   iL R
l) Average and RMS current values: by simulation in the                                                                                                           iDRL
   Matlab software this values can be defined as follows:                                                                                                                                  vCR1
                     Component                   Average                 RMS Current                     Maximum
                                                Current (A)                 (A)                           Voltage
                                                                                                                                                      ZVS                 ZCS; ZVS
   Main switch S                                      4.8106                  7.2725                            Vo
   Diode DS                                           0.0939                  0.6080                           -Vo
   Auxiliary switch SA                                1.5080                  4.9511                     Vo − VC11                                            (c)                                                (d)
   Auxiliary diode DA1                                0.4454                  2.0310                                                           Fig. 13. Waveforms for the ZCZVT PWM boost converter.
   Auxiliary diode DA2
   Output diode DRL
                                                      1.0604
                                                      4.3806
                                                                              4.4970
                                                                              6.4164
                                                                                                          ( -2V )
                                                                                                     − Vo − VC11
                                                                                                             -V      o
                                                                                                                      i
                                                                                                                                                        (a) Main switch (S) voltage and current
                                                                                                                                              (b) Auxiliary switch voltage and resonant inductor current
   Resonant capacitor CR1                                                                                    -Vi                                    (c) Output diode (DRL) voltage and current
                                                                                                                                            (d) Resonant capacitors voltages and resonant inductor current
   Resonant capacitor CR2                                                                                    Vo
                                                                                                                                                        (scales: 100 V/div.; 5 A/div.; 2.5 µs/div.).
   Resonant inductor LR                               1.0627                  5.3515                           




0-7803-4503-7/98/$10.00                                 1988 IEEE                                                                  1034
   The measured efficiency of the boost converter with the                             semiconductor devices. Moreover, it is activated during
proposed ZCZVT commutation cell was equal to 97.9 % at                                 the switching transitions only;
full load (1 kW).
                                                                                      The
                                                                                     !" soft switching for all power semiconductor devices
           VII. TOPOLOGICAL VARIATIONS                                                is achieved. The main switch commutates under ZCS
   As can be seen in Fig. 13.a., there is a resonant peak                             and ZVS simultaneously at the both turn-on and turn-
current through the main switch S during the stage 7. Adding                          off. Thus, it is suitable for both minority and majority
an additional resonant inductor in series with the auxiliary                          carriers semiconductor devices applications such as
diode DA1, as shown in Fig. 14, the characteristic impedance                          Power Mosfets, IGBTs, MCTs, etc.. The auxiliary
of the stage 7 will be increased, reducing the resonant peak                          switch commutates under ZCS at turn-on and under
current through the main switch S [5]. Figure 15 shows this                           ZCS and ZVS at turn-off. The output rectifier
peak current reduction, obtained by simulation. The                                   commutates under ZVS and its reverse recovery is
simulation parameters are the same of the breadboarded                                minimized;
converter and the additional inductance value used was equal                          Taking into account the experimental results, the
                                                                                     !"
to 40 µH.                                                                             converters operate practically without ringings and with
   As reported in [5], the LA value is given by:                                      slow di/dt and dv/dt on power devices, which can
                         LA = LR (n 2 − 1)                ( 53 )                      reduce the EMI emission;
where n represents the resonant current peak reduction. In the                        The
                                                                                     !" converters are regulated by the conventional PWM
simulation results shown in the Fig. 15.b was used n = 3.                             technique at constant frequency;
   The drawbacks of this topological variation are the larger
component number, which increase the size and weight of the                           Among several soft-switching techniques presented in
                                                                                     !"
converter, and an increase at the time of the resonant stages,                        the literature, mainly the ZCS techniques, the proposed
which can represent a switching frequency reduction.                                  ZCZVS commutation cell is more attractive, and can be
                                   L        Iin        DRL                            implemented in any member of the PWM family.
                           DA2         SA   LR
                                                                                                        REFERENCES
                                 DA1 LA
                 Vi
                             +                    S    +
                                                            CR2   Vo           [1]  K. Wang, G. Hua and F. C. Lee, “Analysis, Design and
                                 CR1
                                                      DS                            Experimental Results of ZCS-PWM Boost Converters”, in
                                                                                    Proceedings of the 1995 IEEJ IPEC, pp. 1197-1202.
                                                                               [2] G. Ivensky, D. Sidi and S. Ben-Yaakov, “A Soft Switcher
            Fig. 14. Circuit of the first topological variation.                    Optimized for IGBT´s in PWM Topologies”, in Proceedings of
                                                                                    the 1995 IEEE Applied Power Electronics Conference, pp. 900-
     vS                                                vS
                                                                                    906.
                      iS                                               iS      [3] I. Barbi, J. C. Bolacell, D. C. Martins and F. B. Libano, “Buck
                                                                                    Quasi-Resonant Converter Operating at Constant Frequency:
                                                                                    Analysis, Design and Experimentation”, in Proceedings of the
                                                                                    1989 IEEE Power Electronics Specialists Conference, pp. 873-
                                                                                    880.
                                                                               [4] L. C. de Freitas and P. R. C. Gomes, “A High-Power High-
               (a)                                     (b)                          Frequency ZCS-ZVS-PWM Buck Converter Using a Feedback
                    Fig. 15. Main switch waveforms.                                 Resonant Circuit”, in Proceedings of the 1993 IEEE Power
                      (a) Without LA; (b) With LA                                   Electronics Specialists Conference, pp. 330-336.
               (scales: 100 V/div.; 5 A/div.; 2.5 µs/div.).                    [5] R. C. Fuentes and H. L. Hey, “An Improved ZCS-PWM
                                                                                    Commutation Cell for IGBT´s Applications”, in Proceedings of
                      VIII.             CONCLUSIONS                                 the 1997 IEEE Applied Power Electronics Conference, pp. 805-
                                                                                    810.
   A new family of soft-switching DC-DC PWM converters                         [6] G. Hua, E. X. Yang, Y. Jiang and F. C. Lee, “Novel Zero-
using a true ZCZVT commutation cell was proposed in this                            Current-Transition PWM Converters”, in Proceedings of the
paper. State plane construction technique and commutation                           1993 IEEE Power Electronics Specialists Conference, pp. 538-
analysis were presented. With base in these studies, a design                       544.
guidelines was proposed.                                                       [7] K. Chen and T. A. Stuart, “A Study of IGBT Turn-off Behavior
   To verify the feasibility of this commutation cell, it was                       and Switching Losses for Zero-Voltage and Zero-Current
applied to a PWM boost converter. A prototype of 1 kW                               Switching”, in Proceedings of the 1992 IEEE Applied Power
operating at 40 kHz, with an input voltage rated at 155V has                        Electronics Conference, pp. 411-418.
                                                                               [8] G. Hua, C. S. Leu, Y. Jiang and F. C. Y. Lee, “Novel Zero-
been built. The measured efficiency at full load was 97.9%.
                                                                                    Voltage-Transition PWM Converters”, in IEEE Trans. on Power
   The state plane construction technique applied show be a                         Electronics, vol. 9, no. 2, Mar. 1994, pp. 213-219.
helpful and simple tool, because is not necessary a previous                   [9] H. Irie, “ Resonant Switches in Common Equivalent Circuit of
knowledge of the state variable governing equations for each                        DC/DC Converters”, in Proceedings of the 1991 IEEJ IPEC,
circuit stage.                                                                      pp.362-368.
   The experimental results demonstrate what the design                        [10] C. M. de O. Stein and H. L. Hey, “A True ZCZVT
guidelines is adequate, guaranteeing the correct converter                          Commutation Cell for PWM Converters”, in Proceedings of the
operation.                                                                          1998 IEEE Applied Power Electronics Conference, pp. 1070-
   As shown by theoretical analysis and experimental results,                       1076.
                                                                               [11] C. Q. Lee, Rui Liu and Somboom Sooksatra, ”Nonresonant and
the main features obtained are as follows:
                                                                                    resonant coupled zero voltage switching converters”, in IEEE
    The
   !" ZCZVT PWM commutation cell is placed out of                                   Transactions on Power Electronics, vol. 5, no. 4, Oct. 1990,
    the main power path of the converters and therefore,                            pp. 404-412.
    there is no additional voltage stresses on power



0-7803-4503-7/98/$10.00                     1988 IEEE                       1035

				
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Description: Softswitch is a functional entity, in order to provide next generation network NGN service requirements of real-time call control and connection control functions, and control the next generation core network call. Simply look at, soft switching is of traditional PBX in the "call control" feature of entities, but the traditional "call control" feature is and the business together, the different business functions required for the different call control, and soft-switching nothing to do with the business, which requires softswitch provides call control function is the basic call control various operations.