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Analog integrated circuit design flow using cadence

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Analog integrated circuit design flow using cadence Powered By Docstoc
					            Analog Integrated Circuit Design Flow
                   (DK_90nm: 6.1 version)
Part 1: Hand calculation, schematic capture and simulation

                          IET, NTNU, Trondheim, Norway
                             (Last modified: Jan. 2008)
           Authors: Carsten Wulff and Linga Reddy C, and Trond Ytterdal
               Email: wulff@iet.ntnu.no and lingareddy@iet.ntnu.no




A few words before we start
An analog designer is a person with a high degree of knowledge in several different
areas. The two most important areas are “tools” and “theoretical know-how”. It is
extremely difficult to design an integrated circuit if one has no knowledge of “tools”.
The tools include SPICE, MATLAB, Maple, a schematic editor, a layout editor, DRC
and LVS tools, parasitic extraction tools and usually some linux/unix knowledge like
tcsh, BASH, AWK, PERL, sed or the like. It is possible to be an analog designer
without knowing any of these tools, but you won‟t get much done. In the course you
learn the necessary theoretical know-how, in this tutorial, and the project, you will be
introduced to the tools. Unfortunatly, it is not possible to learn the tools by reading
some document, the only way to learn is to spend some time fighting the tools. If you
have ever encountered electronic design automation (EDA) tools, you will know that
“fighting the tools” is the correct terminology. The tools are usually very expensive
and have an small audience, accordingly they do not have the same polish as more
mainstream software like “Firefox”. In addition, the focus is often on performance,
and not necessarily user interface, or ease of use. There are four software packages
that will be used in this tutorial
    1. Cadence Virtuoso – Schematic capture (drawing schematic) and Layout
    2. Mentor Graphics Eldo – SPICE simulation
    3. Mentor Graphics Calibre – Layout Versus Schematic (LVS) and Design Rule
        Check (DRC)
    4. Synopsys StarXT – parasitic extractor, extracts capacitance and resistance in
        routing and the like from layout
These tools are the same tools that the professionals use to design circuits, so when it
comes to tools, we have the best.

Our goal this year is to design, draw and simulate part of a telescopic operational
transconductance amplifier. This is a difficult task with a steep learning curve, so
we‟ll start relatively slow with a common source amplifier with resistive load. We‟ll
show you how to calculate the transistor values and do some other hand calculation to
get an estimate of the performance. But, most important in this tutorial is getting to
know the EDA tools and Linux. We should probably mention that most of the EDA
tools run on some form of Unix, ergo learning to use Linux is a good idea.



Questions you will have
You will have questions during this tutorial and during the project. You should try to
get answer in the following fashion
    1. Google
    2. Classmates
    3. The manuals for the application
    4. http://it.iet.ntnu.no
    5. The teaching assistant/professor

Make your home and fire up Cadence
If not already logged in, please log in on the Linux server sedna (sedna.iet.ntnu.no).
You‟ll        need     a    graphical      user    interface    (GUI),    so     read
http://it.iet.ntnu.no/ks_connecting if you don‟t know how to get a GUI.

The project directory for this tutorial is cadence_tut. Create the directory called
                                                     1
cadence_tut using the commands below in the terminal .


cd
mkdir cadence_tut
cd cadence_tut


Then perform the following commands:

1)
cp /eda/kits/cmos090.6.1/install/setup_working_dir/* .
cp /eda/kits/cmos090.6.1/install/setup_working_dir/.* .

2)
tcsh

3)
source .cshrc_cmos090

4)


1
  Or command prompt, or DOS window, or console. It‟s usually an icon that looks
like a black computer screen.
icfb &


The Cadence DFII framework should start with the CMOS090 process, if it does not
start please contact one of the authors. Steps 2-4 need to be repeated each time you
want to start Cadence.

Make a link to the CMOS090 design library with the command
ln –s /eda/kits/cmos090.6.1/DK_cmos090gp_7M2T_50A_6.1/DATA/ELDO/CORNERS \
 ~/cmos090eldo
This directory contains all models that the SPICE simulator Eldo needs to run
simulations with the 90nm design kit.

To setup your account for Eldo open a new terminal window and do the commands

echo "source /eda/etc/ams.2007.1" >> ~/.bash_profile
echo "export LM_LICENSE_FILE=1717@129.241.108.106 " >> ~/.bash_profile
source ~/.bash_profile
ezwave


If Ezwave pops up then everything is ready to go. You can see more information on
these commands at http://it.iet.ntnu.no/eda_adms.

Close everything, log-out and log-in again. This ensures that all the setup stuff is
loaded correctly.

We are almost ready to begin our analog design, the next steps are:

Tutorial I:
    Hand calculation
    Bias simulation
    Schematic capture of the design and verifying the desired performance
    SPICE/ELDO simulations
Tutorial II:
    Schematic driven / custom layout of the finalized schematic
    DRC (Design Rule Check) of the layout
    LVS (Layout Versus Schematic)
    Parasitic extraction
    PLS (Post layout simulation)
Cadence Documentation
Unfortunately the help button in Cadence does not work, so you‟ll have to access the
files directly. They are in
   /eda/tools/cadence.ic.5.1.41/doc/
It‟s a bit of a mess in there, but don‟t worry, it is possible to navigate. I usually open
the directory in Firefox and use it to browse. Some direct links to useful documents
are listed below

Virtuoso Schematic Editor User Guide
file:///eda/tools/cadence.ic.5.1.41_ISR/doc/comphelp/comphelpTOC.html
http://www.ece.uci.edu/eceware/cadence/comphelp/comphelpTOC.html

Virtuoso Schematic Editor Tutorial
file:///eda/tools/cadence.ic.5.1.41_ISR/doc/comptut/comptutTOC.html

Virtuoso XL Layout Editor User Guide
file:///eda/tools/cadence.ic.5.1.41_ISR/doc/vxlhelp/vxlhelpTOC.html

Mentor Graphics Documentation
You can find PDF‟s in
/eda/tools/ams.2007.1/docs/pdfdocs
and HTML files in
/eda/tools/ams.2007.1/docs/htmldocs


Eldo User Reference
eldo_ur.pdf


Ezwave User Reference
ezwave_ur.pdf
Hand calculation
Before we draw a single transistor we need to figure out how large the transistor
should be and what current it should sink. The circuit that we will design is shown in
Figure 1.




               Fig u re 1 Co mmo n so u rc e a mp lif ie r w ith re s is ti v e l o a d

It is a common source amplifier with a resistive load and load capacitance. First let‟s
figure out what we know. The power supply voltage (VDD) for this circuit is 1.5V,
normally this is too high in 90nm (the standard is 1.2V) but designing with low VDD is
very difficult, so we‟ll cheat a bit to make our life easier.

The output common mode voltage (VCO) is 0.75V, it is usually chosen close to VDD/2.
An output common mode voltage of 0.75V means that with zero signal voltage at V IN
the output VOUT should be 0.75V. Note that “zero signal voltage at VIN” does not
mean VIN=0, but rather VIN = VCI + vIN, where VCI is the common mode at the input
and vIN is the signal voltage. We need a voltage at VIN to turn our transistor on, which
is VCI, we superimpose a signal voltage on top of this, so if vIN is a sinusoid of
amplitude 0.1V , the input voltage will be
                                VIN = VCI + 0.1Vsin(t)
The input common mode will depend on the threshold voltage of the transistor and
the effective overdrive voltage.
The circuit is loaded with a capacitance (CL), we‟ll chose this to be 4pF. The load
capacitance of a integrated analog amplifier is usually in the range 100fF-10pF.
You‟ll probably only see larger than 10pF loads if very low noise is required (more
than 12 bit accuracy) or if your amplifier is driving output pads. You will not see
loads much less than 100fF. A single node, which translates to a metal wire of a few
micrometers, will likely have a capacitance of at least 10fF.

So we know power supply voltage (VDD), the output common mode voltage (VCO)
and the load capacitance (CL). That‟s what we know. What don‟t we know? We‟ll we
need to figure out the drain current (ID), the transconductance (gm), the effective
overdrive (VEFF = VGS – VT), the resistor value (R1), the gain (A = gmR1) and the unity
gain frequency (0 = gm/CL). Then we need to pick a suitable L and figure out what
W gives us the correct gm and VEFF. The first thing we do is figure out the current.

Usually when you‟re asked to design something you are given a specification for
unity gain frequency, 0. The unity gain frequency sets the gm for a given CL, and a
given VEFF and gm gives us an approximate current through the relation
                                             2I
                                     gm  1 D
                                             VEFF
where the factor 1 (pronounced “eta one”) is between zero2 and one. In the square
law model of the transistor 1=1, but in a real transistor it is usually less. The factor
1 is highly dependent on length due to reduced drain current because of velocity
saturation at shorter channel lengths. In saturation and strong inversion there is not
much dependency on width or current, except for at high VEFF where mobility
degradation kicks in. To figure out this factor we‟ll have to use a simulator, but not
just yet. Since we have no demands on the unity gain frequency, we‟ll pick our
current and just say it‟s 1mA. This is a quite large current; in the opamp that you‟ll
design in the project the current will probably be in the 100uA – 5mA range for a
single branch.

Next we figure out the resistance R1. We know we want an output common mode of
0.75V, so at 1mA current the resistance needs to be 750Ω to give us a voltage drop of
0.75V over the resistor, this will set the output voltage at VDD – 0.75V = 0.75V.

                          R1 = VCO/ID = 0.75V/1mA = 750 Ω




2
 Note that 1 will never be equal to zero, this would mean we get no current for any
VEFF which would mean our transistor is always off.
The effective overdrive is next in line, the VEFF for a transistor is usually chosen such
that the transistor is in strong inversion. An approximate rule of thumb is VEFF =
VDD/8 or VEFF = VDD/10. We‟ll pick VEFF = 120mV. Our transconductance will be

                                 1 I D       1 2  1mA
                          gm                              116.7mS
                                 VEFF          120mV


The gain of the amplifier will be

                       A  g m R1  116.7mS 750  112.5

And the unity gain frequency is
                                              gm
                                    0           14.2GHz
                                              CL
Before we figure out what 1 is, we have to specify the length, because there is a
strong dependency on length. The length (L) of an analog transistor is usually chosen
a bit longer than the minimum length, maybe 1.2 to 2 times longer. We‟ll use L = 0.2.
Let‟s figure out what 1 is, and we do this using a SPICE testbench. Remember that
we can write 1 as
                                          g V
                                    1  m EFF
                                           2I D
The SPICE simulation to find 1 will also give us W and the input common mode VCI.
The testbench can be downloaded from
       http://pluto.iet.ntnu.no/manuals/Originals/cadence/tb_bias.cir
Or on one of the Linux servers copied with
       cp /eda/man/Originals/cadence/tb_bias.cir ~/cadence_tut
Open the testbench in your favorite editor and have a look, if you don‟t have a
favorite text editor, take a look at http://support.math.arizona.edu/linux/editors.php.
Make sure you understand what happens in the testbench. We‟ll now list the
commands you‟ll need to execute to make the testbench run.

In a terminal, change directory to the tutorial directory
cd ~/cadence_tut


Run Eldo with the testbench tb_bias.cir
eldo tb_bias.cir     –noasci –noconf


Run the waveform viewer Ezwave
ezwave &


Those commands should run Eldo and popup the waveform viewer seen in Figure 2.
                           Fig u re 2 E z wa v e ma in w in d o w

Open the file called tb_bias.wdb. In the side panel expand down so you see V(G)
W(ETA1), VDSS(XM1.M1) and GM(XM1.M1). Double click all of these, and they
should show up in the plot window. By pressing F5 you can place a cursor. Drag the
cursor until you find VDSS(XM1.M1) = 120mV, like shown in Figure 3. Use the help
function in Ezwave if you need more information. From the plot we can now read 1
= 0.526, VIN = 0.481 and W=28.




                          Fig u re 3 B ia s si mu la tio n re su lt s

We now know all the parameters necessary to draw the schematic and start
simulating. The point of simulation is to confirm the values listed in the table below
and make sure the amplifier works as expected. It is a very good idea to have the
equations in a spreadsheet, so if you change the length or VEFF and redo the bias
simulation you won‟t have to manually update everything.
Parameter   Value
ID          1mA
VEFF        120mV
VCO         0.750V
R1          750Ω
Gm          8.8mS
A           -6.6
0          2.2GHz
L           1
W           28
VCI         0.481V
Schematic capture

Fire up Cadence as described earlier if it‟s not already open. Inside the icfb window
choose the menu command: File->New->Library. The dialog box in Figure 4 appears.
Specify the name of the library as shown below. Select “Attach to an existing
techfile” and press OK.




                                Fig u re 4 Ne w L ib ra r y




This brings up the dialog box in Figure 5. Choose „cmos090‟ as technology library
and press OK.




                            Fig u re 5 Te ch n o lo g y L ib ra ry


To create a new cell, choose File->New->Cellview from the icfb window. The dialog
box in Figure 6 appears. Select the right library, view name and tool in accordance to
Figure 6. Then specify cell name and press OK. Now a new window (Virtuoso
Schematic Editing) appears as shown in Figure 7.
                               Fig u re 6 Ne w s ch ema ti c




                        Fig u re 7 S c h ema ti c ca p t u re w in d o w


Tip: Open the Library Manager by choosing Tools->Library Manager from the icfb
window. It‟s convenient for exploring libraries and cells. You can also use “i” to pop
up the “Add Cell” dialog.

Now we need to draw the schematic of the common source as shown in Fig. 5 by
picking the appropriate components (“nsvt” for NMOS and “psvt” for PMOS) from
the cmos090 library. The finished schematic is shown in Figure 8.
                       Fig u re 8 Th e co m mo n so u rce a mp li fie r


Let‟s first pick NMOS transistor, its called “nsvt” in cmos090 library. For this, click
on the “Instance” button on the left side in the Virtuoso Schematic Editing window
(Figure 9).




                               Fig u re 9 In s ta n ce b u tto n




This will pop-up a new window as shown in Figure 10. Fill in the information as
shown in the figure. It‟s a good idea to choose a unit width for the transistors, usually
this is chosen so W/L = 5-20, so lets use W=2 and M=14 (M is number of devices in
parallel), remember the transistor should be W=28. Press “Hide” when you‟re done.
                                  Fig u re 1 0 N MOS

Place the transistor in the Virtuoso Schematic Editing window as shown in the Figure
8 and press “Esc” button on the keyboard. Repeat the process with the resistor. For
the resistor we use a hi-resisitve poly-silicon resistor, its called “rhiporpo” in the
cmos090 library. The values for the resistor is shown in Figure 11. To reduce
mismatch we put 5 in parallel (Nb of devices in #).

You can use the arrows to scroll, and the mouse wheel to zoom in the schematic
window. If you press “f” it will fit everything in the current window. To see the rest
of the hotkeys take a look in the Virtuoso Schematic Editor User Guide.




                              Fig u re 1 1 Po ly re s i sto r




Now your schematic should look something like shown in Figure 12.
                    Fig u re 1 2 A ft er p la c in g N MOS a n d r es i sto r


We‟ve already set the size of the transistor and resistor, but if you need to change it
you can select it by clicking on it, and then press “q” on the keyboard. This will pop-
up a window where you can change the transistor‟s dimensions. Press OK when
you‟re done.

For wiring, select the wire as shown in Figure 13 on the left side of the Virtuoso
Schematic Editing window and complete the wiring as shown in Fig. 12. You can also
use the hotkey “w” to enter wire mode.




                                 Fig u re 1 3 Wi r e b u t to n
                                        Fig. 12.

After wiring we need to add pins, and assign net names to all nets (a net is the same as
group of connected wires with the same name). You should always add a net name to
each and every net in you design. Do not use the default names (netXXX), adding a
meaningful net name to all nets will save you hours, if not days when doing layout of
a large design. See next page for how to add net names.

For pins, select the pin button as shown in Figure 14 from left side of the Virtuoso
Schematic Editing window, or use the hotkey “p”. Add the pins vin, vout, vdd, vss
and place them as shown in Figure 15. We need to change the direction of the vout
pin. Select it by clicking on it and press “q” or use the property button (Figure 16).
Change the direction to “out” and click OK. 3




                                Fig u re 1 4 P in b u tto n

3
 Note that Cadence will not allow direct connection between input and output pins,
but sometimes this is necessary. If you need a direct connection between input and
output you can use a 0.1Ohm metal resistor (rm2), this will not affect the simulation
much.
                                Fig u re 1 5 Wi th p in s




                            Fig u re 1 6 P ro p er ty b u tt o n

Finally we add the net names, press “l” or use the wire name button (two below the
wire button). A dialog like Figure 17 will pop-up, add the proper wire names as
shown in Figure 18, note you‟ll have to add two vss names, both on the source (and
bulk) of the transistor and on the bulk of the resistor.




                            Fig u re 1 7 Ad d wi re n a m e
                           Fig u re 1 8 A ft er wi re n a me s


Now check and save the design (top left button in the Virtuoso Schematic Editing
window). Schematic part is done !!!

When we want to do hierarchical design it‟s good to have a symbol for our cells. So
let‟s create a symbol for our common source (CS) schematic. To create a symbol for
our CS choose the menu command Design->Create Cellview->From Cellview, from
inside the Virtuoso Schematic Editing window (where we have just now drawn the
CS schematic). The dialog box in Figure 19 appears.




                            Fig u re 1 9 C rea tin g sy m b o l


Press OK, it will then pop-up another window. Move the vdd and vss pin to “Top
Pins” as shown in Figure 20.
                      Fig u re 2 0 De fin e wh e re th e p in s g o


Press OK and it‟ll pop-up another window with the symbol as shown in Figure 21.
You may change this symbol to whatever you want, like shown in Figure 22.




                            Fig u re 2 1 S ymb o l Ed i to r
                        Fig u re 2 2 F in i sh ed a mp l ifi e r s ymb o l


Now check and save the design in the Virtuoso Symbol Editing window (where we
have just drawn the CS symbol) choose the menu command: Design->Check and
Save.

To check the performance of the CS using the simulator, we usually create a
testbench, either a schematic or an text file where the CS is instantiated. To prepare
for simulation, create a new schematic called tb_cs, add one instance of the CS and
hook up pins to the CS symbol. You can use the same pin names as in the above
exercise. The schematic tb_cs is shown in Figure 23.
                       Fig u re 2 3 Te stb en ch sch ema t ic fo r CS

Before we can start simulating our common source we need to write a netlist.

Creating netlist from the schematic
From Virtuoso Schematic of cell tb_cs:

      Start netlist/simulation tool: Tools → Analog Environment
      Specify simulator: Setup → Simulator, Choose eldo
      The resistors we use (rhiporpo) are not standard devices, so you may need to
       add them to the environment. Choose Setup→Environment and add
       “SimResistorStandard” to both “Switch View List” and “Stop View List” as
       shown in Figure 24, if they are already there you don‟t need to add them.




                  Fig u re 2 4 En vi ro n men t f o r re si s to r s imu la t io n
      Run netlister: Simulation → Netlist → Create Final

You‟ll find your netlist in

~/simulation/tb_cs/eldo/schematic/netlist/eldoFinal


Include this netlist in your testbench.
Verifying Design                                               Through
Simulation
For most analog circuits we do several different simulations. The first one we do is
usually a DC analysis to check that all transistors operate as expected and that they
have the gm, ID and VEFF (VDSSat) we expect. When we are sure that the transistors
operate as they should, we proceed to an AC analysis to check the frequency
response. Maybe finally we do an transient analysis to check linearity or the like. In
this tutorial we‟ll do the two first steps, DC and AC.


DC analysis
We want to check gm, ID, VEFF, VCO and AS = dVOUT/dVIN (small signal gain). So
we‟ll make a testbench and include our circuit. It is very rare that we write a testbench
from scratch, we routinely copy like crazy from previous testbenches. Copy the
testbench tb_cs_dc.cir with the command
   cp /eda/man/Originals/cadence/tb_cs_dc.cir ~/cadence_tut
The testbench should run without modification, but read the testbench so you
understand what it does. Run the testbench with
cd ~/cadence_tut
eldo tb_cs_dc.cir –noasci –noconf


Open the file tb_cs_dc.wdb in Ezwave, if you add gm, ID, VEFF, VOUT, VIN and AS to
the plot and you‟ll get something that looks like Figure 25. If you right click on the
V(OUT) line you can choose “Set as X axis”, that way we can plot the small signal
gain as a function of V(OUT) as shown in Figure 26. Use a cursor (F5) to find where
VEFF = 120mV. We‟ll use this as our reference point when we compare with our hand
calculated values. You can now read the values for gm, ID, VOUT, VIN and AS from the
plot.
                           Fig u re 2 5 S imu la t io n re su l t s

Below we‟ve made a copy of the values we derived during hand          calculation. We‟ve
extended the table with the values we extract from Figure 25.
Parameter                  Value                Simulated             Deviation
ID                         1mA                  0.969mA               - 3.1%
VEFF                       120mV                120mV                 0%
VCO                        0.750V               0.772V                + 2.9 %
Gm                         8.8mS                8.579mS               - 2.5 %
A                          -6.6                 -5.610                15 %
VCI                        0.481V               0.475                 - 1.2%

From this we see that every factor except the gain A is in good agreement with our
calculated values. But the gain is 15 % off, what is this due to? There must be
something we have not included in the model of A = gmR1. One thing we ignored is
the channel length modulation of our transistor represented in the small signal model
by the drain source conductance gds, this is a resistance (rds = 1/gds) in parallel with
our R1, and will reduce the gain according to
                       A = - gm(R1 || rds) or A = - gm/(G1 + gds)

 If we use the simulator to extract the drain source conductance 4 parameter (.plot
gds(xi0.xm0.m1)) we get gds = 0.197mS, G1 = 1/R1 = 1.33mS. If we now calculate
the gain using the hand-calculated gm we see that there is now a 2.4% deviation. This
matches the other errors we have.

                      A = - 8.8mS/(1.33mS + 0.197mS) = - 5.75

It is important to realize that hand calculated values are extremely useful and also
accurate, but it requires that we use a correct model for the parameter we are
calculating. The way we did it is quite alright, we first use the most approximate
expression for a parameter (A = gmR1), if simulations tell us that this is good enough,
then great, we don‟t need to worry about it. But if simulations tell us that the
approximation is not good enough we have to figure out why.

You should also realize that the gain of our amplifier is highly non-linear as a
function of output voltage, we can see this from Figure 26. The gain at an output of
0.2V is almost half the gain at 0.6V. Also note that if we wanted a gain of 5 we could
maximum have an output swing of 0.6V, from 0.3V to 0.9V.

There is one parameter that we have not checked and that is the unity gain frequency,
which we‟ll check in an AC simulation.




4
  Why is gds called a conductance while gm is called a trans-conductance? The current
through the conductance gds depends on the voltage across it (VDS), the current
through the conductance gm depends on a voltage somewhere else (VGS), not the
voltage across it (VDS), therefore a trans-conductance.
            Fig u re 2 6 S ma l l sig n a l g a in a s a fu n ct io n o f o u t p u t vo l ta g e




AC analysis
Copy the testbench called tb_cs_ac.cir and run it. Make sure you read it also, it is a
modified copy of tb_cs_dc.cir. The results can be seen in Figure 27.
                    Fig u re 2 7 A C An a l ys i s, Ma g n i tu d e a n d Ph a s e

From the plot we can see that f0 = 345.8MHz. If we compare that to our calculated
value of the unity gain frequency we see it‟s in good agreement with the expected
value.

Property                 Value                         Simulated                     Deviation
0                       2.2GHz                        -                             -
f0 (0/2)               350.1MHz                      345.8MHz                      - 1.2 %


You should note that the expression 0 = gm/CL, is an approximation and that the real
expression is
                         1  gm R12
                               2
                                       1  (8.8mS  750)2
                0                                       2.175GHz
                          R1CL             750  4 pF
Which results in f0 = 346MHz, which is less than 0.06% deviation from the simulated
value. Hand calculation do a very good job as long as you do them right.

Further Analysis
In a real circuit we would proceed to do mismatch simulations, process corner
simulations (typical, slow, fast), temperature sweeps, supply voltage sweeps, transient
startup analysis and so on. But since this is an early introduction to analog simulation
we‟ll skip that, and worry about it in a year or two. The next installment of this
tutorial deals with layout and parasitic extraction.

Appendix
tb_bias.cir
*The comment line

*The CMOS090 device library for typical corner
.lib key=mos ~/cmos090eldo/cmos090_tt.mod

*The transistor length
.param length=0.2

*The transistor width
.param width=0.5

*Drain current
id 0 g dc 1m

*Diode connected nmos transistor (pmos is called psvt)
xm1 g g 0 0 nsvt w=width l=length

*Gate source voltage
.plot dc v(g)

*Transistor transconductance, the transistors in 90nm are subcircuits, so we
need to specify the actual transistor with xXX.m1
.plot dc gm(xm1.m1)

*Drain source saturation voltage, this is roughly equal to our VEFF
.plot dc vdss(xm1.m1)

*Calculate & plot eta1
.defwave eta1 = vdss(xm1.m1) *gm(xm1.m1)/(2*i(xm1.m1.d))
.plot dc w(eta1)

*Run a dc analysis and sweep the width
.dc param width 0.5 100 1




tb_cs_dc.cir:
*The comment line

*Set the Eldo accuracy
.option eps=1e-6

*The CMOS090 device library for typical corner
.lib key=mos ~/cmos090eldo/cmos090_tt.mod

*Our CS amplifier
.inc ~/simulation/tb_cs/eldo/schematic/netlist/eldoFinal

*Sources to bias the circuit
vdd vdd   0 dc 1.5
vss vss   0 dc 0
vci vci   0 dc 0.481
vi vi 0   dc 0



* To combine the common mode vci and the signal input vi we use a very
* useful circuit called a balun, which stands for balanced to unbalanced
* You can read more about it at http://it.iet.ntnu.no/eda_diffampdc
* All you need to know now is that it takes the signal and combines it with
* the common mode, we've change the transformers in the balun from a gain
* of 0.5 to a gain of 1 to make it easier to use singlended
xb1 vi vci vin na balun

*Load Capacitance
CL vout 0 4p

*Do a dc sweep of the input
.dc vi -0.3 0.3 0.00017

*Calculate the small signal gain
.defwave as = deriv(v(vout))/deriv(v(vi))

*Plot   gm, vdss(veff), Id, Vin, Vout and As
.plot   dc gm(xi0.xm0.m1)
.plot   dc vdss(xi0.xm0.m1)
.plot   dc I(xi0.xm0.m1.d)
.plot   dc gds(xi0.xm0.m1)
.plot   dc v(vin)
.plot   dc v(vout)
.plot   dc w(as)

*The balun subcircuit
.subckt balun vd vc vp vn
Y1 JTRAN vd 0 vp vc param: a=1 ! a=0.5 in the original version
Y2 JTRAN vd 0 vc vn param: a=1 ! a=0.5 in the original version
.ends balun



tb_cs_ac.cir:
*The comment line

*Set the Eldo accuracy
.option eps=1e-6

*The CMOS090 device library for typical corner
.lib key=mos ~/cmos090eldo/cmos090_tt.mod

*Our CS amplifier
.inc ~/simulation/tb_cs/eldo/schematic/netlist/eldoFinal

*Sources to bias the circuit
vdd vdd 0 dc 1.5
vss vss 0 dc 0
vci vci 0 dc 0.481
vi vi 0 ac 1
* To combine the common mode vci and the signal input vi we use a very
* useful circuit called a balun, which stands for balanced to unbalanced
* You can read more about it at http://it.iet.ntnu.no/eda_diffampdc
* All you need to know now is that it takes the signal and combines it with
* the common mode, we've change the transformers in the balun from a gain
* of 0.5 to a gain of 1 to make it easier to use singlended
xb1 vi vci vin na balun

*Load Capacitance
CL vout 0 4p

*Do a dc sweep of the input
.ac dec 70 1 100G

*Plot output voltage
.plot v(vout)

*The balun subcircuit
.subckt balun vd vc vp vn
Y1 JTRAN vd 0 vp vc param: a=1 ! a=0.5 in the original version
Y2 JTRAN vd 0 vc vn param: a=1 ! a=0.5 in the original version
.ends balun




eldoFinal:
* # File name: /home/wulff/simulation/tb_cs/eldo/schematic/netlist/
* tb_cs.c.raw
* Netlist output for eldo.
* Generated on Jan 13 21:51:10 2008
* File name: aic_tb_cs_schematic.s.
* Subcircuit for cell: tb_cs.
* Generated for: eldo.
* Generated on Jan 13 21:51:11 2008.
XI0 VDD VIN VOUT VSS cs_g1
* File name: aic_cs_schematic.s.
* Subcircuit for cell: cs.
* Generated for: eldo.
* Generated on Jan 13 21:51:10 2008.
* terminal mapping: vdd = VDD
*                   vin = VIN
*                   vout = VOUT
*                   vss = VSS
* End of subcircuit definition.
* Include files
* End of Netlist
.SUBCKT cs_g1 VDD VIN VOUT VSS
XR0 VDD VOUT VSS rhiporpo w=2.0 l=7.0 mult=5.0 mismatch=1.0 lpe=0.0
r=3.527e3
+nhead=2.0
XM0 VOUT VIN VSS VSS nsvt w=2.0 l=200e-3 nfing=1.0 mult=14.0 srcefirst=1.0
+mismatch=1.0
.ENDS cs_g1
.TEMP     27.0000
.OPTION
+        PSF_MULTI_BACK = 0
.PROBE V
.END