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					                                                                                                                           LMA1010/2010
DEVICES INCORPORATED
                                                                                                         LMA1010/2010
                                                                                                  16 x 16-bit Multiplier-Accumulator
  DEVICES INCORPORATED                                               16 x 16-bit Multiplier-Accumulator

 FEATURES                                             DESCRIPTION
  20 ns Multiply-Accumulate Time                    The LMA1010 and LMA2010 are                RND, TC, ACC, and SUB controls are
  Replaces Fairchild TMC2210,                       high-speed,    low    power    16-bit      latched on the rising edge of the logical
  Cypress CY7C510, IDT 7210L, and                   multiplier-accumulators.          The      OR of CLK A and CLK B. TC specifies
  AMD Am29510                                       LMA1010 and LMA2010 are function-          the input as two’s complement (TC
                                                    ally identical; they differ only in        HIGH) or unsigned magnitude (TC
  Two’s Complement or Unsigned
                                                    packaging. Full military ambient tem-      LOW). RND, when HIGH, adds ‘1’ to
  Operands
                                                    perature range operation is achieved       the most significant bit position of the
  Accumulator Performs Preload,                     with advanced CMOS technology.             least significant half of the product.
  Accumulate, and Subtract                                                                     Subsequent truncation of the 16 least
  Three-State Outputs                               The LMA1010 and LMA2010 produce significant bits produces a result cor-
  68-pin PLCC, J-Lead                               the 32-bit product of two 16-bit num- rectly rounded to 16-bit precision.
                                                    bers. The results of a series of multipli-
                                                    cations may be accumulated to form ACC and SUB control accumulator
                                                    the sum of products. Accumulation operation. ACC HIGH results in addi-
                                                    is performed to 35-bit precision with tion of the multiplier product and the
                                                    the multiplier product sign extended accumulator contents, with the result
                                                    as appropriate.                            stored in the accumulator register on
                                                                                               the rising edge of CLK R. ACC and
                                                    Data present at the A and B input SUB HIGH results in subtraction of
                                                    registers is latched on the rising edges the accumulator contents from the
                                                    of CLK A and CLK B respectively. multiplier product, with the result
 LMA1010/2010 BLOCK DIAGRAM                                                                    stored in the accumulator register.
                                                                               B 15-0          With ACC LOW and SUB LOW, no
                                                        A 15-0                 R 15-0          accumulation occurs and the next
                                                                                      16
                                                             16                                product is loaded directly into the
      CLK A                                          A REGISTER             B REGISTER
                                                                                               accumulator register. ACC LOW and
      CLK B
                                                                                               SUB HIGH is undefined.
                                                                                                          The LMA1010/2010 output register
                                                                                                          (accumulator register) is divided into
        RND                                                                                               three independently controlled sec-
                           REGISTER




         TC                                                                                               tions. The least significant result (LSR)
        ACC
                                                                               32
                                                                                                          and most significant result (MSR)
        SUB
                                                                       R                                  registers are 16 bits in length. The
                                                                       R + A                              extended result register (XTR) is 3
                                                                                        A
        OEX                                                            R A                                bits long. The output signals R15-0
                                            LEX
       OEM        PRELOAD                   LEM
                                                                      PASS R                35            and input signals B15-0 share the same
        OEL
                  CONTROL
                   LOGIC
                                       3    LEL                                                           bidirectional pins.
       PREL
                                                                                                          Each output register has an indepen-
                       3                                                                                  dent output enable control. In addition
                                      OEX     LEX              LEM                  LEL
                                      OEM
                                                                                                          to providing three-state control of the
                                      OEL     35         3                 16                    16       output buffers, when OEX, OEM, or
                                                                                                          OEL are HIGH and PREL is HIGH, data
      CLK R                                                    ACCUMULATOR REGISTER                       can be preloaded via the bidirectional
                                                                                                          output pins into the respective output
                                                                                                          registers. Data present on the output
                                                                                                          pins is latched on the rising edge of
                                                              OEX              OEM                OEL
                                                                                                          CLK R. The interrelation of PREL and
                                                         3                 16                    16       the enable controls is summarized in
                                                                                                          Table 1.
                                                    R 34-32          R 31-16



                                                                                                            Multiplier-Accumulators
                                                                                    1                                          09/18/2000–LDS.10/2010-Q
                                                                                                                                LMA1010/2010
DEVICES INCORPORATED
                                                                                            16 x 16-bit Multiplier-Accumulator

 TABLE 1. PRELOAD TRUTH TABLE                          FIGURE 1A. INPUT FORMATS
 PREL OEX      OEM    OEL      XTR    MSR LSR                                   AIN                                            BIN
   L      L     L      L       OUT    OUT OUT
                                                                             Fractional Two s Complement (TC = 1)
   L      L     L      H       OUT    OUT     Z
   L      L     H      L       OUT     Z     OUT              15 14 13                 2 1 0                   15 14 13               2 1 0
   L      L     H      H       OUT     Z      Z               20 2 1 2 2              2 13 2 14 2 15           20 2 1 2 2            2 13 2 14 2 15
                                                             (Sign)                                           (Sign)
   L     H      L      L        Z     OUT OUT
   L     H      L      H        Z     OUT     Z                                 Integer Two s Complement (TC = 1)
   L     H      H      L        Z      Z     OUT
   L     H      H      H        Z      Z      Z
                                                              15 14 13                2 1 0                    15 14 13              2 1 0
                                                              215 214 213             22 21 20                 215 214 213           22 21 20
   H      L     L      L        Z      Z      Z
                                                             (Sign)                                           (Sign)
   H      L     L      H        Z      Z     PREL
   H      L     H      L        Z     PREL    Z                                       Unsigned Fractional (TC = 0)
   H      L     H      H        Z     PREL PREL
                                                              15 14 13                 2 1 0                   15 14 13               2 1 0
   H     H      L      L       PREL    Z      Z
                                                              21 22 23                2 14 2 15 2 16           21 22 23              2 14 2 15 2 16
   H     H      L      H       PREL    Z     PREL
   H     H      H      L       PREL PREL      Z
                                                                                        Unsigned Integer (TC = 0)
   H     H      H      H       PREL PREL PREL
                                                              15 14 13                2 1 0                    15 14 13              2 1 0
PREL = Preload data to appropriate register                   215 214 213             22 21 20                 215 214 213           22 21 20
OUT = Register available on output pins
Z    = High impedance state



 FIGURE 1B. OUTPUT FORMATS
                            XTR                                   MSR                                              LSR
                                                         Fractional Two s Complement
                       34 33 32                     31 30 29          18 17 16                    15 14 13              2 1 0
                       24 23 22                     21 20 2 1         2 12 2 13 2 14              2 15 2 16 2 17       2 28 2 29 2 30
                      (Sign)

                                                           Integer Two s Complement
                       34 33 32                     31 30 29            18 17 16                   15 14 13              2 1 0
                       234 233 232                  231 230 229         218 217 216                215 214 213           22 21 20
                      (Sign)

                                                                  Unsigned Fractional
                       34 33 32                     31 30 29          18 17 16                    15 14 13              2 1 0
                       22 21 20                     21 22 23          2 14 2 15 2 16              2 17 2 18 2 19       2 30 2 31 2 32


                                                                   Unsigned Integer
                       34 33 32                     31 30 29            18 17 16                   15 14 13              2 1 0
                       234 233 232                  231 230 229         218 217 216                215 214 213           22 21 20




                                                                                                             Multiplier-Accumulators
                                                                            2                                                           09/18/2000–LDS.10/2010-Q
                                                                                                                                          LMA1010/2010
DEVICES INCORPORATED
                                                                                                 16 x 16-bit Multiplier-Accumulator

 MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)

        Storage temperature ............................................................................................................ –65°C to +150°C
        Operating ambient temperature ........................................................................................... –55°C to +125°C
        VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
        Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
        Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
        Output current into low outputs ............................................................................................................ 25 mA
        Latchup current ............................................................................................................................... > 400 mA



 OPERATING CONDITIONS To meet specified electrical and switching characteristics
                             Mode                             Temperature Range (Ambient)                              Supply Voltage
          Active Operation, Commercial                                       0°C to +70°C                           4.75 V ≤ VCC ≤ 5.25 V
          Active Operation, Industrial                                   –40°C to +85°C                             4.75 V ≤ VCC ≤ 5.25 V
          Active Operation, Military                                     –55°C to +125°C                            4.50 V ≤ VCC ≤ 5.50 V


 ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

 Symbol         Parameter                               Test Condition                                                           Min         Typ        Max        Unit

  VOH           Output High Voltage                     VCC = Min., IOH = –2.0 mA                                                 2.4                               V

  VOL           Output Low Voltage                      VCC = Min., IOL = 8.0 mA                                                                         0.5        V

  VIH           Input High Voltage                                                                                                2.0                   VCC         V

  VIL           Input Low Voltage                       (Note 3)                                                                  0.0                    0.8        V

  IIX           Input Current                           Ground ≤ VIN ≤ VCC (Note 12)                                                                    ±20        µA

  IOZ           Output Leakage Current                  Ground ≤ VOUT ≤ VCC (Note 12)                                                                   ±20        µA

  ICC1          VCC Current, Dynamic                    (Notes 5, 6)                                                                          12          25       mA

  ICC2          VCC Current, Quiescent                  (Note 7)                                                                                         1.0       mA




                                                                                                                      Multiplier-Accumulators
                                                                                   3                                                           09/18/2000–LDS.10/2010-Q
                                                                                                                                    LMA1010/2010
DEVICES INCORPORATED
                                                                                             16 x 16-bit Multiplier-Accumulator

 SWITCHING CHARACTERISTICS

 COMMERCIAL AND INDUSTRIAL OPERATING RANGE (0°C to +70°C) or (-40°C to +85°C) Notes 9, 10 (ns)
                                                                                                         LMA1010/2010–
                                                                     65*                    55*           45*     35*                    25              20*
 Symbol       Parameter                                         Min Max Min Max Min Max Min Max Min Max Min Max
   tMC        Clocked Multiply Time                                     65                        55          45          35                  25               20
   tPW        Clock Pulse Width                                 15                  15                   15          10             10               9
   tS         Input Register Setup Time                         15                  15                   12          12             12              10
   tH         Input Register Hold Time                           2                      2                2           2              2                2
   tSP        Preload Setup Time                                15                  15                   12          12             12              10
   tHP        Preload Hold Time                                  2                      2                2           2              2                2
   tD         Output Delay                                              30                        25          25          25                  20               18
   tENA       Three-State Output Enable Delay (Note 11)                 30                        30          25          25                  20               18
   tDIS       Three-State Output Disable Delay (Note 11)                30                        25          25          25                  20               18


 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
                                                                                                          LMA1010/2010–
                                                                     75*                    65*            55*     40*                  30*              25*
 Symbol       Parameter                                         Min Max Min Max Min Max Min Max Min Max Min Max
  tMC         Clocked Multiply Time                                         75                    65          55          40                  30               25
  tPW         Clock Pulse Width                                 20                  15                   15          15             10               10
  tS          Input Register Setup Time                         20                  15                   15          15             12               12
  tH          Input Register Hold Time                           2                      2                2           2               2               2
  tSP         Preload Setup Time                                20                  15                   15          15             12               12
  tHP         Preload Hold Time                                  2                      2                2           2               2               2
  tD          Output Delay                                                  35                    30          30          25                  20               20
  tENA        Three-State Output Enable Delay (Note 11)                     35                    30          30          25                  20               20
  tDIS        Three-State Output Disable Delay (Note 11)                    35                    25          25          25                  20               20


 SWITCHING WAVEFORMS
                                                           tS                tH
    A15-0
    B15-0
                                                                                  tPW
   CLK A
   CLK B
                                               tPW                                                 tMC
   CLK R
                                                                                   tPW                                         tD
   PREL


        OE*
                             tSP             tHP                 tDIS                                         tENA
                                                                                   HIGH IMPEDANCE
    R34-0                          PRELOAD                                                                                                         OUTPUT



              *includes OEX, OEM, OEL


*DISCONTINUED SPEED GRADE
                                                                                                                Multiplier-Accumulators
                                                                        4                                                                09/18/2000–LDS.10/2010-Q
                                                                                                                       LMA1010/2010
DEVICES INCORPORATED
                                                                        16 x 16-bit Multiplier-Accumulator

 NOTES

1. Maximum Ratings indicate stress         but not 100% tested.                      is specified as a maximum since worst-
specifications only. Functional oper-                                                case operation of any device always
ation of these products at values          9. AC specifications are tested with provides data within that time.
beyond those indicated in the Operat-      input transition times less than 3 ns,
ing Conditions table is not implied.       output reference levels of 1.5 V (except 11. For the tENA test, the transition is
Exposure to maximum rating condi-          tDIS test), and input levels of nominally measured to the 1.5 V crossing point
tions for extended periods may affect      0 to 3.0 V. Output loading may be a with datasheet loads.             For    the
reliability.                               resistive divider which provides for tDIS test, the transition is measured
                                           specified IOH and IOL at an output to the ±200mV level from the mea-
2. The products described by this spec-    voltage of VOH min and VOL max sured steady-state output voltage with
ification include internal circuitry       respectively. Alternatively, a diode ±10mA loads. The balancing voltage,
designed to protect the chip from          bridge with upper and lower current VTH, is set at 3.5 V for Z-to-0 and 0-to-Z
damaging substrate injection currents      sources of IOH and IOL respectively, tests, and set at 0 V for Z-to-1 and
and accumulations of static charge.        and a balancing voltage of 1.5 V may 1-to-Z tests.
Nevertheless, conventional precau-         be used. Parasitic capacitance is 30 pF
tions should be observed during stor-      minimum, and may be distributed.          12. These parameters are only tested at
age, handling, and use of these circuits                                             the high temperature extreme, which is
in order to avoid exposure to excessive    This device has high-speed outputs the worst case for leakage current.
electrical stress values.                  capable of large instantaneous current
                                           pulses and fast turn-on/turn-off times.
3. This device provides hard clamping      As a result, care must be exercised in
of transient undershoot and overshoot.     the testing of this device. The following   FIGURE A. OUTPUT LOADING CKT.
Input levels below ground or above         measures are recommended:
VCC will be clamped beginning at
–0.6 V and VCC + 0.6 V. The device can     a. A 0.1 µF ceramic capacitor should                               S1
                                                                                     DUT
withstand indefinite operation with        be installed between VCC and Ground                                                                        IOL

inputs in the range of –0.5 V to +7.0 V.   leads as close to the Device Under Test
                                                                                                                                           VTH
Device operation will not be adversely     (DUT) as possible. Similar capacitors                      CL
                                                                                                                                   IOH
affected, however, input current levels    should be installed between device
will be well in excess of 100 mA.          VCC and the tester common, and device
                                           ground and tester common.
4. Actual test conditions may vary                                                    FIGURE B. THRESHOLD LEVELS
from those designated but operation is     b. Ground and VCC supply planes                             tENA                         tDIS

guaranteed as specified.                   must be brought directly to the DUT           OE           1.5 V                1.5 V
                                           socket or contactor fingers.
5. Supply current for a given applica-                                               Z     0                                                     3.5V Vth

tion can be accurately approximated c. Input voltages should be adjusted
                                                                                                               1.5 V    VOL*       0.2 V
                                                                                                                                                 0    Z

by:                                       to compensate for inductive ground                                                                     1    Z
            NCV2 F                        and VCC noise to maintain required         Z     1
                                                                                                               1.5 V    VOH*       0.2 V

                                                                                                                                                 0V Vth

                4                         DUT input levels relative to the DUT                 VOL* Measured VOL with IOH = –10mA and IOL = 10mA
                                          ground pin.                                          VOH* Measured VOH with IOH = –10mA and IOL = 10mA
where
                                          10. Each parameter is shown as a
  N = total number of device outputs      minimum or maximum value. Input
  C = capacitive load per output          requirements are specified from the
  V = supply voltage                      point of view of the external system
  F = clock frequency                     driving the chip. Setup time, for
                                          example, is specified as a minimum
6. Tested with all outputs changing since the external system must supply
every cycle and no load, at a 5 MHz at least that much time to meet the
clock rate.                               worst-case requirements of all parts.
7. Tested with all inputs within 0.1 V of Responses from the internal circuitry
VCC or Ground, no load.                   are specified from the point of view of
                                          the device. Output delay, for example,
8. These parameters are guaranteed


                                                                                         Multiplier-Accumulators
                                                              5                                                          09/18/2000–LDS.10/2010-Q
                                                                                                                LMA1010/2010
DEVICES INCORPORATED
                                                              16 x 16-bit Multiplier-Accumulator

        LMA1010 — ORDERING INFORMATION
         64-pin                                          68-pin

                             A6   1     64   A7
                             A5   2     63   A8
                             A4   3     62   A9                 1      2      3      4     5       6       7     8     9      10   11
                             A3   4     61   A10
                             A2   5     60   A11
                             A1   6     59   A12
                                                          A
                             A0   7     58   A13                      NC     B/R0   A1    A3      A5       A7    A9    A11   A13
                        B0, R0    8     57   A14          B
                        B1, R1    9     56   A15               B/R2 B/R1     A0     A2    A4      A6       A8    A10   A12   A14   NC
                        B2, R2    10    55   OEL          C
                        B3, R3    11    54   RND               B/R4 B/R3                                                     OEL   A15
                        B4, R4    12    53   SUB
                                                          D
                        B5, R5    13    52   ACC
                        B6, R6    14    51   CLK A             B/R6 B/R5                                                     SUB RND
                        B7, R7    15    50   CLK B        E
                                                                                                Top View
                          GND     16    49   VCC              GND B/R7                                                       CLK A ACC
                        B8, R8    17    48   TC           F                               Through Package
                        B9, R9    18    47   OEX               B/R9 B/R8            (i.e., Component Side Pinout)            VCC CLK B
                       B10, R10   19    46   PREL
                                                          G
                       B11, R11   20    45   OEM
                                                               B/R11 B/R10                                                   OEX   TC
                       B12, R12   21    44   CLK R
                       B13, R13   22    43   R34          H
                       B14, R14   23    42   R33               B/R13 B/R12                                                   OEM PREL
                       B15, R15   24    41   R32          J
                            R16   25    40   R31               B/R15 B/R14                                                   R34 CLK R
                            R17   26    39   R30
                                                          K
                            R18   27    38   R29
                                                               NC    R16     R18    R20   R22     R24   R26      R28   R30   R32   R33
                            R19   28    37   R28
                            R20   29    36   R27          L
                            R21   30    35   R26                     R17     R19    R21   R23     R25   R27      R29   R31   NC
                            R22   31    34   R25
                            R23   32    33   R24




                          Discontinued Package                                 Discontinued Package



                         Sidebraze Hermetic DIP                               Ceramic Pin Grid Array
Speed                             (D6)                                                (G2)
        0°C to +70°C — COMMERCIAL SCREENING




        –55°C to +125°C — COMMERCIAL SCREENING




        –55°C to +125°C — MIL-STD-883 COMPLIANT




                                                                                    Multiplier-Accumulators
                                                     6                                                             09/18/2000–LDS.10/2010-Q
                                                                                                                  LMA1010/2010
DEVICES INCORPORATED
                                                                                               16 x 16-bit Multiplier-Accumulator

        LMA2010 — ORDERING INFORMATION
         68-pin




                   B0, R0
                   B1, R1
                   A14
                   A13
                   A12
                   A11
                   A10
                   A9
                   A8
                   A7
                   A6
                   A5
                   A4
                   A3
                   A2
                   A1
                   A0
                       9   8   7   6   5   4   3   2   1 68 67 66 65 64 63 62 61
           A15    10                                                           60   B2, R2
          OEL     11                                                           59   B3, R3
          RND     12                                                           58   B4, R4
          SUB     13                                                           57   B5, R5
          ACC     14                                                           56   B6, R6
         CLK A    15                                                           55   B7, R7
         CLK B    16                                                           54   GND
           VCC    17                                                           53   GND
                                                   Top
           VCC    18                                                           52   B8, R8
           VCC    19
                                                   View                        51   B9, R9
           VCC    20                                                           50   B10, R10
            TC    21                                                           49   B11, R11
          OEX     22                                                           48   B12, R12
         PREL     23                                                           47   B13, R13
          OEM     24                                                           46   B14, R14
         CLK R    25                                                           45   B15, R15
           R34    26                                                    44          R16
                       27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
                   R33
                   R32
                   R31
                   R30
                   R29
                   R28
                   R27
                   R26
                   R25
                   R24
                   R23
                   R22
                   R21
                   R20
                   R19
                   R18
                   R17




        Plastic J-Lead Chip Carrier
Speed               (J2)
        0°C to +70°C — COMMERCIAL SCREENING
35 ns            LMA2010JC35
25 ns            LMA2010JC25




        –40°C to +85°C — INDUSTRIAL SCREENING
25 ns            LMA2010JI25




        –55°C to +125°C — MIL-STD-883 COMPLIANT




                                                                                                        Multiplier-Accumulators
                                                                                         7                          09/18/2000–LDS.10/2010-Q

				
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