A Mixed Signal High Functionality CMOS Front-End for X-Ray Spectroscopy and Imaging with Semiconductor Pixel Detectors Stefano Caccia Politecnico di Milano, Department of Electronics Engineering and Information Science, P.za L. da Vinci 32, 20133 Milano, Italy Advisor Prof. Giuseppe Bertuccio LFDR PROJECT (Large Format Detector Readout) STAR-X ARCHITECTURE (SpecTroscopic ASIC for Radiation detectors) FRONT-END SPECIFICATIONS STAR-X is an Analog/Digital Signal Processor for X-g ray imaging and spectroscopy. STAR-X32 is designed for 32x32 large pixel array detectors and The Read Out Pixel Cell (RPC) is a mixed-signal and includes 32 ADC’s (10 bits), serial interface, configuration memory, trigger spectroscopy grade front-end electronics with high logic, acquisition interface, probe/calibration network. functionality as: digitally selectable shaping time, pile-up 32 × 32 GaAs rejection function, digital and analog section disabling X-γ Ray Detector 250 m function, discriminator threshold level fine adjustment. The specifications are here reported: • RPC size: 300 μm × 300 μm • RPC array: 16 × 16 (23 mm2) and 32 × 32 (92 mm2) • Dynamic Range: 120 - 12000 electrons (0.5-50 keV for GaAs) • Digitally (3 bit) selectable Shaping Time: 1 µs to 10 µs 1.1 cm • Equivalent Noise Charge: 25.7 e- r.m.s. ( = 10 µs, CIL= 0.4 pF) POLITECNICO DI MILANO FRONT-END SECTION DESIGN PAVIA UNIVERSITY BACK-END SECTION DESIGN • Separate Analog & Digital Power Supplies: + 3.3 V THALE ALENIA SPACE INTERFACE AND ACQUISITION SYSTEM • Power Consumption: 430 μW/channel LFDR project has been commissioned by ESA (European Space Agency) to an Italian team. Its aim is the realization of an ASIC to be bump-bonded to a • Technology: CMOS 0.35 μm (2P/4M/HR) (austriamicrosystems) GaAs pixel detector for X-γ ray spectroscopy for astrophysics. SHAPER SCHEMATIC Pin Test Voltage References Shaping Time Selection Signal Ground RESET / PUR LOGIC SCHEMATIC Enable Vgate Selection ANG DIG To Output Buffer Shaper Signal Peak INPUT Feedback Stop Stretcher PAD network Output Enable Analog Trigger Reset Gate Output Vtest Output Peak Pole-Zero Peak PDin Preamp. Shaper Buffer network Stretcher Discriminator Vref- Ctest simdet TDin S DSC Amplitude R Latch MTh Trigger Discriminator Peak Discriminator Pre Disable Trigger Output Reset Amplitude Power Supplies VAN1 V-I A B First Shaping Stage Gain Compensation AC Current Second Shaping Stage Discriminator Reset/PUR conv. Circuit Coupler Logic VAN2 EOC Start Q Q VDIG EOC DAC 50 ns RN Schematic of the RC-CR shaper employed in the Read Out Pixel Cell. Col Flip-Flop The switchable capacitances realize 8 different shaping times from 1 μs to 10 μs. The current conveyor structure, present in both the shaping stages, guarantees an high resistance and a suitable linearity saving area. Disc Disc Fine Threshold Start EoC Column Output Schematic of the Reset / Pile-Up Rejection Logic. The area occupation is Disable Tuning Level enable 60 μm × 80 μm. EXPERIMENTAL CHARACTERIZATION READ OUT PIXEL CELL LAYOUT PILE-UP REJECTION / RESET FUNCTIONALITY 1.5 - 1.10 Shaper Output [ V ] 1.4 Qin= 12000 e Shaper Output [ V ] = 10 s 1.3 1.05 EOC = 6 s 1.2 Set of screen shots showing 1.00 = 1 s peak stretcher 1.1 Qin= 120 e - shaper the functionality of the RPC 1.0 0.95 and the operation of the Pile-Up rejection function. 0.9 0.90 trigger 0 10 20 30 40 -5 0 5 10 15 20 25 30 35 40 input pulse Time [ s ] Time [s ] Shaper response over the entire dynamic range for = 6 μs. Shaper 300 μm response for different shaping times at constant test input signal. No Pile-Up Pile-Up case 8 50 Input Load Capacitance ~ 400 fF 6 ENC [ electrons r.m.s.] % Linearity Error 4 Ileak = 2.5 pA peak stretcher peak stretcher 2 40 31.5 e- 0 Ileak ~ 0 pA -2 30 -4 - 0.8 % < err % < 2.5 % -6 25.7 e- -8 0 10 20 30 40 50 11 2 3 4 5 6 7 8 910 Equivalent Photon Energy [keV] Shaping Time [s ] Percentage linearity error over the entire dynamic range and Equivalent Noise Charge as a function of the shaping time with an input load capacitance of 400 fF. 300 μm Trigger (two valid pulses) Trigger (single valid pulse) STAR-X16 PROTOTYPE STAR-X32 PROTOTYPE Test Hybrid 16 × 16 ASIC Read Out Pixel Cell 16.2 mm 18.3 mm Prototype of STAR-X32 ASIC. It is composed by 4 identical 16x16 quadrants controlled by a local and a Photos of the test hybrid circuit for the 16 × 16 prototype ASIC and the Read Out Pixel Cell. global logic with 32 ADC’s with parallel operation. The ASIC area is about 3 cm2 with 214 input/output pads. The author would like to thank: Didier Martin (ESA); Nicoletta Ratti, Ivan Cappelluti, Paolo Bastia and Flavio Ferrari (Thales Alenia Space); Piero Malcovati, Fausto Borghetti, Andrea Rossini, Marco Grassi and Vincenzo Ferragina (Univerità di Pavia); Alberto Pullia, Diego Maiocchi (Università degli Studi di Milano).
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