CSP Technology in Fujikura

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CSP Technology in Fujikura Powered By Docstoc
					WLCSP
Technology in
    Electron Device Laboratory
Introduction
   Wafer Level Chip Sized Package
     The Latest IC Packaging Technology
     Ultimate Small Sized & Low Cost



   Business Model
       IC Packaging Service
            Receive Customer’s Bare Wafers and
             Send Encapsulated Wafers Back to
             Customers
Introduction
   Function of IC Package
     Protection for Die Surface
     Stress Release between Die and PCB
     I/O Pitch Adjustment between Die and
      PCB
   Demand to IC Package
     High Density and Small Size
     High Speed and High Performance
     Low Cost
                       Trend of IC Package

                              Conventional
                                 CSP

                                              Wafer Level
Density




                 QFP                             CSP


                                  BGA


          1970         1980       1990       2000
             Process Innovation
QFP,BGA, Conventional CSP
     Wafer         Dicing             Packaging




Wafer Level CSP               Ultimate Down-Sizing
     Wafer        Packaging             Dicing
       Example of WLCSP
       solution
 ・Wrist Camera (Fujitsu)
 ・G-SHOCK Watch (IEP)

  Wire-bonding          WLCSP
        27mm


               shrink
30mm




 75% down-size mounting area
Seeds & Motivation

   Silicon Piezoresistive Pressure
    Sensors, Accelerometer
            Planer Process
     Silicon
      Technologies

   Flexible Print Circuit (FPC)
           Distribution /Tracing
     Ciruit
      Technologies
Cross Technologies
Development
   Silicon Wafer Handling
   Poly-Imide Insulation
   Seed Layer Sputtering
   Cu Re-tracing
   Solder Bumping
                 Structure
       Metal-covered Polyimide Post Method
                                ENCAPSULANT
LEAD FREE BUMP

                                           Cu POST

                                              PI CORE




                                         Cu RE-ROUTE

 DIE
                                   INSULATION RESIN
             AL PAD
                  Structure

   Elastic polyimde core       Redistribution   trace
    absorbs strain              & metal post
    between mounted chip                            Polyimide
                              Overcoat
    and PCB.                                        core
   Single Cu layer
    enables to be electro-
    plating process simple.                                Polyimide
   Redistribution and
    copper overlay            Al
    formed at one plating     pad       Si
    work, advantageous                  wafer
    for cost reduction.                          Not to
                                                 scale.
Process
  Wafer process


  Post formation
  Redistribution

   Encapsulation


    Solder Bumping


Singulation & Sort (pack)
Suitable Applications
Target
   Small Sized, Small number of
    Pins
     DSP
     Voltage regulator
     Analog Amp.
     ASIC
     Flash   Memory?

   Medium Size Production Volume
Target Market

   Consumer Electronics

   Telecom???
   Automotive???
Our Advantages

   Quick & Flexible Development,
    Design & Production
   Cross Technologies
    Development
   Neutral & Independent
                                                 -> 20,000wafers/month
                   Road Map                       5,000wafers/month

                                                              8inches
                                                    6inches




       R&D Stage          Pre-Production       Mass-Production
2000               2001                    2002                2005
                             Year

				
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posted:3/22/2011
language:English
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