Limitations of Polling

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					                      Advantages and Disadvantages of Polling


                                       Advantage:
      Issue I/O
     Command to                        • simple to implement in both software and hardware
       Device

                                       Disadvantages:
     Read Status
      of Device                        • Polling occupies CPU, prevents useful work

                                       • Very inefficient for data transfer (sending data to
                                         memory via CPU)
        Check
        Status          Error
Not Ready                              • May miss important events when busy polling
                                         inactive slaves or when doing something useful (and
              Ready
                                         not polling)
      Perform I/O
       Operation       I/O ↔ CPU

                                       Summary: micro-management is too inefficient if
                                       system is busy or has multiple active devices.
                        Partial Solution – Interrupt-Driven I/O

       Issue Command                                    ...
                                 CPU now does
              to                                        INSTRUCTION N-1
          I/O Device             something else
                                                        INSTRUCTION N
                                                        program suspended
                                                        program resumes
         Read Status             Interrupt CPU          INSTRUCTION N + 1
        of I/O Device            when ready to          INSTRUCTION N + 2
                                 transfer data          ...

 Exception
 Handler

                                                  Advantages of using Interrupts:
             Check
                          Exit
             Status
                                                  • CPU can perform useful work
                                                  • Can’t miss important events

        Transfer data                             Disadvantage:
      between memory
       and I/O device
                                                  • Data transfer still under control of
                                                    CPU
             RTE

Only operating system has
direct control of I/O devices
                                Interrupts in General
An interrupt is an external asynchronous signal to alert the CPU that some event or
device needs immediate attention.




                                                           Causes:
     CPU
                                                           • I/O Completions
                request interrupt by
                asserting IRQ line                         • External Events
        IRQ                             Hardware               e.g., mouse movement,
                                         Device                      network-interface card
      IACK
               Interrupt acknowledged                                sensor, switch, etc.
               by CPU by asserting
                                                           • Timer Expires
               IACK
                   Interrupt Types Having Different Priorities
Hardware devices are assigned a priority and dealt with by the CPU according to priority.
The priority is high for very time-critical (or important) devices and low for less time-
critical (or important) devices.




          CPU
                             Interrupt mask bits set level
   Interrupt Mask Bits
                             below which interrupts will not
                                                                          Highest Priority (IRQ7)
                             be processed
                  IRQ7                                  System Timer
                  IRQ6
                  IRQ5                                 Hard Disk Controller
                  IRQ4                                 Floppy Disk Controller
                  IRQ3
                  IRQ2
                  IRQ1                                  Parallel Port
                                                                          Lowest Priority (IRQ1)


   If a device initiates an interrupt at
   level p, the interrupt mask is set to p
                                     Interrupt Mask Bits
The interrupt mask bits are used to set the level below which interrupts will not be
processed (usually by means of a MOVE #data,SR instruction).


                     15        10 9 8                                   0
                                   I2 I1 I0         X     N   Z    V    C   Status Register


                                   Interrupt
                                     Mask



                 Pritority Level     Interrupt Mask Recognized Levels

                 7 (highest)              111                 7                     Non-maskable
                       6                  110                 7                     interrupt
                       5                  101               6,7
                       4                  100               5,6,7
                       3                  011              4,5,6,7
                       2                  010             3,4,5,6,7
                       1                  001            2,3,4,5,6,7                All interrupts
                 0 (lowest)               000           1,2,3,4,5,6,7               recognized. User
                                                                                    programs run with
                                                                                    mask 0002
                                Time Sequence of Multiple Interrupt Example


                                        Disk interrupt
                                                                                                                  • Printer – Priority 2
                                        Priority 4 held
                                        pending                                                                   • Disk – Priority 4
                                                               Modem handler finishes
                                                               Disk interrupt occurs                              • Modem – Priority 5

                           Modem                                           Disk
                           Priority 5                                      handler
                                                                           finishes
   Printer
   interrupt                                                                                         Printer handler finishes
   Priority 2


   0              10              15         20           25                35              40
                                                                                                                Time

      User              Printer          Modem                   Disk             Printer          User
    Program            handler           handler                handler          handler         Program

       Mask 000        Mask 010         Mask 101               Mask 100          Mask 010        Mask 000            Direction of Stack Growth
                         User               User                  User            User
                                           Printer               Printer
PC and SR
saved                                                                                                PC and SR
                                                                                                     restored
                                        Summary
• User programs can always be interrupted since they always run with interrupt mask set
  to zero.

• A low priority interrupt-service routine can always be interrupted by a higher priority
  interrupt request


• A high priority interrupt-service routine cannot be interrupted by a lower priority
  interrupt. The low priority interrupt is ignored until the higher priority is finished.



          When any interrupt handler begins, all interrupts are inhibited until
          processor registers have been saved; then higher-level interrupts are
          enabled by changing the SR.
                           Interrupt Control Signals

If an interrupt is acknowledged, the
value of the interrupt mask is output
on the address bus                             ILP2 ILP1 ILP0 Priority
                                               Level
                                        A1
                                               Hi   Hi     Hi          7 – highest
                                        A2     Hi   Hi     Lo          6
     68000                                     Hi   Lo     Hi          5
                                        A3     Hi   Lo     Lo          4
                                               Lo   Hi     Hi          3
                                               Lo   Hi     Lo          2
                                               Lo    Lo    Hi          1
                                        F1=1
                                        F2=1
                                        F3=1
                                               Interrupt    ILP2 ILP1 ILP0 Priority
                                               Level
                                        ILPO   None             Hi   Hi    Hi        0 – none
                                                1               Hi   Hi    Lo        1 – lowest
                                        ILP1    2               Hi   Lo    Hi        2
                                                3               Hi   Lo    Lo        3
Interrupt Inputs                        ILP2    4               Lo   Hi    Hi        4
                                                5               Lo   Hi    Lo        5
• indicate interrupt request                    6               Lo    Lo   Hi        6
• encode level of interrupt
                           Interrupt Vector Numbers
A vector address is a memory location that contains the address of a routine to handle the
exception. Vector addresses are generated internally by the 68000 using vector numbers,
except in the case of a user (or vectored) interrupt.



                                 D0
                                                                                       VPA
                                                           68000
      68000                      vector number                          Control
                  Data           on data bus                            Bus
                  Bus

                                 D7



 User Interrupt                                       AutoVector Interrupt
 • device sends processor a vector number             • one vector number is used for each input
   on the lower data bus                                priority level (and generated internally)
 • vector number is multiplied by four to             • the processor uses vector numbers 25-31
   obtain vector address                                for autovectoring
 • addresses $100 through $3FC are used
   by user interrupts
       Exception Processing Sequence for Interrupts

       Start


Make internal copy              Set Interrupt
      of SR
                                  Mask to
                                                No – User Interrupt
      S←1
      T←0
                                    VPA low?           Obtain Vector
                                                       Number from
                    Interrupt
     Interrupt?                         Yes - Autovector               yes
                                        Interrupt        Bus Error?
               exception

 Get (Internally                                          no
Generated) Vector               Obtain Vector
    Number                      Number from
                                                                       Force
                                                                      Spurious
                                                                      Interrup


 Vector Address =
4 × Vector Number



Push PC and copied
   SR on stack



PC ←vector address



       End
        (Simplified) Interface for User Interrupts




D0-D7                                           Lower Data Bus
    68000                                  DECODER

                                                 IACK7
                       1                          IACK6
                A1                                IACK5
                A2     1
                                                  IACK4
                A3     1
                                                  IACK3               Vector
                   1                              IACK2
                F1 1               1
                                                                          b
                                                  IACK1
                                           CS
                F2
                   1                                                IACK I/O Device
                F3
                                                  IRQ7              IRQ      DTACK
                           0                       IRQ6
          IPL0             0
                                                   IRQ5
          IPL1                                     IRQ4
                           0
          IPL2                                     IRQ3
                                                   IRQ2
                                                   IRQ1   ENCODER

        DTACK




    Vector Number              Vector
    Address                                           Advantage
            0                  $00000000
                               $00000004              • Flexibility
            2                  $00000008
            3                  $0000000C
            .                        .                Disadvantage
            64                       .
            .                        .
            .                        .                • Complex hardware required
            255                $000003FC
(Simplified) Interface for AutoVector Interrupts



 D0-D7

      68000                           ENCODER

                                             IACK7
                                             IACK6
              A1     0
                                             IACK5
              A2     0
                                             IACK4
              A3     0
                                             IACK3               I/O Device
                 1                           IACK2
              F1 1           1               IACK1
              F2                     CS
              F3
                 1                                             IACK
                                              IRQ7             IRQ
                         0                    IRQ6                        VPA
            IPL0         0
                                              IRQ5
            IPL1                              IRQ4
                         0
            IPL2                              IRQ3
                                              IRQ2
                                                     DECODER
                                              IRQ1

            VPA




Interrupt   Vector Number    Vector                   Advantage
Address
  1                24            $00000064            • Simplicity
  2                25            $00000068
  3                26            $0000006C
  4                27            $00000070
                                                      Disadvantage
  5                28            $00000074
  6                29            $00000078            • Inflexible
       Exception Table – User Interrupts

Vector Vector         Exception Type
Number Address

  0       000         Reset – initial supervisor stack pointer
  -       004         Reset – initial program counter value
  2       008         Bus Error
  3       00C         Address Error
  4       010         Illegal Instruction
  5       014         Divide by zero
  6       018         CHK Instruction
  7       01C         TRAPV Instruction
  8       020         Privilege Violation
  9       024         Trace
  10      028         Line 1010 emulator
  11      02C         Line 1111 emulator
  12      030         Unassigned – reserved
  13      034         Unassigned – reserved
  14      038         Unassigned – reserved
  15      03C         Uninitialized interrupt vector
  16      040         Unassigned – reserved
  .       .           .
  23      05C         Unassigned – reserved
  24      060         Spurious Interrupt
  25      064         Level 1 interrupt autovector
  .       .           .
  31      07C         Level 2 interrupt autovector
  32      080         Trap #0
  .       .           .
  47      0BC         Trap #15
  48      0C0         Unassigned – reserved
  .       .           .
  63      0FC         Unassigned – reserved
  64      100         User interrupt vector
  .       .           .                              192 User
 255      3FC         User interrupt vector         Interrupts
       Exception Table – Autovector Interrupts

Vector Vector         Exception Type
Number Address

  0       000         Reset – initial supervisor stack pointer
  -       004         Reset – initial program counter value
  2       008         Bus Error
  3       00C         Address Error
  4       010         Illegal Instruction
  5       014         Divide by zero
  6       018         CHK Instruction
  7       01C         TRAPV Instruction
  8       020         Privilege Violation
  9       024         Trace
  10      028         Line 1010 emulator
  11      02C         Line 1111 emulator
  12      030         Unassigned – reserved
  13      034         Unassigned – reserved
  14      038         Unassigned – reserved
  15      03C         Uninitialized interrupt vector
  16      040         Unassigned – reserved
  .       .           .
  23      05C         Unassigned – reserved
  24      060         Spurious Interrupt
  25      064         Level 1 interrupt autovector
                                                            7 User
  .       .           .
  31      07C         Level 7 interrupt autovector        Interrupts
  32      080         Trap #0
  .       .           .
  47      0BC         Trap #15
  48      0C0         Unassigned – reserved
  .       .           .
  63      0FC         Unassigned – reserved
  64      100         User interrupt vector
  .       .           .
 255      3FC         User interrupt vector
        Using the DUART’s Timer to Generate Interrupts
        68000’s clock


                                                      Interrupt Status Register (ISR)
                                                         0    0    0   0    1   0       0   0   $00C00B
             Counter/
              Timer                                   Interrupt Mask Register (IMR)
                                                          0    0   0    0   1    0      0   0   $00C00B

Interrupt Vector Register (IVR)
    x    x   x    x     x   x       x   x   $00C019                    STOP                     $00C01F



                                                         IACK IRQ           DTACK



  D0-D7


         68000                              IACK7
                            1                IACK6
                  A1                         IACK5
                            0
                  A2                         IACK4
                  A3        1
                                             IACK3
                                             IACK2
                                             IACK1


                                              IRQ7
                                               IRQ6
                                1
                 IPL0                          IRQ5
                                0
                 IPL1                          IRQ4
                                1
                                               IRQ3
                 IPL2                          IRQ2
                                               IRQ1


             DTACK
                               Example

Write an interrupt-driven program using the DUART’s timer to
display an asterisk on the console upon each interrupt. Use
$FFFF as the timer reload value.

DUART      EQU       $00C001    ;68681 base address
ACR        EQU       8          ;auxiliary control register
CTUR       EQU       12         ;counter/timer upper register
CTLR       EQU       14         ;counter/timer lower register
IMR        EQU       10         ;interrupt mask register
IVR        EQU       24         ;interrupt vector register
STOP       EQU       30         ;timer stop command address
I2VECTOR   EQU       26         ;I2 autovector number

******************************************************
* L2ISR - Level 2 Interrupt Service Routine          *
******************************************************

           ORG       $8006       ;INT2   entry at $8006
L2ISR      TST.B     STOP(A0)    ;stop   cmd, clr interrupt
           MOVE.B    #'*',D0     ;send   an asterisk
           TRAP      #1          ;upon   each interrupt
           RTE

******************************************************
* INIT – User Program: type “GO 8050”                *
******************************************************

           ORG       $8050         ;user prog. at $8050
INIT       MOVEA.L   #DUART,A0     ;A0 -> 68681 DUART
           MOVE.B    #$08,IMR(A0) ;enable timer interrupts
           MOVE.B    #I2VECTOR,IVR(A0) ;specify vector #
           MOVE.B    #$FF,CTUR(A0) ;specify preload value
           MOVE.B    #$FF,CTLR(A0)
           MOVE.B    #$70,ACR(A0) ;select clock source

           ORI.W     #$0700,SR        ;mask all interrupts(111)
           ANDI.W    #$F9FF,SR        ;mask level 1 only (001)
HERE       BRA       HERE             ;sit on this a while
                                     Decoders
A decoder can detect a code at its input and produce a single output that indicates the
presence of the code. The code is the address of the output to be made active.


                                        active-low signal

              A  D7
  code        B D6
inputs        C D5
                 D4              decoded
                                                                   Truth Table
                 D3              outputs
                 D2                           CS   A B C       D7 D6 D5    D4 D3 D2    D1 D0
                 D1                           0    x   x   x   1   1   1   1   1   1   1   1
   enable     CS D0                           1    0   0   0   1   1   1   1   1   1   1   0
                                              1    0   0   1   1   1   1   1   1   1   0   1
                                              1    0   1   0   1   1   1   1   1   0   1   1
                   Symbol                     1    0   1   1   1   1   1   1   0   1   1   1
                                              1    1   0   0   1   1   1   0   1   1   1   1
                                              1    1   0   1   1   1   0   1   1   1   1   1
                                              1    1   1   0   1   0   1   1   1   1   1   1
                                              1    1   1   1   0   1   1   1   1   1   1   1
                                Priority Encoders

A priority encoder performs the opposite function to a decoder. If a single input becomes
active, this input produces a specified output word. If more than one input becomes
active it encodes the input with the highest magnitude and ignores all lower magnitude
inputs.


                D7      A
                D6      B       outputs
                D5      C
inputs          D4
                D3                                             Truth Table
                D2                             CS D7 D6    D5 D4   D3 D2 D1      A B C
                D1                             0   x   x   x   x   x    x    x   0   0   0
                                               1   1   x   x   x   x    x    x   1   1   1
   enable          CS                          1   0   1   x   x   x    x    x   1   1   0
                                               1   0   0   1   x   x    x    x   1   0   1
                                               1   0   0   0   1   x    x    x   1   0   0
                Symbol                         1   0   0   0   0   1    x    x   0   1   1
                                               1   0   0   0   0   0    1    x   0   1   0
                                               1   0   0   0   0   0    0    1   0   0   1

				
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