Get documents about "Optoelectronic VLSI (OE-VLSI)
Document Sample
CHAPTER 1
INTRODUCTION
Optoelectronic VLSI (OE-VLSI) technology provides close integration of photonic
devices with VLSI- electronics. The goal is to supply multiple high performance optical
inputs and output signals, with aggregate data-rates up to and even exceeding a terabit-
per-second, to state-of-the-art VLSI circuits. OE-VLSI technologies are used most
effectively in systems where a a high-bandwidth “data-firehose” must be received,
switched or quickly processed by the electronic circuit, . Such a technology allows a
significant increase in integration density over all- electrical systems because the
functionality present in many separate electronic chips can be condensed into fewer
chips (and in some cases one single chip) with large numbers of optical inputs and/or
outputs (I/O’s). The use of OE-VLSI - “packaging” simultaneously affords a reduction
in the energy required to transmit digital signals within the system (and hence the
power-delay product of the system) by reducing (and in certain cases eliminating) the
parasitics associated with conventional packaging technology that use wire-bonds
between chips. This permits an increase in inter-connect speed for a given power
dissipation (or likewise, a reduction in power for a given system clock rate). Here the
benefits of intimately integrating the photonic devices to the VLSI circuits by
comparing an OE-VLSI technology to a more conventional packaging approach where
the photonic devices are wire-bonded to the electronics is also considered.
1
CHAPTER 2
SMART PIXEL AND OE-VLSI TECHNOLOGY
“Smart-pixel” technologies can employ materials with widely differing properties for
light detection, logic, and optical transmission. Various smart pixel technologies are
currently being developed. Most smart pixels are based on either silicon or gallium
arsenide substrates. The main logic families being considered here are silicon CMOS,
silicon bipolar, and GaAs - MESFET’s. As silicon– germanium - technology –matures,
this will also become a prime candidate for integration with photonic devices. Various
light detectors, transceiver circuits, and light transmitter device technologies have also
been proposed. OE-VLSI represents a generalization of smart-pixel technologies, in
that the concept of eachoptical I/O channel being associated with only a specific
subset of transistors on the chip (i.e., a pixel). Surface-normal optical interconnects to
VLSI circuits through either monolithic or hybrid integration methods. Compared to
high- performance all electronic systems, OE VLSI circuit technologies can offer a
relatively simple means of communicating large amounts of information to-and-from a
custom VLSI circuit, as well as a relative ease-of-design of the array.
2
CHAPTER 3
3. THREE LIGHT TRANSMITTED TECHNOLOGIES.
One factor in determining the suitability of a smart-pixel or OE-VLSI technology to a
given application is the light transmitter technology that is adopted. Three approaches are
presently under investigation: laser sources, LED sources, and light modulators. The first
approach has the advantage in that active light sources such as vertical-cavity surface-
emitting lasers (VCSEL’s) can provide large dynamic range and high contrast ratios .1
The optical system can also be simplified because no external laser is required. Surface
emitting lasers can be designed (with additional beam-shaping elements when necessary)
to efficiently direct the laser beam out of the smart pixel. When arrays of lasers are
integrated on a chip, substantial on-chip static power dissipation can ensue when the
lasers are biased above threshold. Although some ultra low threshold devices are now
being researched, VCSEL’s current 1mA and threshold voltages of 1.5–2 V. Light-
emitting diodes (LED’s) can be integrated on a large scale with GaAs logic and also with
silicon. They benefit from simpler fabrication and larger tolerance to processing
variations, but suffer from higher on-chip power dissipation and smaller modulation
bandwidth. The large spectral width of their emission and their large emission angles are
also the potential issues.
The light-modulator approach has the advantage that modulator fabrication processes can
be extremely simple and may be more consistent with logic technology. They are capable
of being produced in large arrays with high-yields. Light modulators are high-impedance,
capacitive devices(much like a CMOS gate) and hence can reduce the on chip dissipated
power. The excess heat dissipation due to the inefficiency associated with electrical-to-
optical conversion in the lasers is kept away from the electronic chip (although an
external light-source is then required). For high-speed digital interconnections, among the
well understood modulator is the multiple quantum well MQW)electro absorption (EA)
modulator. This is a capacitance device that can be switched at gigabits-per second.
3
FIG.- 1.
Structure of a 3-D hybrid GaAs MQW-modulator/silicon CMOS
circuit.
FIG-2
SEM photograph of the MQW diodes after bonding, substrate
removal, and epoxy removal.
4
FIG-3
Photomicrograph of one of the CMOS/MQW-modulator sub reticles that contains 16
distinct OE-VLSI chip designs. After bonding and substrate removal, each such sub
reticle integrates 3441 GaAs–AlGa As MQW diodes. Three columns of 80 diodes are
placed between the chips, in the saw-cut lanes. These are used for process-monitor
5
purposes after substrate-removal, prior to saw-cut. An additional diode, placed at the
reticle center is used for photo reflectance measurements.
6
CHAPTER 4
MONOLITHIC AND HYBRID INTEGRATION
Another critical feature that distinguishes smart-pixel or OE-VLSI technologies is the
choice of integration method used to create the OE circuits. These approaches can be
broadly classified as hybrid and monolithic. Monolithic integration may ultimately ensure
the manufacturability of large arrays of optical devices on VLSI electronics at lower cost
than the hybrid approach. It is also expected that the parasitic capacitance associated with
monolithic devices will be low. One new class of hybrid techniques, known as wafer-
fusion is applied at the wafer-level before the photonic devices are processed. This
technique involves fusing two wafers with different lattice constants under high-pressure
and elevated temperatures in contaminant-free environments. This technique has been
thus far used for fabrication of long-wavelength VCSEL’s and photo detectors for
telecommunications applications, but also is promising for OE-to-VLSI integration.
Another prefabrication technique is polyimide bonding where multiple chip-scale III–V
substrates can be bonded, using a polyimide layer, to a processed silicon wafer. Epitaxial
device layers are grown on the III–V chips before bonding, but processing of the
photonic devices is completed after the bonding to the silicon is performed VCSEL’s
grown on silicon substrates have been using this hybrid integration method.
7
CHAPTER 5
EPITAXIAL-LIFTOFF AND FLIP-CHIP BONDING
Chip-scale techniques for attaching processed photonic devices onto VLSI circuits.
These techniques include epitaxial liftoff and flip chip bonding. The epitaxial-liftoff
method involves the use of an artificial layer under the epitaxial device layers, that can
be selectively etched to separate the epitaxial layers from the substrate. A thin
membrane is typically used to transfer the devices to a host Silicon substrate. It has been
used to attach LED’s and photo detectors on Silicon circuits. The simplest and most
effective method of intimately attaching photonic devices to VLSI circuits today is flip-
chip bonding. Flip-chip bonding, currently used for commercial silicon packaging. The
procedure involves the preparation of the VLSI and GaAs chips with solder bumps,
followed by an alignment-and-bonding step. This is commonly done using thermo
compression bonding, although a thermo sonic-bonding The Ga As substrate can then be
removed after the devices are bonded to the host Silicon substrate; this differentiates the
flip-chip bonding technique from lift-off procedures where the substrate is removed
before the photonic devices are placed on the target substrate. A variant of this The flip-
chip bonding techniques now well-established for attaching large arrays of MQW
modulators and detectors operating at 850 nm to pre fabricated silicon circuits. Flip-chip
bonding has also been used to integrate VCSEL arrays with silicon and Ga As substrates.
8
CHAPTER 6
OE-VLSI INTEGRATION VERSUS WIRE-BONDING
The most widely used means of providing electrical connections between electronic
driver or receiver circuits and optical devices such as modulators and lasers, is wire-
bonding. A short-wire bond can provide a simple and cost effective means of connecting
the photonic devices to the transceivers electronics. It is generally believed that the
number of wire-bonds that will be possible to a single electronic chip, and the necessary
on-chip electrical routing to the wire-bond pads, will ultimately limit the electrical I/O to
a VLSI circuit. To determine the power-speed tradeoffs of on chip-versus off-chip
optical transceivers and hence to quantify the benefits of intimate integration of optical
transceivers onto -VLSI electronics, following parameters are considered.
6.1. Fundamental Bit-Rate Limit
The ideal case of a wire bond with an arbitrarily fast driver (zero source resistance), no
parasitic pad Capacitance, and perfectly matched load is discussed. Wire-bonded
packaging technology. Considering a long wire bond over a ground plane under the
assumption that the wire diameter is much smaller than its height above the ground plane
the “ideal” wire over a ground plane under the assumption that the wire diameter is much
smaller than its height above the ground plane the “ideal” wire, inductance is
Where d is the wire diameter ,h is its height above the plane, and are
respectively the permittivity and permeability of the medium. The dc resistance of the
wire-bond is small. The wire-bond resistance is given by
9
Where is the conductivity of the wire.
FIG-4
Inductance of a 50-_m-diameter 2-mm-long wire-bond as a function of
its height above the ground plane.
FIG-5
Wire-bond over a ground plane showing calculated field-lines: d is the diameter of the
wire-bond and h is its height above the ground
10
FIG-6
(a) Wire-bonded photonic device is assumed to have a parasitic capacitance of 1 pF and
an inductance of 1.5 nH. (b) Flip-chip bonded OE-VLSI device has a parasitic
capacitance of 70 fF and an inductance of 0.05 nH. exceeds the (bulk) resistive
impedance and the line transitions
11
FIG-7Photomicrograph of sub reticle showing a close up of the OE-VLSI chips, dicing
lanes, and process monitor diodes. Each chip integrates 200 diodes. Vertical and
horizontal pitch of the diodes are 62.5 and 125 _ respectively. Each diode is
approximately 25 with an active area of approximately
12
6.2. Limits Due to Parasitic Pad Capacitance and Wire Inductance.
The previous section reviewed the ideal case of a wire bond with an arbitrarily fast
driver (with zero source resistance) and no parasitic pad capacitance. Here we will
discuss a practical realization where there are finite parasitic capacitance and inductance
associated with the connection between the driver circuits and the device being driven,
even when these distances are physically short. These will specifically include the on
chip Inter connection capacitance, the bond-pad capacitance, the bond-inductance, and
the device capacitance. For a wire with a finite length , diameter , located at a height
above the ground plane, the wire inductance is explained above. Where is the
permeability of the medium (in this case air). The inductance of the wire-bond can be
reduced by positioning the wire closer to ground.
FIG-8
Equivalent circuit of VLSI circuit driving optoelectronic device Network
consists of a driver circuit, a bond-pad, a hybrid bond (wire-bond or flip-
chip bond), a second bond-pad, and the OE device. (b) Simplified network
for calculation of 3-dB bandwidth of wire-bonded photonic device.
13
6.3. Circuit Models for the Photonic Transceivers
The network assumed in this paper is shown in above figure. R-source is the source
resistance of the line driver. The transmitted signal from the driver experiences a
capacitive discontinuity at the bond-pad, an RLC line corresponding to the wire bond (or
flip-chip bond), another capacitive discontinuity at the second (photonic) chip, and finally
the photonic load device impedance itself. C-pad represents the sum of the capacitance
of a pad (either wire-bond pad or flip-chip pad) together with the stray capacitance of any
on-chip wiring to and from the pad. L-bond,R-bond, ,and C-bond , are respectively the
inductance, resistance, and capacitance of either the wire-bond or the flip-chip bond.
Finally and are, respectively ,The CL and RL are the load capacitance and resistance of
the OE device. For the wire-bond case, note that C-bond and C-load are approximately
equal, and the parasitic capacitance is dominated by the bond-pad capacitance. Because
the wire bond is short, we use a lumped model for the wire-bond where C-bond and L-
bond are, respectively, the capacitance and inductance of the bond. The resulting
simplified network configuration is shown in above Fig. (b) and can be recognized as a
simple low-pass filter with a (3-dB) cutoff frequency ( fc)given by
We will for the moment ignore the effect of the driver resistance (R--source ). We will
also assume that the line is terminated with an impedance of value , so that R-load is
chosen to precisely match the line impedance If we make the approximation that digital
non return-to zero(NRZ) transmission of full logic swing can be reliably executed at
about one fourth the cutoff frequency (clock frequency of bits/clock-cycle), then we find
that the maximum bit rate of this simple wire-bonded OE device ,assuming perfect
termination, is approximately 15 Gb/s. Note that this estimate has assumed zero-
impedance line drivers. Drivers with non zero source resistance will cause attenuation
of the logic signal and deterioration of the bit rate.
14
6.4. Parallel (Load) Termination Versus Series (Source) Termination
Here, a practical realization where there are substantial on-resistance associated with the
driver in addition to the parasitic capacitance and inductance associated with the physical
connection between the driver circuits and the device being driven is discussed. These
will specifically include the inter connection lines on the substrates, the wire-bond pad
capacitance and inductance and the capacitance of the photonic device. It is generally
known that a properly designed parallel terminated transmission line provides the ability
to increase bit rates by removing unwanted signal reflections. As depicted in Fig. 9(a),
the source resistance is designed to be as small as possible, and the load resistance in the
ideal case is matched to the line-impedance Z0 , so that the signal at the load experiences
no reflections. Parallel or “load” termination is typically required at operating frequencies
where the bit period (t b ) of the signal is less than twice the time-of-flight( tb) across the
link. However, parallel-terminated matched transmission lines can be power-inefficient
due to constant dc power dissipation; terminated in parallel with a matched resistor.
Further more, in CMOS circuit technologies, low-impedance drivers always have larger
buffer delays, more power dissipation and require more area to implement. This is
because more stages of cascaded inverters, with large current carrying capability are
required to achieve a low-source impedance. For short links on the order of a few
millimeters, and bit rates in the regime of 1–10 Gb/s (i.e., frequencies where the
wavelength is large compared to the interconnection distance),series or “source”
termination can provide a high speed ,low-power alternative to parallel termination .In
the ideal source-terminated circuit [Fig. 9(b)] the source-resistance of the driver is equal
to the line impedance, and the load resistance is infinite (open circuit). In this ideal case,
a signal reflection is incurred, and is terminated at the driver. From a circuit point-of-
view, drivers with high-source impedance driving high-impedance loads are desirable
because these typically require smaller drive currents; hence they are easier to drive with
on-chip buffers. However, as the source impedance is increased, and drive currents
reduced, circuit speed can degrade significantly due to capacitive discontinuities along
the signal path; examples of such discontinuities would be parasitic pad capacitance and
load capacitance. The delay and rise time of the network are essentially dictated by the
output (source) resistance of the driver and the parasitic capacitance of the network
15
interconnecting the driver with the photonic device. Because Z0 increases with the line
inductance (which includes self- and mutual-inductance), high impedance lines are also
more prone to crosstalk, which can become a significant issue for parallel data
transmission on multiple lines.
FIG-9
In the Parallel (load) versus series (source) termination.9 (a) Schematic for a parallel-
terminated circuit. In the ideal case, the load resistance (RL) is equal to the line
impedance (Z0) and the source resistance is negligible-9(b) Schematic for a source-
terminated circuit. In the ideal case the source-resistance is equal to the line impedance,
and the load resistance is infinite.
16
6.5. Performance of Source-Terminated Drivers
In this section, we examine the performance of source terminated photonic drivers for
both wire-bonded and flip-chip bonded cases. To do this, we model both analytically, and
via simulation, the behavior of a simple source-terminated transmission line where the
source resistance is allowed to vary with respect to the effective impedance of the
network. The simplified network assumed for analytical modeling is shown in Fig.
8(b).R-source is assumed to be the source resistance of the driver, (i.e., part of the driving
transistor shown in the figure). We make the assumption that the resistance (R-bond) of
the wire-bond is negligible and can hence be ignored. This amounts to an assumption of a
lossless transmission line.2 To analytically model the behavior of a source-terminated
line as the source resistance varies, we make the further assumption of a lumped network
(valid for short wire-bonds in the 1–10 Gb/s regime), and perform an s-parameter
analysis of the circuit in the Laplace domain to obtain an expression for as a function of
the input voltage (Vin ). This is then simulated for an ideal step input.
The result is shown in Fig. 8(a), which graphs the response of the wire-bonded photonic
transceiver versus time to the ideal unit-step input for two (limiting) cases of the source
resistance (shown as R=20ohm , and R=200 ohm ). As can be seen from the figure, a
higher source resistance leads to lower bandwidth (due to the larger time constant).
On the other hand, a very low-resistance source provides higher bandwidth but results in
ringing, even for short wire-bonds, which can causes errors due to overshoot and
undershoot. Fig. 8(b) graphs the instantaneous power dissipation as a function of time for
the wire-bonded transceiver for the two limiting resistance values.
It is evident that low source-resistance drivers result in much higher peak power
dissipated in the circuit and will also exhibit a higher average power dissipation for a
given bit rate. To confirm the validity of the analysis, SPICE simulations of the network
17
in Fig. 8(a) is performed with the wire bonded photonic transceiver parameters as before.
The unit step function input was replaced a 50-ps rise time signal characteristic of high-
speed electronics.3 For these simulations, we assumed that the photonic device required a
voltage drive of 3.3 V, although the behavior of the curves are, to first order, independent
of the supply voltage.
The source-resistance parameter was varied between 20–200 . A 3-D plot of the
simulation results is graphed in Fig. 10(a), which is in 2We note that at high speeds, most
transmission lines experience some loss due to skin-effect related resistance. Indeed,
this resistive loss can be used to benefit because it serves to “damp” out the oscillations
caused by multiple reflections However, for short wire-bonds this is a small effect and
will not substantially affect the results. This finite rise time signal represents more
realistic conditions and results in slightly less ringing as the rise time is increased. This
allows a slightly lower resistance (i.e., lower RC time constant) for a given amount of
ringing. However, this is offset by the slight increase in the rise time of the output
signal, and hence does not substantially change the results on the maximum bandwidth
of the wire-bonded device or the power dissipation for a given bit can be determined.
FIG-10
(a) 3-D Plot of simulated response of the network in Fig. 8(a) illustrating output rise and
fall times as a function of the source resistance of the driver. The input was a ramp with
50-ps rise- and fall times. A high-impedance load device with capacitance of 100 fF was
used for these simulations.
(b) Cross section of the 3-D plot. Given a specific bit-rate target, the maximum source-
resistance (and hence the minimum power dissipation) can be determined. Given a
maximum allowable ringing of 25%, a minimum value of source resistance and hence a
maximum overshoot-limited bit rate
18
FIG-11
Calculated response of the network in Fig. 6(b) versus time to the ideal unit-step input as
a function of the source resistance (R). (a) Low-resistance source provides higher
bandwidth but results in ringing which causes errors due to overshoot and undershoot. A
19
high-resistance source results in reduced bandwidth due to the parasitic c power
dissipation. (b) Instantaneous power dissipated in the circuit capacitance in the network,
but also reduces power dissipation Fig. 9. (a) 3-D Plot of simulated response of the
network in Fig. 6(a) illustrating output rise and fall times as a function of the source
resistance of the driver. The input was a ramp with 50-ps rise- and fall times. A high-
impedance load device with capacitance of 100 fF was used for these simulations.
..
FIG-12
Calculated response of the network in Fig. 8(b) versus time to the ideal unit-step input as
a function of the source resistance (R). Low-resistance source provides higher bandwidth
20
but results in ringing which causes errors due to overshoot and undershoot. A high-
resistance source results in reduced bandwidth due to the parasitic capacitance in the
network, but also reduces power dissipation.
6.6. Flip-Chip Versus Wire-Bonded Photonics
The preceding analysis is also valid for characterizing the performance of flip-chip
bonded photonic devices, with the appropriate values for the parasitic inductance,
resistance, and capacitance of the flip-chip bonds. In comparison, the equivalent flip-chip
bonded circuits do not exhibit ringing
effects at the time-scales being discussed here, due to their lower parasitic capacitance
and inductance values. Compared to the wire-bonded case the maximum bit-rate limit for
the flip-chip bonded transceiver (assuming no driver bandwidth limits) is on the order of
60 Gb/s. Alternatively, for a given bit rate, this allows the use of a much larger source-
resistance (and hence lower power) driver. Because high-impedance, low-power drivers
typically require less area to implement, this also translates into a direct cost savings for
the electronics. It is then possible to directly compare the performance of the flip-chip
bonded OE-VLSI transmitter with the wire-bonded transmitter. Each link is designed to
21
minimize power dissipation (by maximizing the source resistance at a given bit rate)
under the constraint that only a controlled amount of signal-degradation (due to multiple
reflections) will be allowed. In order to simplify the analysis, the bit-period (T ) is taken
to be twice the rise time of the output signal (Vout ), where the rise time is defined as the
time the signal takes to rise from 10% of the logic swing and settle to within 90% of the
swing. Fig. 9(b) illustrates this principle. Given a specific bit rate, the maximum source-
resistance (and hence the minimum power dissipation) can be determined. The
assumption is made that undershoot caused by ringing (for the wire-bonded transceiver)
must be kept to within 25% of the logic swing. Given a maximum allowable ringing of
25%, a minimum value of source resistance and hence a maximum overshoot-limited bit
rate can be determined. Finally, the power dissipation is calculated from
Where is the instantaneous power [from Fig. 8(b)],T is the bit-period (twice the rise
time), Vin^2 is the assumed logic swing and k is a constant approximately equal to 9. The
approximation in (8) is valid for a wide range of resistance values and can be used to
estimate the average power dissipation for the transmitter circuits. Following the
procedure described above for both wire bonded transceivers and flip-chip bonded
transceiver at each bit rate, we can plot the (minimum) power dissipation of each
transceiver as a function of bit rate (Fig. 13). Curves are drawn for 16, 32, 64, and 128
devices, clearly illustrating the advantages of the OE-VLSI approach. We also see the
ringing-limited bit rate of the wire-bonded approach when source terminated electronic
drivers are used. As we might have expected, the OE-VLSI approach provides lower-
power transmitters even at low bit rates. But beyond a few Gb/s (approximately 2.6 Gb/s
for the assumed parasitic), the wire bonded approach begins to fail when using source-
terminated drivers. At these bit rates there is a clear bandwidth and power dissipation
22
advantage to the OE-VLSI approach, even at surprisingly low numbers of integrated
photonic devices.
FIG-13
Maximum bit rate for wire-bonded versus flip-chip bonded EA modulators using source-
terminated driver-electronics. Curves are drawn for16, 32, 64, and 128 devices, showing
the power-speed advantages of the OE-VLSI approach.
6.7. Driving Low Impedance Photonic Devices (e.g., VCSEL’s)
The specific bandwidth and power limits calculated for wire bonded versus integrated OE
are in general accurate only for modulators, since these are high-impedance devices that
can be modeled as a purely capacitive load. The analysis can be considered to be
approximately valid for VCSEL’s driven from below threshold (seen as high impedance
over the initial part of the signal). For VCSEL’s biased above threshold, lasers, and other
low-impedance devices, the analysis should include a termination resistance that may not
23
necessarily be matched with respect to the line or to the drive resistance. For this case,
analysis and SPICE simulations suggest that signal reflections may be somewhat reduced
(compared to the high-impedance load case) allowing the traditional source terminated
wire-bonded solution to operate at slightly higher speed for the same values of the
parasitic capacitance and inductance. For low impedance loads, the power dissipation
benefits of the source-terminated flip-chip bonded solution are also somewhat reduced
(compared to the high-impedance loads) due to the short-circuit dc power dissipation.
24
CHAPTER 7
SUMMARY AND CONCLUSION
In this paper, we briefly reviewed the motivations and status of emerging OE- VLSI
technologies. All the OE-VLSI integration techniques reviewed in this paper have the
common goal of providing dense integration of OE devices to VLSI circuit with
minimum electrical parasitic, i.e., low capacitance, resistance and inductance. The
purpose of the remainder of the paper was to compare the performance of such an O E
Device to that of a conventional wire-bonded OE circuit. Specifically, we have attempted
to quantify the power-speed benefits of a hybrid flip-chip bonded OE-VLSI technology to
a low-cost, wire-bonded OE packaging technique as a function of array size (i.e., the
number of OE devices attached to the VLSI circuit). To do this, we examined the
behavior of a simple series-terminated transmission line where the source resistance not
perfectly matched to the line-impedance, but instead is designed to minimize power
dissipation at the expense of a controlled amount of signal-degradation due to ringing.
The specific values for the parasitic that were assumed for the OE-VLSI technology was
based on recent measurements of flip-chip bonded MQW modulators on CMOS,
although the results in general are relevant to all intimate integration techniques that
provide low-parasitic interconnections to single, linear, or 2-D arrays of photonics
devices. It is important to note that efforts to extract high-speed performance from
conventional wire-bond packaging technology will necessitate the use of very-low-
resistance drivers and end-terminated (matched) transmission lines. These high
performance packaging techniques are not those typically associated with high-volume
electronics, but are instead the preview of special-purpose logic technologies and
microwave packaging. As the simple analysis presented in this paper indicates, attempts
at chip-to-chip packaging will begin to fail beyond 15 Gb/s or so (the photonic device
cutoff depending on the precise values of the parasitic). These load-terminated photonic
driver circuits are also very power hungry, which makes the integration of more than a
few high-speed drivers difficult. Furthermore, it essentially rules out the possibility of
conventional CMOS driver circuits which typically have significant source
resistance. When these microwave packaging techniques are abandoned for simpler (and
cheaper) source-terminated drivers the performance of the wire-bonded transceivers
25
dramatically drops to a few gigabits due to ringing effects. The advantages of OE-VLSI
integration are then manifest. The lower parasitic capacitance for the smaller bonds
allows the use of a larger source-resistance (and hence lower power) driver for a given bit
rate. Because high-resistance, low power drivers typically require less area to implement,
this also translates into a direct cost savings for the electronics. OE-VLSI integration
approach. Furthermore, the elimination of the wire-bond inductance removes the bit-rate
limitation due to ringing effects, allowing much higher speed operation of the OE devices
than would otherwise be possible with low-cost electronic packaging and simple silicon-
based source-terminated driver circuits. Compared to the wire-bonded case the maximum
bit-rate limit for the flip-chip bonded transceiver (assuming no driver bandwidth limits) is
on the order of 60 Gb/s. Due to this power and speed benefit, a general conclusion is that
OE-VLSI integration will be beneficial not only for large 2-D arrays, but also for linear
arrays or even discrete OE components.
26
CHAPTER 8
REFERENCES
[1] A. V. Krishnamurthy and D. A. B. Miller, “Firehose architectures for free-space
optically interconnected VLSI circuits,” J. Parallel and Distributed Computing, vol. 41,
pp. 109–114, 1997
[2] H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J.
Select. Areas. Commun., vol. 6, pp. 1209–1226, Sept.. 1988.
[3] F. Kiamilev, S. C. Esener, R. Paturi, Y. Fainman, P. Mercier, C. C. Guest, and S. H.
Lee, “Programmable optoelectronic multiprocessors and their comparison with symbolic
substitution for digital optical computing,” Opt. Eng., vol. 28, no. 4, pp. 396–408, Apr.
1989.
[4] A. V. Krishnamoorthy and D. A. B. Miller, “Scaling optoelectronic- VLSI circuits
into the 21st century: A technology roadmap,” IEEE J. Select. Topics Quantum Electron.,
vol. 2, pp. 55–76, Apr. 1996. [5] J. W. Goodman and E. Schenfeld, Eds., Special Issue on
massively
[5] www.wikipedia.com
27
