Flash memory technology

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					10             FLASH MEMORY TECHNOLOGY




OVERVIEW


Flash memory technology is a mix of EPROM and EEPROM technologies. The term ÒflashÓ was
chosen because a large chunk of memory could be erased at one time. The name, therefore, dis-
tinguishes flash devices from EEPROMs, where each byte is erased individually.


Flash memory technology is today a mature technology. It is a strong competitor to other non-
volatile memories such as EPROMs and EEPROMs, and to some DRAM applications.


HOW THE DEVICE WORKS


The more common elementary
flash cell consists of one transistor                  ONO DIELECTRIC                  POLY 2 WORD/SELECT

with a floating gate, similar to an
                                                                                        POLY 1 FLOATING
EPROM cell. However, technology                                                               GATE


and geometry differences between
flash devices and EPROMs exist. In                 N+ S/D
                                                                                          N+ S/D


particular, the gate oxide between
the silicon and the floating gate is
thinner for flash technology.                                      EPROM MEMORY CELL

Source and drain diffusions are also
different. These differences allow
the flash device to be programmed
                                                                                         POLYCIDE
and erased electrically. Figures 10-
                                                                                        ONO
1 and 10-2 show a comparison                         OXIDE ON N+


between a flash memory cell and an                                           POLY 1

EPROM cell from a same manufac-
turer (AMD) with the same technol-                      N+ S/D
                                                                          GATE OXIDE 1

ogy complexity. The cells look
similar since the gate oxide thick-                                 FLASH MEMORY CELL
                                               Photos by ICE, “Memory 1997”                          22482
ness and the source/drain diffusion
differences are not visible in the
                                      Figure 10-1. AMD EPROM Versus AMD Flash Memory Cells
photographs.



INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                             10-1
Flash Memory Technology




                                                                                Cell Gate
                              Type       Density        Date Code   Cell Size
                                                                                 Length
                             Flash        4Mbit           9406       6µm2        0.7µm
                            EPROM         1Mbit           9634      5.52µm2      0.7µm
                          Source: ICE, "Memory 1997"                                  22483


                             Figure 10-2. EPROM Versus Flash Cell (AMD)


Other flash cell concepts are based upon EEPROM technology. Figure 10-3 shows a split-gate cell
and Figure 10-4 shows a transistor with the tunnel oxide in only a part of the oxide under the float-
ing gate. These cells are larger than the conventional one-transistor cell, but are far smaller than
the conventional two-transistor EEPROM cell.




                          Photo by ICE, “Memory 1997”                              22480



                                      Figure 10-3. Split Gate Flash Cell




                          Photo by ICE, “Memory 1997”                              22481



                                  Figure 10-4. Tunnel Window Flash Cell




10-2                                                         INTEGRATED CIRCUIT ENGINEERING CORPORATION
                                                                                    Flash Memory Technology




The electrical functionality of the flash memory cell is similar to that of an EPROM or EEPROM.
Electrons are trapped onto the floating gate (see a detailed description in Section 9). These elec-
trons modify the threshold voltage of the storage transistor. Electrons are trapped in the floating
gate using Fowler-Nordheim tunneling (as with the EEPROM) or hot electron injection (as with
the EPROM). Electrons are removed from the floating gate using Fowler-Nordheim tunneling as
with the EEPROM. Figure 10-5 summarizes the different modes of flash programming.


                                          Electron Trapping                 Electron Removal


                                                                  VCG


        Bi-polarity FN-t
         Write / Erase
          technology


                                       Fowler-Nordheim tunneling


                                                                                     Vsub
                                                                  VCG


          Hot-Electron            VD                                    Fowler-Nordheim tunneling
       injection and FN-t
           technology


                                         Hot-Electron Injection


     Source: ICE, "Memory 1997"                                                                     20840



               Figure 10-5. Comparison Between the Different Types of Flash Programming



Figure 10-6 summarizes chip and cell sizes of some of the flash memories analyzed by ICE’s lab-
oratory. Most of these are date coded 1994 but give a good idea of what is widely used in 1997.
All these memories use the NOR flash architecture. A photo of SanDisk’s 32Mbit flash cell (used
on its CompactFlash cards) featuring a cell size of 1.8µm2 is shown Figure 10-7.


ARCHITECTURE


As with other semiconductors, the flash memory chip size is the major contributor to the cost of
the device. For this reason, designers have developed alternative memory array architectures,
yielding a trade-off between die size and speed. NOR, NAND, DINOR, and AND are the main
architectures developed for flash memories.




INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                                  10-3
Flash Memory Technology




                                                              Cell Size                         Gate       Die Size
                                Density     Date Code                         Cell Type
                                                               (µm2)                         Length (µm)    (mm2)
           SST                   1Mbit            9417          10.2          Split Gate         0.95       29.0
           AMD                   2Mbit            9325           8.0                  1T         0.80       51.2
           AMD                   4Mbit            9406           6.0                  1T         0.70       49.8
           ATMEL                 4Mbit            9411          16.6       Tunnel Window         N/A       107.0
           INTEL                 16Mbit           1993           3.3                  1T         0.75      123.6
           AMD/FUJITSU           16Mbit           9436           2.7                  1T         0.60       87.0
         Source: ICE, "Memory 1997"                                                                                22479



                                 Figure 10-6. Flash Chip and Cell Size Comparison




                                                                            METAL BIT LINE


                                                     POLY 3

                                                    POLY 2
                                               POLY 1


                                            W
                                           PLUG

                                                                  DIFFUSED BIT LINE




                                                         Control Word Control
                                                         (Poly 2) (Poly 3) (Poly 2)



                                                     Q1                           Q3


                                                     Q2                           Q4



                                  Photo by ICE, “Memory 1997”                                  22478



                                              Figure 10-7. SanDisk Flash Cell

NOR Cell


The NOR architecture is currently the most popular flash architecture. It is commonly used in
EPROM and EEPROM designs. Aside from active transistors, the largest contributor to area in the
cell array is the metal to diffusion contacts. NOR architecture requires one contact per two cells,
which consumes the most area of all the flash architecture alternatives. Electron trapping in the
floating gate is done by hot-electron injection. Electrons are removed by Fowler-Nordheim tunnel-
ing. The worldÕs leading manufacturers of flash devices (Intel, AMD) use NOR cell configurations.




10-4                                                                   INTEGRATED CIRCUIT ENGINEERING CORPORATION
                                                                                 Flash Memory Technology




NAND Cell


To reduce cell area, the NAND configuration was developed. Figure 10-8 shows the layouts of
NOR and NAND configurations for the same feature size. The NAND structure is considerably
more compact.


                  ,,, ,,
                  NOR-CELL
                                         ,,,     ,,,       ,,       ,,,     ,,   ,,
                  ,,, ,,
                  ,,, ,,                 ,,,
                                         ,,,     ,,,
                                                 ,,,       ,,
                                                           ,,       ,,,
                                                                    ,,,     ,,
                                                                            ,,   ,,
                                                                                 ,,
                  ,,, ,,                 ,,,     ,,,       ,,       ,,,     ,,   ,,


                          ,,,,,,,, ,,,,,,,,,
                   NAND-CELL
                                 ,,,
                                 ,,,
                          ,,,,,,,, ,,,,,,,,,
                                 ,,,
                          ,,,,,,,, ,,,,,,,,,
                                 ,,,
                          ,,,,,,,, ,,,,,,,,,
                         Floating Gate

                                      Control Gate


               ,,,,,,,,,,,,,,,,
                Select Gate                                       Select Gate



               ,,,,,,,,,,,,,,,,
                                                     Bit Line (Aluminum)


               ,,,,,,,,,,,,,,,,
                                                       P-Well
                                    N+
                Source: ICE, "Memory 1997"                                            19960



                      Figure 10-8. Comparison of NOR and NAND Architectures


A drawback to the NAND configuration is that when a cell is read, the sense amplifier sees a
weaker signal than that on a NOR configuration since several transistors are in series. Figures 10-
9 and 10-10 describe the NAND architecture from Toshiba. The weak signal slows down the speed
of the read circuitry, which can be overcome by operating in serial access mode. This memory will
not be competitive for random access applications. Figure 10-11 shows a speed comparison of
NOR and NAND devices.


DINOR Cell


DINOR (divided bit-line NOR) and AND architectures are two other flash architectures that
attempt to reduce die area compared to the conventional NOR configuration. Both architectures
were co-developed by Hitachi and Mitsubishi.




INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                          10-5
Flash Memory Technology




                                                      EMBEDDING
                                                      COMPOUND



                                                                                   POLY 3                METAL


                                                       POLY 2




                                                                              N+                        POLY 1
       EDGE CELLS                                                                                                EDGE CELLS


   Photo by ICE, “Memory 1997”                                                                                            22476



                                       Figure 10-9. Toshiba Flash NAND Cell



                                              Architecture               NAND
                                              Date Code           9528
                                              Cell Size           1.3µm2
                                              Die Size            103mm2
                                              Min Feature         Cell: 0.25µm
                                              Size (Gate)         Periphery: 0.5µm
                                            Source: ICE, "Memory 1997"                  22475



                                 Figure 10-10. ToshibaÕs 32Mbit Flash Characteristcs




                                            Architecture                 NOR                NAND

                                      Random Access Time                 80ns               20µs

                                       Serial Access Time                 —                 80ns

                                    Source: ICE, "Memory 1997"                                  19961



                                  Figure 10-11. NOR Versus NAND Access Times


The DINOR design uses sub-bit lines in polysilicon. Mitsubishi states that its device shows low
power dissipation, sector erase, fast access time, high data transfer rate, and 3V operation. Its
device uses a complex manufacturing process involving a 0.5µm CMOS triple well, triple-level
polysilicon, tungsten plugs, and two layers of metal. Figure 10-12 shows the DINOR architecture.


AND Cell


With AND architecture, the metal bit line is replaced by an embedded diffusion line. This pro-
vides a reduction in cell size. The 32Mbit AND-based flash memory device proposed by Hitachi
needs a single 3V power supply. In random access mode, the device is slower than a NOR-based
device. HitachiÕs device is specified to operate with a 50ns high-speed serial access time.



10-6                                                                INTEGRATED CIRCUIT ENGINEERING CORPORATION
                                                                                                              Flash Memory Technology




       ,
    ,,,,,,,                 ,
                                 Second Al




       ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
        ,,,, ,,, ,,, ,,,, ,,,,, ,,,, ,,,, ,,
       ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
       ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
       ,,,,, ,,, ,,, ,,,, ,,,,, ,,,, ,,,,
        ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
                            ,
                                                   Sub-Bit Line (Polysilicon)                          Main Bit Line (First Al)




                                                                        12.7µm (1.6µm/Cell)
              Select Transistor
       Source: Mitsubishi/ICE, "Memory 1997"                                                                               19962A



                                                  Figure 10-12. DINOR Architecture


Figure 10-13 presents a review of the different flash architectures. Figure 10-14 shows a cell size
comparison between DRAM, NAND, and NOR flash architectures. The NOR flash one-transistor
cell has roughly the same size as a DRAM cell for the same process generation.


                                 NOR ARCHITECTURE                                         NAND ARCHITECTURE

                              Bit 1       Bit 2       Bit 3                                          Bit 1        Bit 2
              Word 1                                                                       Select Gate 1


                                                                                           Word 1


              Word 2                                                                       Word 2


                                                                                           Word 3


              Word 3
                                                                                           Word 8

                                                                                          Select Gate 2



                                                              Source
                                                              For One
                                                               Block                       AND ARCHITECTURE
                                                                                                          Bit 1           Bit 2

                                                                                     Select Gate 1
                             DINOR ARCHITECTURE
        Main Bit Line                                                                Word 1
          (Metal)

     Select Tr2 Select Tr1             Sub Bit Line (Polysilicon)                    Word 2
                        Word 1                                            Word 8
                                                                                     Word 3




                    Source Line
                                                                                     Word 8



                                                                                     Select Gate 2



             Source: ICE, "Memory 1997"                                                                                      19963


                                                  Figure 10-13. Flash Architectures


INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                                                           10-7
Flash Memory Technology




                            Technology           NAND Flash        NOR Flash
                                                                                DRAM Cell
                           (Gate Length)            Cell             Cell

                                 0.6µm                 3µm2          6µm2          6µm2
                                 0.4µm                 1.3µm2        2.5µm2       2.5µm2
                        Source: ICE, "Memory 1997"                                        22474



                        Figure 10-14. Flash and DRAM Cell Size Comparison



Several companies strongly support one type of flash architecture. However, to hedge their bets
and to offer products for several different end uses, many firms have elected to build flash devices
using more than one type of architecture. Figure 10-15 shows vendors’ support of flash memory
architectures.


                                    NOR                NAND         AND         DINOR

                            Intel                    National     Hitachi      Mitsubishi
                            AMD                      Samsung      Mitsubishi   Hitachi
                            Atmel                    Toshiba                   Motorola
                            Fujitsu                  Fujitsu
                            TI                       AMD
                            Micron
                            SGS-Thomson
                            Macronix
                            UMC
                            Mitsubishi
                            Samsung
                            Toshiba

                          Winbond uses its proprietary "split-gate" architecture.
                          Source: ICE, "Memory 1997"                                 20080C



                   Figure 10-15. Vendors’ Support of Flash Memory Architectures



Audio NAND Flash


Toshiba, Samsung, and National Semiconductor each introduced 4Mbit serial audio NAND flash
devices. Their devices used the NAND cell configuration. These parts, used for telephone
answering machines or other audio data storage, have started to replace audio DRAMs. Based on
the small NAND cell, audio NAND flash uses serial access to face speed problems. Moreover,
audio NAND devices are cheaper than standard NAND flash since they contain fewer functions.
Sometimes audio flash devices may contain some bad cells. Even though those faulty cells would
not affect the audio applications, the product would sell for less money.




10-8                                                            INTEGRATED CIRCUIT ENGINEERING CORPORATION
                                                                                     Flash Memory Technology




MULTI-LEVEL STORAGE CELL (MLC)


Four-Level Storage Cell


Most of the major flash companies are working to develop their version of a multi-level cell flash
device. The goal of this device is to store information in several different levels inside the same
memory cell. The most common developments are those that store information on four different
levels in the same cell.


In multi-level cell, there are two difficult issues that must be addressed by manufacturers. The
first is to tightly control the program cycle that gives four different levels of charge. The second
difficulty is to accurately recognize, during the read cycle, the four different threshold voltages of
the programmed transistor.


Flash devices must be reliable even in worst case conditions. External parameters (power sup-
plies, temperatures, etc.) may vary from the time the flash device is programmed to the time it is
read. Figure 10-16 shows an example of threshold voltage distribution for four stages stored on
the same transistor.


                             Cell Distribution
            "11"                                 "10"    "01"                 "00"




                                                                                                      VT
Source: ICE, "Memory 1997"                                                                                 20805



                              Figure 10-16. Threshold Voltage Distribution for Four States


Different companies are working intensively on this issue. During each of the past several years,
papers were presented by most of the major flash manufacturers regarding multi-level cell tech-
nology. Intel presented a paper on its four-level storage work at the 1995 ISSCC conference. At
the 1996 ISSCC conference, two papers were presented on this concept. Samsung presented a
128Mbit four-level NAND flash cell and NEC presented a 64Mbit four-level NOR flash cell. At
the 1995 Symposium on VLSI Circuits, Toshiba presented a development for future high density




INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                              10-9
            Flash Memory Technology




            MLC NAND flash memories. At the December 1996 IEDM Conference, SGS-Thomson presented
            a study on MLC for the different flash architectures and their trade-offs. Highlights of this study
            are presented in Figure 10-17.


                                                     Advantage as              Disadvantage as             Advantage as                Disadvantage as
     Array Architecture           Cell Size*
                                                   Single-Bit Concept         Single-Bit Concept          Multi-Bit Concept            Multi-Bit Concept

Common Ground                       9-11F2     1. General purpose          1. Relatively large         1. Minimum interaction  1. Closely coupled
                                                  applications and most       cell size                   between neighbors       metal bitline
                                                  understood array and                                 2. CHEI for programming 2. Vt distribution affected
                                                  technology                                                                      by neighbor data

DINOR                                7.5F2     1. Reduced cell size while 1. Requires triple poly      1. Reduction in BL-BL      1. Tunneling during
                                                  preserving the common                                   coupling                   programming
                                                  ground array                                                                    2. Source resistance

AND                                      8F2   1. Good combination of                  —               1. Reduction in BL-BL      1. Tunneling during
                                                  CG and DINOR                                            coupling                   programming
                                               2. Drain contact every                                                             2. Source resistance
                                                  32-128 cells

NOR Virtual Ground -                     6F2   1. Small cell size                      —               1. CHE programming         1. Resistive diffusion
AMG                                            2. Low current                                          2. Reduction in BL-BL         bitlines
                                                  programming                                             coupling                2. Neighbor interaction
                                                                                                                                     affecting Vt distribution

NOR Virtual Ground -                 7.5F2     1. Overerase not an issue   1. Requires triple poly     1. CHEI programming        1. Neighbor interaction
Split Gate Poly-Poly Erase                                                                             2. Disturb reduction due      affecting Vt distribution
                                                                                                          to poly-poly erase      2. Low read current and
                                                                                                                                     high erase voltages

NAND                                     6F2   1. Small cell size          1. Read thru stack of                  —               1. Programming by tunnel-
                                                                              15 cells                                               ing in the channel
                                                                           2. High read and program-
                                                                              ming voltages

*F is the technology feature size
Source: SGS-Thomson/ICE, "Memory 1997"                                                                                                                     22595



                                         Figure 10-17. Trade-Off of MLC Using Different Flash Architectures



            During the first half of 1997, Intel announced that it sampled 64Mbit MLC parts. SanDisk, along
            with manufacturing partner Matsushita, used the technology to boost single-chip capacity to
            64Mbit. It refers to its multi-level cell technology as “Double Density” or “D2”. SanDisk claims
            that the 64Mbit die is only 10 percent larger than the company’s 32Mbit die. Meanwhile, the com-
            pany is also working on a 256Mbit Double Density flash device.


            Multi-Level Storage Cell for Audio Applications


            Development of MLC cell takes considerable time because digital storage needs to be reliable. The
            data needs to stay valid in worst-case conditions. For audio applications, however, tolerances
            allow for some error. For this reason, Information Storage Devices (ISD) proposed non-volatile
            memories that are able to store 256 different levels on the same transistor. ISD’s product family is
            called ChipCorder and enables a single chip solution for voice recording and playback. It cur-
            rently has a chip with up to four minutes of voice storage capacity.



            10-10                                                                 INTEGRATED CIRCUIT ENGINEERING CORPORATION
                                                                                        Flash Memory Technology




POWER SUPPLY


Currently, flash power supplies range from 5V/12V down to 2V. Flash memory power supplies
vary widely from vendor to vendor. There are two main reasons for this variation. First, flash
cells need high voltage for programming. With different types of flash architectures and designs,
different program/erase techniques (Fowler-Nordheim tunneling or hot-electron injection) exist.
These architectures do not share the same voltage requirements. For example, high voltage with
no current can be generated internally with a voltage pump. However the source/drain current
of hot-electron injection requires an external power supply.


The second reason for wide power supply variation is that there are many applications that cur-
rently require different power supply levels. Some applications may require low-voltage flash
devices while others operate well using flash device with high-voltage characteristics.
Manufacturers can propose different types of power supplies that best fit a specific application.


SmartVoltage


SmartVoltage is an Intel concept. However, other manufacturers including Sharp and Micron
have signed on to license the technology. SmartVoltage parts can be used for several power sup-
plies. Read voltage may be 2.7V, 3.3V or 5.5V and programming voltage may be 3.3V, 5V or 12V.


Flash memories are used in a wide variety of applications as illustrated Figure 10-18. All these appli-
cations allow vendors to offer several flash solutions. Using the NAND flash architecture for serial
access applications is one example. Figure 10-19 shows the diversity of the flash memory types.


                                    Focus Segment                 Application

                                           Auto                  Engine Control

                                            PC                       BIOS

                                           HDD                    Disc Control

                                        Wireless                  Analog/SSM

                                      Networking                  Hub Control

                                 Source: TI/ICE, "Memory 1997"                  22596



                                 Figure 10-18. Flash Target Segments




INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                                10-11
Flash Memory Technology




                        Core Architecture               NOR, NAND, DiNOR, AND
                        Cell Architecture               1 Transistor, Split Gate, Others
                        Storage                         1 Level, Multi-Level Cell (MLC)
                        Voltage (Read/Program)          5V/12V, 5V/5V, 3V/5V, 3V/3V, 2.7V/2.7V,
                                                        2.2V/2.2V, Smart Voltage
                        Configurations                  Random Access, Serial Access, Others
                        Applications                    Audio, PC, Wireless
                      Source: ICE, "Memory 1997"                                            22473



                                                Figure 10-19. Flash Diversity



RELIABILITY CONCERNS


There are three primary reliability concerns of a flash memory IC. They are data retention, thin
oxide stress, and over or under erasing/programming.


Regarding erase/program, flash ICs that use hot electron injection for trapping electrons in the
floating gate are programmed (data equal to 0) by capturing electrons in the floating gate, as with
an EPROM.


Flash ICs that use Folwer-Nordheim tunneling for trapping electrons in the floating gate will be
programmed (data equal to 0) by removing the electrons from the floating gate, as with an
EEPROM. The reliability concern is to either over program or over erase as shown in Figure 10-20.

                               12V                                                 0V


                   0V                        0V                        12V                      F

                        N+                 N+                                N+            N+




                      VT SHIFT HIGH                                          VT SHIFT LOW
               • FN tunneling for program                         • Hot electron injection to program
               • Low program/erase current                        • Lower program disturb
               • Over program problem                             • Over erase problem
               • Slow program time                                • Fast program time

                Source: Motorola/ICE, "Memory 1997"                                                 20841



                 Figure 10-20. Erased Threshold Voltage Shift for Flash Memory Cell




10-12                                                          INTEGRATED CIRCUIT ENGINEERING CORPORATION
                                                                                          Flash Memory Technology




PCMCIA


Magnetic memory storage and flash memory devices will co-exist. Magnetic memory will con-
tinue to dominate in ultra-high capacity, low cost/Mbyte applications where power, weight/size,
and mechanical ruggedness are not a consideration. Flash-based mass storage will become per-
vasive in small, low power, portable electronic platforms, providing low power, small size, and
unparalleled ruggedness/reliability and offering lowest entry cost of any mass storage. PCMCIA
(Personal Computer Memory Card International Association) cards were developed for this flash
mass storage application.


Hitachi proposed a 75Mbyte ATA PC Card using a mostly good memory (MGM) production tech-
nique. The chip must have a minimum of 98 percent of its memory cell sectors free of defect and
have all logic circuits 100 percent functional. Figure 10-21 illustrates an ATA Card using the MGM
technology.


                                                                                       512Byte Sector   Aux Byte


                                                                      Address Decode
                                                                                       512Byte Sector   Aux Byte
                                                                                       512Byte Sector   Aux Byte
                                                  µC +
            µC             Logic                                                       512Byte Sector   Aux Byte
                                                  Logic
                                                                                       512Byte Sector   Aux Byte
                                                                                       512Byte Sector   Aux Byte
                                            Flash       Flash
          Flash            Flash                                                           Data Register
                                          with MGM    with MGM
                                                                                        MGM Memory
                                            Flash       Flash
          Flash            Flash
                                          with MGM    with MGM
                                                                                         Good Sector
                                            Flash       Flash                            Bad Sector
          Flash            Flash
                                          with MGM    with MGM


           First Generation                 Second Generation
  Source: Hitachi/ICE, "Memory 1997"                                                                           22597



                                       Figure 10-21. ATA Card Evolution



SMALL FLASH-MEMORY MODULES


Small flash-memory modules were developed for applications where PCMCIA storage cards will
not physically fit. The main applications are for equipment needing small-size storage such as
PDAs, cameras, and digital audio recorders.


Three developments—CompactFlash, Miniature Card and Solid State Floppy Disk Card
(SSFDC)—are similar in size but employ substantially different electrical interface schemes.
Figure 10-22 presents the three miniature flash card solutions.



INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                                         10-13
Flash Memory Technology




                                       CompactFlash        Miniature Card             SSFDC

            Original Developers           SanDisk             Intel/AMD              Toshiba

            Industry Alliance          CampactFlash        Miniature Card         SSFDC Forum
                                        Association      Implementers Forum

            Module Dimensions          43 x 36 x 3.3mm     38 x 33 x 3.5mm       45 x 37 x 0.76mm

            Memory Type                  NOR Flash       NOR Flash, DRAM,          NAND Flash
                                                         SRAM, OTP, ROM

            Capacity                    2 to 15Mbytes        2, 4Mbytes             2, 4Mbytes

            Connector Type              50-Pin subset    40-Pad Elastomeric       68-Pin PCMCIA
                                         of PCMCIA                                 With Adapter

            Number of Contacts          Circular Pins    Flat-Edge Contacts    Flat-Surface Contacts

            Software Interface              ATA              FTL (Flash            Host-Based
                                                          Translation Layer)        Controller

            Built-In Controller?            Yes                  No                     No
          Source: ICE, "Memory 1997"                                                              22598



                          Figure 10-22. Standards for Small Flash-Memory Modules


CompactFlash


CompactFlash was developed by SanDisk Corporation, Sunnyvale, California, in 1994. The
CompactFlash Association (CFA) was established in October, 1995, to promote and encourage the
worldwide adoption of CompactFash technology as an open industry standard. More than 40
companies have joined the CFA.


The CompactFlash design incorporates the ATA (AT-Attachment) interface standard, that uses the
same electrical signals as PCMCIA/ATA flash cards. The first product that employed
CompactFlash technology was IBM’s Palm Top PC110, which was introduced in September, 1995.


Miniature Card


The Miniature Card, originally developed by Intel, is supported by the Miniature Card
Implementers Forum (MCIF). The Miniature Card incorporates a linear-addressed format like
PCMCIA flash cards. This card needs host-based software to be read. This software is called Flash
Translation Layer (FTL) and was developed by M Systems. Miniature Cards are cheaper than
CompactFlash cards but need that additional software. Figure 10-23 shows the ATA configuration
versus the linear configuration. Intel developed its Miniature Card for high-volume consumer
applications and will not support CompactFlash.




10-14                                                    INTEGRATED CIRCUIT ENGINEERING CORPORATION
                                                                                       Flash Memory Technology




         ATA Flash Cards
                                                                                  Card
          System
                                                                         Intelligent
            Host                               ATA                                         Flash
                                                                         Controller
            CPU




         Linear Non-ATA Flash Cards
                                                                                  Card
                    System

                      Host         Flash File                                Flash Memory
                      CPU       System Software



        Source: ICE, "Memory 1997"                                                                 20807



                                     Figure 10-23. ATA Versus Linear Flash Card



Solid State Floppy Disk Card (SSFDC)


Toshiba’s Solid State Floppy Disk Card is based on its flash NAND cell technology. This card was
announced in late 1995. With its small die size, the NAND technology is more cost effective. Like
the CompactCard this card includes an adapter to be compatible with the PCMCIA Type II cards.
An SSFDC Forum was held in April 1996 in Japan to agree on an industry standard for a super-
small data storage medium. More than 40 companies, including Samsung Electronics, have joined
the SSFDC Forum.


The SSFDC is the size of a credit card, and is much thinner than any of the other small-form factor
memory cards. Used with an ATA PC card adapter, SSFDC can be used as a standard PC card.




INTEGRATED CIRCUIT ENGINEERING CORPORATION                                                                 10-15
Flash Memory Technology




10-16                     INTEGRATED CIRCUIT ENGINEERING CORPORATION

				
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