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					                Programmable Logic Module
             The architecture of programmable logic devices



                              Krzysztof Murawski PhD Ing.
                                           k.murawski@ita.wat.edu.pl




Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   1
                                             Agenda
        Introduction to PLD?
        PAL & PLA
        SPLDs
        GAL & CPLD
        EPLD & FPGA
        PLD Programming
        Key Terms
Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   2
                     Introduction to PLD?
One of the most important developments in digital electronics
has been the introduction of programmable logic
devices (PLDs) – in the mid 1970s. Earlier digital
circuits were constructed in various scales of integrated circuit
logic, such as SSI and MSI and other. These devices contained
logic gates and more complicated digital circuits. The
functions of device were determined at the time of
manufacture and could not be changed.

Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   3
                     Introduction to PLD?
The idea was to construct combinational logic circuits that
were programmable. However, contrary to microprocessors,
which can run a program but posses a fixed hardware, the
programmability of PLDs was intended at the hardware level.
A PLD is supplied to the user with no
logic function programmed in at all.
In other words, a PLD is a general purpose chip whose
hardware can be reconfigured to meat particular
specifications. It is up to the designer to make the PLD
perform in whatever way a design requires; only those
functions required by the design need be programmed.

Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   4
                       Introduction to PLD?
Since several functions can usually be combined in the design and
programmed onto a single chip. Also, if a design needs to be
changed, a PLD can be reprogrammed with the new
design information, often without removing
it from the circuit (ISP).




  Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   5
                     Introduction to PLD?
PLD is a generic term. There is a wide variety of PLD types,
including:
   PAL (Programmable Array Logic) - 1970, only logic gates
   PLA (Programmable Logic Array)              no flip-flops,
    PALCE (PAL CMOS Electrically erasable/programmable),
    GAL (Generic Array Logic) - 1980,
    EPLD (Erasable PLD),
    CPLD (Complex PLD),
    FPGA (Field-Programmable Gate Array) - 1980,
    others.

Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   6
                      Introduction to PLD?




PLD       –   Programmable Logic Device
SPLD      –   Small/Simple Programmable Logic Device
CPLD      –   Complex Programmable Logic Device
FPGA      –   Field Programmable Gate Array
 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   7
                                      PAL & PLA
The first PLDs were called PAL or PLA, depending on the
programming scheme. They used only logic gates, thus allowing
only the implementation of combinational circuits. To solve this
problem, registered PLDs were launched soon after, which
included one flip-flop at each output of the circuit. With them,
simple sequential functions could then be implemented as well.




 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   8
                                      PAL & PLA
In the beginning of the 1980s, additional logic circuitry was
added to each PLD output. The new output cell, called
macrocell, contained (besides the flip-flop) logic
gates and multiplexers. Moreover, the cell itself was
programmable, allowing several modes of operation. It provided
also a „return” (feedback) signal from the output of the circuit to
the programmable array, which gave the PLD greater flexibility.
This new PLD structure was called generic PAL (GAL).


 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   9
                            PAL Architecture
                              Inputs

                                                                       Outputs




                               programmable
                                interconnects




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                            PLA Architecture
                           Inputs

                                                                       Programmable OR




                     programmable
                                                                                         programmable
                     interconnects
                                                                                         interconnects




                Programmable AND
                                                                                                Outputs


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                                               SPLDs
                                            All chips: PAL, PLA, registered PLD,
                                            and GAL or PALCE are now referred to
                                            as SPLDs (Simple PLDs).


The GAL and PALCE device is the only still produced in a
standalone package. All PLDs (simple or complex) are
nonvolatile. They can be OTP (One-Time Programmable), in
which case fuses or antifuses are used, or can be
reprogrammable, with EEPROM or Flash memory.
 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT        12
                                       GAL & CPLD
                                             GAL devices were fabricated on the same
              - 15
       22
          V10
                              8B
                                             chip like typical PLD, but using a more
   G AL                   20V
                        L
                     GA
            8C
                                        5L
                                             sophisticated              routing   scheme,   more
        6LV
    GA
      L1                            8-1
                                 6V
                              L1
                           GA                advanced silicon technology, and several
                                             additional features (like JTAG support and
interface to several logic standards: 3V3, 5V). This approach
became known as CPLD (Complex PLD). The output cell of
GAL devices, called macrocell, contained besides the
flip-flop, logic gates and a few multiplexers.
 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT                        13
                                  GAL & CPLD
                     In the GAL devices the EEPROM
                     memory was employed instead of PROM
                    or EPROM. An electronic signature for
                    identification was also included. At each
                    output there is a macrocell (after the OR
                    gate), which contains, besides the flip-flop,
logic gates and multiplexers. A feedback signal from the
Macrocell to the programmable array can also be observed.
Current GAL devices use CMOS technology, 3.3 V supply,
EEPROM or Flash technology, and maximum frequency around
250 MHz.
 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   14
         GAL architecture (GAL16V8)
1 CLK


                                                                            Output           19
                                                                           Macrocell


2



                                                                            Output
                                                                                          18
                                                                           Macrocell


3



                                                                            Output           17
                                                                           Macrocell


4
                                                                                       /OE 11

    Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT                15
      GAL16V8 – output macrocell
                                                  M                    M
                                                  U                    U
                                                  X                    X


                                                                       M
                                                                       U              I/O
                                                                       X
                                                          D    Q

                                              XOR
                                                            C Q




                                                   M
                                                   U
                                                   X


                                                                           Input or /OE


Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT                        16
GAL16V8 – combinatorial output
                                                  M                    M
                                                  U                    U
                                                  X                    X


                                                                       M
                                                                       U              I/O
                                                                       X
                                                          D    Q

                                              XOR
                                                            C Q




                                                   M
                                                   U
                                                   X


                                                                           Input or /OE


Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT                        17
      GAL16V8 – registered output
                                                  M                    M
                                                  U                    U
                                                  X                    X


                                                                       M
                                                                       U              I/O
                                                                       X
                                                          D    Q

                                              XOR
                                                            C Q




                                                   M
                                                   U
                                                   X


                                                                           Input or /OE


Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT                        18
    GAL22V10 – output macrocell
   CLK




                                                                       M
                                                                       U
                                                                       X   I/O
                                                          D    Q


                                                            C Q




                                                  M
                                                  U
                                                  X

Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT             19
GAL22V10 – combinatorial output
   CLK




                                                                       M
                                                                       U
                                                                       X   I/O
                                                          D    Q


                                                            C Q




                                                  M
                                                  U
                                                  X

Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT             20
    GAL22V10 – registered output
   CLK




                                                                       M
                                                                       U
                                                                       X   I/O
                                                          D    Q


                                                            C Q




                                                  M
                                                  U
                                                  X

Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT             21
         PLD Symbol Understanding
The part number of a PAL device gives the designer
information about the number of inputs and outputs and their
configurations, as follows:
                     Number of inputs
                     H Active HIGH
                     L Active LOW
         Output type P Programmable polarity
                     R Registered (D flip-flop)
                     X XOR registered
                     C Complementary (both HIGH and LOW)
                     V Versalite
                     Number of (registered) outputs
PAL 22 R 8
Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   22
        PLD ver. CPLD Architecture
                                                           S
                                                           W           PLD 1
                                                           I
                                                           T
                                                           C
                                                           H           PLD 2
                          I/O
                                                            M
                                                            A
                                                            T
                                                            R
                                                            I          PLD n
                                                            X
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An example of CPLD Architecture




EPM7096
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       MAX 7000 Device Macrocell




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MAX 7000E/S Device Macrocell




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                                EPLD & FPGA
                         Field Programmable Gate Array (FPGA)
                         devices were introduced by Xilinx in the
                         mid 1980s. FPGAs devices are mostly
                         volatile, for they make use of SRAM to
                         store the connections, in which case a
                         configuration ROM is necessary to load
                         the interconnects at power up. The
basic architecture of an FPGA consists of
a     matrix       of     CLBs       (Configurable Logic
Blocks), interconnected by an array of switch matrices. The
internal architecture of a CLB is different from that of a PLD.

 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   27
                                EPLD & FPGA
                         Instead      of     implementing     SOP
                         expressions with AND gates followed by
                         OR gates (like in SPLDs), its operation is
                         normally based on a LUT (lookup table).
                         Moreover, in an FPGA the number of
                         flip-flops is much more abundant than in
a CPLD, thus allowing the construction of more complicated
circuits. Besides JTAG support and interface to diverse logic
levels, other additional features are also included in FPGA chips,
like SRAM memory, clock multiplication (PLL), PCI interface,
etc. Some chips also include dedicated blocks, like multipliers
and DSPs.
 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   28
                          FPGA architecture
        CLB                                        CLB                          CLB
                               Switch                                  Switch
                               Matrix                                  Matrix

        CLB                                        CLB                          CLB
                               Switch                                  Switch
                               Matrix                                  Matrix

        CLB                                        CLB                          CLB
Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT                  29
An example of FPGA Architecture

                                    Cyclone EP1C12
                             LAB                        LAB            LAB
    (Phase Locked Loops)
                                               Dual ports
                                                memory

                                                         4Kb
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                 Cyclone LAB Structure




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        LAB – Wide Control Signals




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    Cyclone CLB (LE) architecture




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          PLD Architecture Evolution




  Global                     Programmable                          Enhanced    FastTrack
Interconect                   Interconect                           (PIA)     Interconect
                              Array (PIA)

 Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT                 34
                                    Next Subject


                Programmable Logic Module
                                              Programming



                              Krzysztof Murawski PhD Ing.
                                           k.murawski@ita.wat.edu.pl




Institute of Teleinformatics and Automatics, Cybernetics Faculty MUT   35

				
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Description: PLD (programmable logic device): PLD is used as a common integrated circuit manufacturing, and his logic functions programmed by the user of the device to get. PLD of integration in general high enough to meet the design needs of digital systems in general. This can be programmed by the designers themselves and put a digital system, "integrated" in a PLD, while chip manufacturers do not have to please the design and production of a special integrated circuit chip.