Low-Temperature_ Hermetic_ High-Yield Wafer-Level Packaging Technology

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					                         Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology




Low-Temperature, Hermetic, High-Yield Wafer-Level
Packaging Technology

Patty P. Chang-Chien, Kelly J. Tornquist, Matt Y. Nishimoto, Craig B.
Geiger, Ling-Shine Jane Lee, Minhdao D. Truong, Jansen J. Uyeda,
Lawrence J. Lembo, Michael E. Barsky, Richard Lai, and Aaron K. Oki
Northrop Grumman Space Technology

    Northrop Grumman Space Technology has developed a patented low-
    temperature, hermetically sealed (hermetic), high-yield wafer-level packaging
    (WLP) technology that is compatible with standard monolithic microwave
    integrated circuit (MMIC) fabrication processes. These wafer-level packages
    are fabricated using batch processes. They are MMIC-compatible, hermetic,
    and mechanically robust. Northrop Grumman’s WLP technology is an enabling
    process for realizing lightweight, multifunctional modules for space and
    Department of Defense applications. It is the building block for integrating
    MMICs fabricated using various technologies with dissimilar substrates, thus
    achieving maximum design flexibility and optimizing circuit performance. WLP
    eliminates costly labor-intensive, higher-level module assemblies and offers
    significant weight and size savings at both the subsystem and system levels.
    Northrop Grumman’s WLP technology is the first hermetic packaging process
    that is compatible with high-performance, high-frequency, radio-frequency
    Group III and Group V compound semiconductor MMICs at the circuit level
    and can be produced in an MMIC chip production environment.


Introduction
The hermetic electronic module is one of the most expensive components in many
Department of Defense (DoD) systems. Hermetic wafer-level packaging (WLP) can
save DoD programs hundreds of millions of dollars by minimizing costs associated with
hermeticity requirements. Hermetic wafer-level packages can also reduce the unit cost of
commercial, high-performance, high-frequency monolithic microwave integrated circuit
(MMIC) chips, especially for units that operate in harsh environments.
Typically, not all parts of the module require hermetic packaging; however, hermeticity is
required for the more sensitive, high-performance microelectronics that reside within the
module. If the sensitive microelectronic components can be hermetically sealed at the
wafer level using batch fabrication techniques in their fabrication stage, it will relax the
hermeticity requirement at the submodule or module level drastically, as well as eliminate
all costs associated with hermetic sealing at the higher levels.
Northrop Grumman Space Technology has developed a patented low-temperature WLP
technology, that, to our knowledge, is the first MMIC-compatible hermetic packaging
process suitable for batch fabrication of high-performance, high-frequency, radio-
frequency (RF) Group III and Group V (III-V) MMICs. That combination will offer signifi-
cant cost savings for the military and will revolutionize the RF front-end performance of
MMIC modules, especially at frequencies beyond 44 GHz.


                       Technology Review Journal • Spring/Summer 2006                          57
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



 How to Select the Best Packaging Technology for MMICs
 Many WLP techniques have recently been reported in the literature [1–9], especially in
 the microelectromechanical systems (MEMS) community. Most of these wafer-level
 bonding techniques are being implemented in silicon-based material systems. Very few
 are suitable for III-V RF MMICs because of high-temperature processes that cannot be
 tolerated in III-V semiconductor systems. Most commonly implemented WLP techniques
 are briefly described in a sidebar, “Common Wafer-Level Packaging Techniques”
 (pages 79–80).
 All WLP approaches reported to date can be grouped in two categories, sealing an
 existing cavity and encapsulating a device, as illustrated in Figure 1:
 • Sealing an existing preformed cavity in the substrate or a cavity formed in the
      additive film layers (Figure 1a). The cavity is sealed by a cover wafer or cap.
 • Encapsulating an area with a shell-like structure (Figure 1b). The “gap” in the
      shell structure, shown at the right in Figure 1b, is sealed by film deposited during
      subsequent processing steps.
 The Northrop Grumman WLP technology uses a low-temperature wafer-bonding tech-
 nique to seal a cavity, as discussed in greater detail in the section “Northrop Grumman’s
 Low-Temperature Packaging Process” (page 82). As a prelude to that description, the
 following subsections outline four of the most important factors to be considered in
 packaging high-performance MMICs: process/device compatibility, hermeticity, reliability,
 and cost. Each factor should be carefully considered in selecting a particular packaging
 method.
 Process/Device Compatibility. MMIC/module thermal requirements, such as the maximum
 allowed temperature and exposure duration, should be considered during the package
 assembly (bonding) process. The thermal budget ultimately limits the assembly methods
 selected for a particular application. Wafer-bonding temperature, temperature-ramping
 profile, and exposure duration are all critical fabrication parameters.
 Any of those factors can directly compromise both the performance and reliability of a
 temperature-sensitive MMIC component. For example, many high-performance III-V-based
 circuits have molecular beam epitaxy (MBE) grown materials that are sensitive to process
 temperatures. Undesirably high temperatures or prolonged elevated temperatures will
 induce thermal diffusion of thin, multistacked layers into one another. That interdiffusion
 of the grown MBE layers directly affects device performance and reliability.
 The wafer-bonding temperature also dictates the amount of thermally induced stress
 between the wafer bonds and any interface between two dissimilar materials, such as
 semiconductor to metal or dielectric films to metal. It is critical to maintain low bonding
 temperatures to eliminate or minimize these undesirable thermally induced effects.
 Hermeticity. Hermeticity is critical for effective packaging of high-performance MMIC
 and MEMS devices. Hermetically sealed cavities offer a stable, controlled operating
 environment for the packaged parts by protecting them from moisture and undesirable
 organic materials. Moisture penetration is a common failure mode for packages immersed
 in liquid or high-humidity environments. Moisture inside a package can cause condensa-
 tion on the active area of the device, leading to corrosion of the structure and/or degraded
 performance.




58                       Technology Review Journal • Spring/Summer 2006
                       Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology




Common Wafer-Level Packaging Techniques
The most commonly implemented wafer-level bonding processes are briefly described
below. The shortcomings of each in supporting radio frequency (RF) monolithic
microwave integrated circuit (MMIC) production are noted, demonstrating the need for
more MMIC-friendly hermetic packaging processes.

Silicon Fusion Bonding
Direct silicon-to-silicon bonding is achieved by placing the surfaces of two flat silicon
wafers together. The two wafers are bonded by weak van der Waals forces, and the
bond is established by high-temperature annealing typically exceeding 1000°C for an
extended period. Fusion bonding is thermal stress free because the thermal expansion
coefficients between the two wafers are identical and the quality of the bond is excel-
lent. However, the requirement for high-temperature annealing and extremely flat
surfaces forbids the use of fusion bonding on substrates with active components,
such as III-V RF MMICs.

Anodic Bonding
Anodic bonding, also known as electrostatic bonding, is one of the most commonly
used techniques for wafer bonding in silicon-based systems. The bonding occurs
between a sodium-rich glass wafer and a silicon wafer or a substrate with polysilicon
films. The sodium ions in the glass are absolutely essential for anodic bonding. The
wafers are typically heated between 180°C and 500°C to mobilize the sodium ions in
the glass.
When a voltage—typically between 200 and 1000 V—is applied between the two
wafers, sodium ions drift away from the interface, thereby generating a strong electrical
field between the two bonded surfaces. The resulting bond is extremely strong and can
be used to create hermetic cavities. However, very flat bonding interfaces and proper
device passivation and shielding are prerequisites for high yields and to prevent the
devices from being damaged by the high electrical field during the bonding process.
Those requirements add unacceptable cost to RF MMICs by adding complexity to
device design and processing.

Eutectic Alloy Bonding
A eutectic alloy bond is established when a metal diffuses into the substrate or another
metal and forms a eutectic alloy at the interface. Despite the desirable low bonding
temperatures of many eutectic systems, eutectic alloy bonding techniques remain
unpopular because they impede uniform, reliable bonding over large areas. A frequent
result is cracking or stress in the eutectic film, caused by a mismatch in the thermal
expansion coefficients between the eutectic materials. Those undesirable characteris-
tics directly affect RF MMIC performance and package reliability because of high film
stress and rough film surface due to eutectic alloys. Hence, eutectic alloy bonding is
not suitable for packaging RF MMICs.




                      Technology Review Journal • Spring/Summer 2006                        59
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology




  Adhesive Bonding
  Wafer bonding can also be achieved by “gluing” the wafers together using an interme-
  diate organic layer. Materials such as photoresist, polyimide, ultraviolet curable resins,
  various waxes, and polymers have all been used to create organic bonds between
  wafers. The greatest advantage of adhesive bonding is a very low bonding tempera-
  ture—less than 100°C. However, poor bonding strength, high vapor pressure, and
  polymer aging make hermetic sealing by adhesive bonding impossible. It is therefore
  a poor candidate for packaging III-V electronics with hermetic requirements.

  Solder Bonding
  Solder bonding offers the advantage of a low bonding temperature. Whatever the
  soldering system, solder bonding is highly tolerant of topology variations and can be
  performed at MMIC-compatible temperatures. Topology tolerance allows this tech-
  nique to consistently produce extremely high bonding yields. However, the low
  bonding temperature translates to a low solder-reflow temperature, making solder-
  bonded MMIC packages thermally incompatible with high-temperature Department of
  Defense environments in general and space applications in particular. The low-reflow
  temperature is also problematic for postmodule or higher-level assemblies that typically
  require an assembly temperature higher than solder-reflow temperatures.




 The ability to hermetically seal cavities is critical in bonding/packaging methods and
 materials. For example, materials such as organic polymers or adhesives may be unsuitable
 for packaging high-performance MMIC devices. They are known to outgas, jeopardizing
 the hermeticity of the cavity.
 In addition to providing moisture protection, hermeticity contributes to device perfor-
 mance as well as reliability enhancement by controlling the package environment in
 specific or optimal conditions. For example, MMICs perform best in an oxygen-free
 (nitrogen) environment. Specific MEMS devices, such as resonators and pressure
 sensors, require a vacuum or a specific level of pressure in order to function properly.
 Package Reliability. Packaged devices are only as reliable as the packages in which they
 reside. The seal or bond should be both chemically and physically stable over the entire
 operating lifetime of the packaged device. Chemically unstable bonds, which deteriorate
 over time, can destroy a hermetically sealed cavity and cause device performance to
 degrade.
 Outgassing and hardening of organic adhesives are prime examples of chemical instability
 as they jeopardize the physical integrity of the package and thus the performance stability
 of the packaged device. One of the critical issues governing the reliability of packages is
 the mismatch between the mechanical properties of the packaging and device materials.
 Device encapsulation between two dissimilar materials, as in the case of wafer bonding,
 can result in large residual stresses and pose severe reliability problems such as cracking
 and deformation.




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                        Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



a. Wafer-level packaging using a cover wafer (cap)
           Cap                             Cap                              Cap
                                                                           Cavity
                                          Cavity

          Cavity

         Substrate                       Substrate                       Substrate


b. Wafer-level packaging by encapsulation
                                        Microshell

                                           Cavity



                                          Substrate


Figure 1. Two basic wafer-level packaging processes

Because MMIC parts are delicate, extra precaution should be taken when designing the
packages and performing the packaging processes. If a substantial amount of residual
stress is stored during the bonding/assembling procedures, it will be released over time
and can result in cracks at concentrated stress areas. Stress redistribution within the
package can alter the mechanical properties of the enclosed circuits, and introduce
undesirable noise and drift. The combination of lower packaging temperature and proper
packaging design is the most effective solution to reduce residual stress and improve the
physical stability of these packages.
Cost. Critical in determining the best packaging and bonding methods for a particular
application, cost is itself heavily influenced by a range of parameters. These include
device and package yield, reliability, process feasibility and reproducibility, and the
complexity of the manufacturing techniques used to fabricate the parts and packages.
At the MMIC/device level, WLP processes can actually increase the cost by adding one
or more steps to the device-level batch processing. Significant cost savings are realized,
however, at the subsystem or system level. WLP brings the subsystem and system
assembly times down, achieving higher test yields more quickly than when hermetic
sealing is delayed until the assembly of subsystems and systems.
Ideal Process Features. Considering the foregoing factors, the ideal WLP process should
feature
• Low temperature for MMIC compatibility and package stability
• Hermetic sealing for device reliability and system assembly/test cost reduction
• Mechanical and chemical robustness for reliability
• Minimal addition of packaging steps for cost savings and yield enhancement
• High-yield batch fabrication for cost conservation




                       Technology Review Journal • Spring/Summer 2006                        61
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



 Northrop Grumman’s Low-Temperature Packaging Process
 The WLP process developed at Northrop Grumman is a batch fabrication as well as a
 stand-alone process that is applied after the standard MMIC front-side processes. The
 front-side MMIC processes produce the basic MMIC device layers, whereas the back-
 side processes produce the vias necessary to complete the MMIC fabrication. The WLP
 process does not affect either the front-side or the back-side processes, so the resulting
 MMIC performance is not compromised.
 Northrop Grumman’s low-temperature packaging process combines the benefits of low-
 temperature solder bonding and thermodynamically stable eutectic alloy bonding. The
 novel process is highly topology tolerant, producing superior bonding and interconnec-
 tion yields while keeping the processing temperature low. It enables multiple-wafer stack
 integration and is compatible with standard assembly processes such as solder bumping.
 The bonding temperature does not exceed 180ºC, resulting in very low built-in stress,
 thereby making it suitable for packaging high-performance RF MMICs and for multiwafer
 heterogeneous integration.
 Our baseline WLP is a two-wafer process that consists of a substrate and a cover wafer,
 as shown in Figure 2. Figure 2a shows the simplified flow of the WLP processes. Figure 2b
 shows individual WLP chips after dicing; their compact size is illustrated against a U.S.
 dime. The substrate and cover halves are first processed separately using standard MMIC
 front-side batch fabrication processes. Matching metallic sealing rings are deposited on
 the two wafer halves. A low-temperature wafer-level bonding process then fuses the
 sealing rings of the two wafers together. The cavities are created between the two wafer
 halves, encapsulating the front side of the circuits within the cavities at the wafer level.
 The bonded wafer pair is then processed to form the vias using standard MMIC back-side
 batch fabrication processes.
 Three types of vias are required for WLP devices: dc bias, RF signal, and ground. All three
 are formed in the thinned substrate by the same MMIC back-side fabrication processes
 Northrop Grumman uses for MMIC production. Vertical rather than lateral RF via topology
 minimizes parasitic via losses at high frequencies. Performance of low-loss RF vias and
 package evaluation are discussed later in greater detail in the section entitled “Low-Loss
 Radio-Frequency Vias for High-Frequency Applications” (page 85).


 Demonstrated Hermeticity and Mechanical/Thermal
 Robustness
 WLP devices are processed using batch fabrication at the wafer level. They can be diced
 into individual chips, using conventional techniques to saw through the wafer stack.
 Figure 3a is a photograph of a bonded WLP wafer. Individually diced WLP chips
 (Figure 3b) are 2.5 × 2.5 mm in chip dimension, and only 0.6 mm thick. A cross-section
 illustration of the WLP cavity is shown in Figure 3c, and the corresponding SEM micro-
 graph is shown in Figure 3d. The cavity formed between the two wafers is only about
 0.008 mm. In this configuration, the packaged MMIC circuits, shown upside down inside
 the cavity, are tested by accessing the probe pads on the back side of the package.
 The packages were subjected to helium leak tests to evaluate their hermeticity. Hermeticity
 of vias on the individual wafers was confirmed by an open-face helium test prior to wafer
 bonding/assembly. In order to meet hermeticity requirement specified by the open-face


62                       Technology Review Journal • Spring/Summer 2006
                         Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



a. Simplified WLP process flow
 Substrate Wafer                                                              Cover Wafer
    Standard                                                                  Standard
    Front-Side                                                                Front-Side
    MMIC                                                                      MMIC
    Processes                                                                 Processes
                                                        Flip
                                                       Wafer
   WLP Sealing                                                               WLP Sealing
   Ring A                                                                    Ring B




                            Wafer
                            Bonding



                      Standard
                      Back-Side
                      MMIC Processes



                           Sawing/
                           Dicing

 b. Individual WLP chips




  Note: WLP = wafer-level packaging/package
      MMIC = monolithic microwave integrated circuit

Figure 2. Wafer-level-packaging process flow


helium test in Military Standard 883F, method 1014.9, condition A4 (flexible method), the
leak rate needs to be less than 1 × 10–8 atm-cc/s. The tested wafers resulted in a leak rate
of less than 2.2 × 10–9 atm-cc/s, which approaches the detection limit of NGST’s helium
test setup, confirming that the via structures and the individual wafers are hermetic.
Helium leak tests were also performed on diced packages. The packages are grouped
to speed up the testing, and tests were conducted with group size varying from 1 to 30
packages. According to Military Standard 883, method 1014.9, condition A2 (flexible


                       Technology Review Journal • Spring/Summer 2006                          63
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



                                   a. Bonded WLP wafer




 b. Individually diced WLP chips                     c. WLP cavity cross section
                                                                RF         Probe
 0.6                                                            Via        Pad     Bonding
 mm          2.5 mm                                                                Ring
                                                                                   (wafer 1)
                                       Wafer       Wafer 1 (thin
                                                                 ne                 Bonding
                                                                   d)
                                       Bonding                                      Ring
                                                                                    (wafer 2)
                                                                                   Circuit
                                 2.5                                               (low-noise
                                 mm                                                amplifier)
                                                           Wafer 2



                                                 d. SEM cross section of cavity




                      Wafer 1,
                      Thinned


                      Wafer 2


                             Bonding                                                  RF
                             Ring                                                     Via



                      Cavity
                      Height,                                                  Circuit
                      0.008 mm                                                 (low-noise
                                                                               amplifier)



  Note: WLP = wafer-level packaging/package
         RF = radio frequency
        SEM = scanning electron microscope

 Figure 3. Fabricated wafer-level-packaged wafer and chips with 0.008-mm cavity
 height



64                        Technology Review Journal • Spring/Summer 2006
                        Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



method), the packages are considered hermetic if the helium leak rates are less than
5 × 10–8 atm-cc/s. The various package groups all resulted in leak rates of less than
the requirement, ranging from 2.2 × 10–9 atm-cc/s for small groups (2 to 5 chips) to
1.5 × 108 atm-cc/s for large groups (30 chips).
Because of the extremely small cavity internal volume, which stresses the helium test’s
sensitivity limit, radioactive gas tests using Krypton-85 gas were performed by a commer-
cial vendor to further confirm hermeticity of these wafer-level packages. The vendor
verified that these parts meet the hermeticity requirement as stated in Military Standard
883, method 1014.9, condition B (radioactive gas test). For completeness, gross leak tests
were also performed using a dye penetrant; no gross leaks were detected from these
packages.
The packages were also subjected to pyroshock and vibration sine tests that comply
with Military Standard 883, method 2002.4, condition B, and method 2007.3, respectively.
Functionality and performance of the packaged devices were identical after each test,
confirming that the packages were mechanically and electrically robust and suitable for
use in harsh environments. In addition, the packages were thermally cycled from –55°C to
125°C for 50 cycles per Military Standard 883, method 1010.8, condition B. No signs of
device degradation were detected, confirming that these packages are thermally stable.


Low-Loss Radio-Frequency Vias for High-Frequency
Applications
Hermetic packaging should not compromise circuit performance by routing signals in
and out of the packages. We used a test structure to evaluate the RF via performance of
packaged devices. The test structure, shown in Figure 4a, consists of two RF via transi-
tions and a through line inside the cavity. Measured data show that transitional loss per
via is less than 0.1 dB up to 25 GHz, about 0.25 dB at 35 GHz, and 0.35 dB at 50 GHz.
The measured performance correlates well with simulated results based on finite-element
electromagnetic software. Imposing a simultaneous two-port matching condition on the
data reduces loss to about 0.15 dB per transition via at 50 GHz.
These RF vias provide low loss transitions that are suitable for high-frequency MMIC
circuits. The ability to provide a low-loss RF signal into and out of the packaged cavity
allows for dramatic performance enhancement relative to existing packaging techniques—
a benefit of WLP technology.


Monolithic Microwave Integrated Circuit Compatibility
MMIC compatibility is an important feature of our WLP technology. To demonstrate that
feature, we used WLP techniques to package a low-noise amplifier (LNA) designed to
have an approximately 10-dB gain between 30 and 40 GHz with our 0.1-mm GaAs high-
electron-mobility transistor (HEMT) technology (Figure 5a). The additional processing
had no perceptible effect on circuit performance. A nearly 100% wafer-bonding yield and
an average RF functional yield exceeding 85% were obtained from WLP wafers. Figure 5a
presents a photograph of the WLP LNA. Figure 5b presents measured data obtained from
packaged LNAs. The data confirm that the WLP processes are 100% compatible with
existing III-V semiconductor processing.



                       Technology Review Journal • Spring/Summer 2006                       65
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



   a. Through-line test structure                                                                    b. Measured data and simulated results per
                                                                                                        transition via for insertion loss
                                     RF Via Transitions
                                                                                                          0 xx   xx   xx   xx   xx   xx
                                                                                                       –0.1                               xx
                                                                                                                                               x
                                                                                                                                                       x




                                                                               Insertion Loss (dB)
                                                                                                       –0.2                                    x       x       x
                                                                                                                                                               x
                                                                                                       –0.3
                                                                                                       –0.4
                                                                                                       –0.5
                                                                                                       –0.6
                                                                                                       –0.7
                                                                                                                                     Measured Data
                                                                                                       –0.8
                                                                                                                                     Simulated Results
                                                                                                       –0.9
                                                                                                       –1.0
                                                                                                            0    5    10 15     20 25     30 35        40 45 50
                                                                                                                           Frequency (GHz)

                              Through-Line Inside Cavity
 c. Measured data and simulated results per                                                            d. Insertion loss of 0.15 dB at 50 GHz
    transition via for isolation                                                                          per RF transition
                      0                                                                                   0 x     x
                                                                                                                  x    x    x    x    x    x
                                                                                                                       x    x    x                         x
                                                                                                                                      x
                     –5                                                                                –0.1                                x   x                x
 Return Loss (dB)




                                                                                 Insertion Loss (dB)




                                                                                                       –0.2                                        x       x    /
                    –10
                                                                       x
                                                                                                       –0.3
                    –15                                    x   x   x
                                                    x                                                  –0.4
                                               x
                    –20                   x                                                            –0.5
                    –25
                                      x                                                                –0.6
                                                                                                       –0.7
                                                                                                                      Measured Data
                                 x
                    –30                                 Measured Data                                                 Simulated Results with
                                                                                                       –0.8
                    –35
                                                        Simulated Results                                             Simulated 2-Port Matching
                                                                                                       –0.9
                    –40                                                                                –1.0
                          0     5    10   15 20    25 30       35 40   45 50                                0    5    10 15     20   25   30   35 40           45 50
                                           Frequency (GHz)                                                                 Frequency (GHz)

 Figure 4. Test structure and measured data for evaluating radio-frequency via
 performance

 Because WLP uses all batch-fabrication processing techniques, it is possible to produce
 a large quantity of III-V MMICs with hermetic sealing on wafer packages. With further
 process improvement to enhance yield, combined with enhanced RF design to further
 minimize electrical via transitional losses, WLP technology offers significant potential
 cost savings and system performance enhancement.
 We also use low-temperature WLP technology to package our lateral-deflection (LD) RF
 MEMS switches. These switches are fabricated using the same 100-mm MMIC production
 facility and processes at Northrop Grumman and are 100% compatible with standard
 MMIC, as well as WLP processes. The compatibility of all three processes—MMIC,
 MEMS, and WLP—enables packaging and MMIC integration with MEMS switches. LD
 RF MEMS switches are discussed in detail in References 10 through 12. A brief introduc-
 tion to LD switches is provided in a sidebar (pages 88–91).


 Wafer-Level-Packaging Enabled Applications
 WLP is an enabling technology and a building block for heterogeneous integrated
 circuits. Different technologies, often built on different semiconductor substrates,
 offer unique MMIC capabilities that are often required simultaneously in a system.


66                                                 Technology Review Journal • Spring/Summer 2006
                                              Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



a. Diagram and photograph of WLP LNA
                                               Through              Bonding
                                                 Via                Ring                  Low-Noise
                                                                    (wafer 1)              Amplifier
                                       Wafer 1 (thinned)




Wafer
Bonding




                                           Wafer 2                Bonding
                                                   Circuit        Ring
                                            (low-noise amplifier) (wafer 2)                            Bonding
                                                                                                        Ring
b. Measured data from WLP LNA circuits
                             20


                             10
  Amplifier Gain, S21 (dB)




                              0
                                                                                   Designed
                             –10                                                   Operating
                                                                                   Range

                             –20


                             –30


                             –40
                                   0           10              20           30                  40               50
                                                               Frequency (GHz)
  Note: LNA = low-noise amplifier
       WLP = wafer-level packaging/packaged
Figure 5. Low-noise amplifier packaged using wafer-level processing techniques

The technologies are not always compatible with one another because different process-
ing techniques are required for fabricating different semiconductor materials. For example,
the substrate profiles for building LNAs are optimized for noise figures and are often built
using InP technologies, whereas the profiles for power amplifiers are optimized for power
efficiency and typically built with GaAs or GaN technologies. For a system that needs
both types of MMICs, WLP technology offers a unique capability to put multiple
technologies into close proximity without sacrificing either performance or reliability. To
extend this heterogeneous integration capability further, it is possible to integrate silicon-
based digital circuits with RF MMICs using the same wafer-bonding processes.
                                                                                              (Continued on page 72)


                                             Technology Review Journal • Spring/Summer 2006                       67
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology




  Packaged Lateral-Deflection Radio-Frequency
  Microelectromechanical System Switches
  Unlike most microelectromechanical systems (MEMS) switches, the motion of the
  lateral-deflection (LD) switch is parallel rather than perpendicular to the substrate.
  Because of the lateral configuration, the LD switch is inherently a single-pole, double-
  throw switch, able to replace two single-pole, single-throw switches. The basic LD
  switch is a suspended metal beam in a double-clamped configuration, as shown in
  Figure S1.

     a. Photograph of lateral-deflection switch
        RF In                RF Paths        RF Output 1                    Electrodes




      Beam Anchor                            RF Output 2          Stops           Beam
  b. Modes of switch operation               RF
                                             Output 1
                                                                                   To dc
                                                                                   Voltage 1
             Electrodes                                        Electrodes   TFR
                              Stops                 Stops
  RF In       Beam                      Beam                      Beam
              Anchor                                              Anchor
                                                                                   To dc
                              Stops                 Stops                          Voltage 2
             Electrodes                                        Electrodes   TFR


              Neutral Position               RF
              Actuated Position 1            Output 2
              Actuated Position 2
      Note: RF = radio frequency
          TFR = thin-film resistor

 Figure S1. Modes of operation of lateral-deflection radio-frequency
 microelectromechanical switch


68                         Technology Review Journal • Spring/Summer 2006
                      Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology




The switch is actuated electrostatically by applying voltages to the electrodes on
either side of the center beam. When the LD switch is actuated, the center beam flexes
laterally toward the electrode. Mechanical stops located along both sides of the center
beam prevent it from overtraveling. The radio-frequency (RF) input signal is applied
through a beam anchor, and the RF signal can be routed to either RF output 1 or RF
output 2 by applying a dc voltage to the appropriate electrode. The two RF paths are
illustrated by the arrows in Figure S1a.
LD switches are suitable for broadband operation from dc to greater than 50 GHz
because they are metal-to-metal contact switches. The LD switch offers excellent RF
performance and switching speed, as shown in Figure S2. Insertion losses of less
than 0.2 dB and 1 dB, along with isolation of greater than 45 dB and 20 dB, have been
demonstrated at 10 GHz and 50 GHz, respectively (Figure S2a). Under normal operation,
the typical switching speed of an LD switch is less than 2 µs (Figure S2b).
An LD switch can be bidirectionally powered on or off because of its unique lateral
configuration. Consequently, its switching speed can be enhanced by a push-pull
mode of operation. In that case, the switch operates like a single-pole, single-throw
switch, and voltages can be applied to toggle the switch. As shown in Figure S2b,
control voltage 1 on the desired contact side is applied before voltage 2 on the
opposite side is turned off. With such a push-pull operation, submicrosecond switch-
ing speed can be achieved and has been demonstrated.
Figures S3a and S3b present photographs of a wafer-level-packaged (WLP) LD RF
MEMS switch. Each package contains one LD MEMS switch, as shown in Figure 3b.
Three types of vias provide access to and from the switch through the thinned
substrate wafer to the back of the package (Figure S3a):
• Ground vias provide proper ground to the switch.
• Direct-current vias supply voltages necessary to actuate the switch.
• Radio-frequency vias provide signal input/output to the device.
Excellent switch yields are obtained from devices packaged using this WLP process.
A dc yield exceeding 90% and an RF yield exceeding 85% are routinely obtained from
100% device testing.
Figure S4 shows a representative set of measured data (unmatched), including the
losses from the RF vias and RF switches. The tight data grouping shows that the
fabricated devices have excellent yield and uniformity.
Hermetic packages have dramatically improved the lifetime of RF MEMS switches. To
date, more than 23 billon hot switching (RF always on) cycles have been accumulated
on packaged LD switches at Northrop Grumman. The switches are tested at 15 GHz,
with 1-ms dwell time at 50% duty cycle and tests are still ongoing.
A well-known MEMS switch failure is caused by oxidation at the RF contacts. When
the switch is under RF drive, current going through switch contacts can generate
extremely hot local spots, hence accelerating and promoting localized oxidation if the
switch is not immersed in an oxygen-free environment. Oxidation at the contact
undesirably increases the switch’s contact resistance, causing it to fail. Hermetic WLP
gives switches an oxygen-free environment, enhancing their reliability. Additional
reliability testing is under way.




                     Technology Review Journal • Spring/Summer 2006                       69
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology




a. Radio-frequency performance of lateral-deflection switch
                                            0
                                                                                  Insertion Loss
                                          –10                       –0.2 dB         (switch on)                –0.96 dB
                                                                   at 10 GHz                                   at 50 GHz
     Insertion Loss/Isolation, S21 (dB)




                                          –20

                                          –30                                                                  –21.6 dB
                                                                                     Isolation                 at 50 GHz
                                          –40                                       (switch off)


                                          –50
                                                                    –46 dB
                                          –60                      at 10 GHz


                                          –70

                                          –80
                                                0             10                20           30               40           50
                                                                                Frequency (GHz)

b. Submicrosecond switching speed of lateral-deflection switch
                                                                               100 MS/s Sample T




                                                                                               Control Voltage (V1)




                                                                                               Control Voltage (V2)


                                                                                               Radio-Frequency Signal




                                                                                              Switching Speed ~600 ns

                                                    Ch 1 50.0 V BW         Ch 2 50.0 V BW            Ch 3 20.0 mV BW

 Figure S2. Lateral-deflection switch radio-frequency performance and
 submicrosecond switching speed




70                                                           Technology Review Journal • Spring/Summer 2006
                                                    Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology




      a. Back side of completed WLP chip                                   b. Front side of WLP chip before
                                                                              wafer bonding
                       Ground Via                       dc Vias                                            dc Vias




                       Ground Via                       RF Vias        Sealing     RF Vias                 MEMS
                                                                        Ring                               Switch
                  Note: WPL = wafer-level packaging/packaged
                         RF = radio frequency
                     MEMS = microelectromechanical system

Figure S3. Photographs of wafer-level-packaged lateral-deflection radio-frequency
microelectromechanical switch



                                      0
                                                                          Insertion Loss
Insertion Loss/Isolation, S21 (dB)




                                     –10                                    (switch on)


                                     –20

                                                                            Isolation
                                     –30                                   (switch off)


                                     –40


                                     –50


                                     –60
                                           0   5   10      15       20     25     30         35       40        45     50
                                                                     Frequency (GHz)

Figure S4. Measured data from wafer-level-packaged switches, showing excellent
device yield and uniformity




                                                   Technology Review Journal • Spring/Summer 2006                      71
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



 The WLP technology introduced above offers flexibility in packaging RF MMICs fabri-
 cated on different substrates with the same packaging steps. Such flexibility allows
 minimal packaging processes to be maintained and controlled in a manufacturing environ-
 ment and further reduces unit cost associated with packaging.
 Significant system performance enhancement and cost savings are expected from such
 WLP integrated circuits. Current state-of-the-art packaging relies on a multilayer, densely
 packed ball-grid-array module that requires dual-sided assembly and automated pick-and-
 place assembly of several MMICs per module. Using WLP to bring the different circuits
 into close proximity eliminates the need for additional board material and MMIC pick-and-
 place assembly. That integration approach also lowers component count and minimizes
 unnecessary component-to-component interfaces and interconnections, such as wire
 bonds. The result is a much lower overall ohmic loss and fewer wire-induced parasitics in
 the integrated circuits—especially critical for circuits that operate at higher frequencies.
 WLP also offers significant size, weight, and assembly savings. The hermetic packages
 can eliminate many bulky and heavy packages or metal housings currently used at the
 system level to meet a hermeticity requirement. Instead of imposing the hermeticity
 requirement on the entire module, such as hermetic vias and laser welding of module
 housing, WLP hermetically seals only the parts that require environmental protection—
 namely, the electronics. That approach offers two benefits: considerable weight/size
 savings and ease of chip replacement, when necessary.
 The cost of launching a system/module for space applications is in the range of dollars
 per weight unit. That cost is usually significant, and every gram counts. A hermetic WLP
 transceiver with integrated circuits can reduce module weight by at least a hundredfold,
 compared with a transceiver packaged with ball-grid arrays.
 Individually packaged hermetic MMICs also reduce the cost of unit replacement.
 Currently, if a component inside the hermetically sealed module must be replaced, the
 entire module must be taken apart (hence breaking the hermetic seal), the part replaced,
 and the entire module reassembled to meet the hermetic requirement. Hermetically sealed
 WLP parts relax the hermeticity requirement for the entire module, because a part can be
 replaced without having to perform any hermetic testing.
 Furthermore, it is easier to perform system diagnostic tasks if the module is no longer
 seam-sealed for hermeticity. WLP technology can minimize or eliminate diagnostic and
 assembly tasks, which can add up to a significant labor and schedule bill. We are
 aggressively developing a heterogeneous integration capability, using the existing
 MMIC and WLP processes and expertise to replace conventional labor-intensive
 integration processes.


 Summary and Recommendations
 An innovative WLP technology developed and patented by Northrop Grumman combines
 the low-temperature, topology-tolerant characteristics of solder bonding with hermetic
 stable bonds of alloy bonding to produce high-yield, robust, MMIC-compatible WLP
 chips. Compatible with standard MMIC fabrication processes, our technology has proved
 suitable for packaging various high-frequency MMIC and MEMS devices. Furthermore,
 the packages meet the hermeticity specifications of Military Standard 883. The current
 WLP processes can already produce devices with an RF functional yield exceeding 85%,



72                       Technology Review Journal • Spring/Summer 2006
                        Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



and further improvement in circuit yield is expected as WLP processes mature and are
optimized.
Low-loss RF vias are also realized with an insertion loss below 0.35 dB at 50 GHz without
matching and 0.15 dB with proper matching (Figure 4, page 86). The packages exhibit
excellent mechanical integrity during the dicing process. Data obtained from packages
before and after die separation show that the dicing process affects neither device perfor-
mance nor package integrity. Shock and vibration tests demonstrated the mechanical
robustness of the packages. Our novel technology enables wafer-level hermetic packaging
of RF MMIC and RF MEMS devices for improved performance and reliability. It realizes
affordable, lightweight, multifunctional modules for space applications.
RF MMIC designers who are interested in implementing WLP processes with their RF
designs will need to consider the effects of WLP on their device/circuit performance. The
packaged devices must be designed properly, taking into account the effects of the cavity
height and the proximity of the sealing ring. Most of those effects can be eliminated or
minimized by proper modeling. WLP can have the following effects:
• Parasitic effects due to close proximity of the grounded seal ring to RF circuitry
• Modes (cavity resonances) generated by the enclosed cavity and its effects on RF
    MMIC performance
• Line impedance changes due to close proximity of other circuitry/structures
• Signal coupling between the substrate and the cover wafer or the features/device
    on the cover wafer.
Despite the simplicity of WLP implementation in existing MMIC processes, three-
dimensional modeling tools/methodologies must be used in designing WLP circuitry.
Many two-dimensional approximations commonly used in circuit design can no longer be
applied, because of their close proximity of structures in the z direction. RF calibration
structures should also be carefully considered and designed to ensure meaningful
measurements are obtainable from packaged devices. Northrop Grumman is constructing
the WLP design kit as part of the WLP technology baseline effort to offer some guidance
in designing circuits.


Acknowledgment
The authors wish to thank the Defense Advance Research Projects Agency’s (DARPA’s)
Intelligent RF Front Ends program for enabling the advancement of the LD RF MEMS
switch technology and the WLP technology at Northrop Grumman Space Technology.


References
1.   A.V. Chavan and K.D. Wise, “A Batch-processed Vacuum-sealed Capacitive Pressure
     Sensor,” Transducers ’97 Digest of Technical Papers, 1997 Int. Conf. Solid-State
     Sensors and Actuators, Chicago, June 16–19, 1997, pp. 1449–1452. Northrop Grumman
     employees may access this document via http://sitg2.ms.northgrum.com/etl/
     request.cfm.
2.   A. Berthold and M.J. Vellekoop, “IC-Compatible Silicon Wafer-to-Wafer Bonding,”
     Sensors and Actuators: A. Physical, Vol. 60, No. 1-3, May 1997, pp. 208–211. Northrop
     Grumman employees may access this document via http://sitg2.ms.northgrum.com/
     etl/request.cfm.


                       Technology Review Journal • Spring/Summer 2006                      73
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



3.  M. Esashi, A. Nakano, S. Shoji, and H. Hebiguchi, “Low-Temperature Silicon-to-
    Silicon Anodic Bonding with Intermediate Low Melting Point Glass,” Sensors and
    Actuators: A. Physical, Vol. 23, No. 1-3, April 1990, pp. 931–934. Northrop Grumman
    employees may access this document via http://sitg2.ms.northgrum.com/etl/
    request.cfm.
4. H.J. Quenzer and W. Benecke, “Low Temperature Silicon Wafer Bonding,” Sensors
    and Actuators: A. Physical, Vol. 32, No. 1-3, April 1992, pp. 340–344. Northrop
    Grumman employees may access this document via http://sitg2.ms.northgrum.com/
    etl/request.cfm.
5. R.F. Wolffenbuttel, “Low-Temperature Intermediate Au-Si Wafer Bonding; Eutectic or
    Silicide Bond,” Sensors and Actuators: A. Physical, Vol. 62, No. 1-3, July 1997,
    pp. 680–686. Northrop Grumman employees may access this document via
    http://sitg2.ms.northgrum.com/etl/request.cfm.
6. H. Guckel and D.W. Burns, “Planar Processed Polysilicon Sealed Cavities for Pressure
    Transducer Arrays,” IEEE Int. Electron Devices Meeting, IEDM ’84 Technical
    Digest, San Francisco, Calif., December 9–12, 1984, pp. 223–225. Northrop Grumman
    employees may access this document via http://sitg2.ms.northgrum.com/etl/
    request.cfm.
7. M.B. Cohn, Y. Liang, R.T. Howe, and A.P. Pisano, “Wafer-to-Wafer Transfer of
    Microstructures for Vacuum Packaging,” Technical Digest, 1996 Solid-State Sensor
    and Actuator Workshop, Hilton Head, S.C., June 3–6, 1996, pp. 32–35. Northrop
    Grumman employees may access this document via http://sitg2.ms.northgrum.com/
    etl/request.cfm.
8. Y.T. Cheng, W.T. Hsu, L. Lin, C.T. Nguyen, and K. Najafi, “Vacuum Packaging
    Technology Using Localized Aluminum/Silicon-to-Glass Bonding,” MEMS ’01,
    Technical Digest 14th IEEE Int. Conf. Micro Electro Mechanical Systems,
    Interlaken, Switzerland, January 21–25, 2001, pp. 18–21. Northrop Grumman
    employees may access this document via http://sitg2.ms.northgrum.com/etl/
    request.cfm.
9. P.P. Chang-Chien and K.D. Wise, “Wafer-Level Packaging Using Localized Mass
    Deposition,” Int. Conf. Solid State Sensors and Actuators, Transducers ’01, Munich,
    Germany, June 10–14, 2001, pp. 182–185. Northrop Grumman employees may access
    this document via http://sitg2.ms.northgrum.com/etl/request.cfm.
10. P.P. Chang-Chien, K.J. Tornquist, M.D. Truong, C.B. Geiger, L.S.J. Lee, J.J. Uyeda,
    R.Grundbacher, R. Lai, and A.K. Oki, “Low Temperature Wafer-Level Packaging for
    RF MEMS Switches,” presented at the Government Microcircuit Applications and
    Critical Technology Conference (GOMAC Tech-05), Las Vegas, Nev., April 4–7, 2005,
    Paper 6.4. patty.chang-chien@ngc.com.
11. P.P. Chang-Chien, “MMIC Compatible Lateral Deflection RF MEMS Switches,”
    State-of-the-Art Program on Compound Semiconductors (SOTAPOCS XLII)
    and Processes at the Compound-Semiconductor/Solution Interface: Proc. Int.
    Symposia, 207th meeting of the Electrochemical Society, Quebec City, Canada,
    May 15–20, 2005, pp. 301–310. Northrop Grumman employees may access this
    document via http://sitg2.ms.northgrum.com/etl/request.cfm.
12. P.P. Chang-Chien, K.J. Tornquist, M.Y. Nishimoto, C.B. Geiger, L.S.J. Lee, M.D.Truong,
    J.J. Uyeda, L.J. Lembo, M.E. Barsky, R. Lai, and A.K. Oki, “Advanced Integration
    Technologies for Wideband, Affordable Microsystems,” presented at SPIE Intelligent
    Integrated Microsystems Conference, Kissimmee (Orlando), Fla., April 19–21, 2006.
    patty.chang-chien@ngc.com.

74                       Technology Review Journal • Spring/Summer 2006
                   Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



Author Profiles
                      Patty P. Chang-Chien is a staff engineer in Northrop Grumman
                      Space Technology’s Microelectronics Center, Technology
                      Development Department. She leads the WLP, RF MEMS tech-
                      nology, and heterogeneous integration development efforts.
                      She has over 11 years of experience in WLP, heterogeneous
                      integration, and MEMS device design, fabrication, and testing.
                      She has authored numerous conference and journal papers on
                      WLP and RF MEMS technologies. She received a BS from the
                      California Institute of Technology, an MS from the University
                      of California, Los Angeles, and a PhD from the University of
                      Michigan, Ann Arbor, all in electrical engineering.

                      patty.chang-chien@ngc.com
                      Kelly J. Tornquist is a member of the technical staff in
                      Northrop Grumman Space Technology’s Microelectronics
                      Center, Technology Development Department. She has five
                      years of RF design and modeling experience in millimeter-
                      wave devices, circuits, and WLP devices. She holds a BS
                      from Rutgers University and an MS from the University of
                      Michigan, Ann Arbor, both in electrical engineering.

                      kelly.tornquist@ngc.com




                      Matt Y. Nishimoto is a staff engineer in Northrop Grumman
                      Space Technology’s RF Product Center, Advanced Technolo-
                      gies Department. He has 10 years of experience in designing
                      and developing millimeter-wave integrated circuits. He is the
                      principle investigator on DARPA’s Intelligent RF Front Ends
                      program. He was manager of an LNA risk-reduction hardware
                      program, which produced a world-record amplifier noise figure
                      of 183 GHz. He holds a BS and an MS, both in electrical
                      engineering, from the University of Hawaii at Manoa.

                      matt.nishimoto@ngc.com




                  Technology Review Journal • Spring/Summer 2006                      75
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



                             Craig B. Geiger is a process engineer in Northrop Grumman
                             Space Technology’s Microelectronics Center, Semiconductor
                             Processes Department. He has over 17 years of experience in
                             the fabrication and processing of GaAs HEMT and hetero-
                             junction bipolar transistor (HBT) devices. He has developed
                             several back-side processes, including wafer bonding, wafer
                             thinning, and via etching. He received a BS from the Univer-
                             sity of California, Los Angeles, and an MS from California
                             State University, Long Beach, both in mechanical engineering.

                             craig.geiger@ngc.com

                             Ling-Shine Jane Lee is a process engineer in Northrop
                             Grumman Space Technology’s Microelectronics Center,
                             Semiconductor Processes Department. With over 17 years
                             of experience in the fabrication and processing of GaAs,
                             InP HEMT, and HBT devices, she has developed and estab-
                             lished many processes used in Northrop Grumman Space
                             Technology’s MMIC production. She holds a BS in chemistry
                             from National Taiwan University, Taipei, Taiwan; an MS in
                             chemistry from the University of Notre Dame; and an MS in
                             metallurgical engineering from Ohio State University.

                             jane.lee@ngc.com
                             Minhdao D. Truong is a staff engineer in Northrop Grumman
                             Space Technology’s Microelectronics Center, Test Depart-
                             ment. He has over 20 years of experience in testing advanced
                             millimeter-wave circuits and developing test hardware and
                             software. He focuses on test development for applications
                             ranging from modular base stations to heterogeneously
                             integrated MMICs with WLP. He received a BS in electrical
                             engineering, specializing in RF communications, from
                             California State University, Long Beach.

                             minhdao.truong@ngc.com

                             Jansen J. Uyeda is the section head for the photolithography
                             and wet processing group in Northrop Grumman Space
                             Technology’s Microelectronics Center, Semiconductor
                             Processes Department. He has over nine years of experience in
                             process development for GaAs and InP HBT devices; GaAs,
                             InP, and GaN HEMT devices; and RF MEMS, WLP, and other
                             advanced processes. In 2003, he was a member of the team
                             that received the Space Technology Award for Innovation for
                             advanced HEMT and submicron HBT fabrication technology.
                             He holds a BS from the University of Hawaii at Manoa and an
                             MS from the University of Southern California, both in
                             electrical engineering.

                             jansen.uyeda@ngc.com

76                       Technology Review Journal • Spring/Summer 2006
 Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



    Lawrence J. Lembo is a senior staff scientist in Northrop
    Grumman Space Technology’s Microelectronics Center,
    Technology Development Department. He was previously
    manager of the Electro-Optics, Lasers, and Research Center,
    Photonics Technology Department. He has responsibilities
    both as the lead Northrop Grumman Space Technology
    photonics technologist and as project manager for DARPA’s
    Intelligent RF Front Ends program. He has over 23 years of
    experience in optical physics, specializing in photonics
    technology and nonlinear optics. He holds 12 patents in the
    field of photonics technology and has published over 30
    articles in professional journals. He received a BS from the
    Massachusetts Institute of Technology and a PhD from
    Stanford University, both in physics.

    larry.lembo@ngc.com

    Michael E. Barsky is the assistant department manager of
    Northrop Grumman Space Technology’s Microelectronics
    Center, Semiconductor Processes Department. With over 10
    years of experience in semiconductor fabrication, he manages
    semiconductor fabrication at the center. He is involved in all
    aspects of development and production of integrated circuits.
    Previously, he was a HEMT product engineer responsible for
    Northrop Grumman Space Technology’s InP HEMT process
    and product development, as well as GaAs HEMT production.
    He holds a BS from the University of California, Irvine, and a
    PhD from the University of California, Los Angeles, both in
    chemistry.

    mike.barsky@ngc.com

    Richard Lai is a Technical Fellow and manager of Northrop
    Grumman Space Technology’s Microelectronics Center,
    Technology Development Department. He has been the
    principal investigator for an advanced HEMT MMIC research
    and development project since 1994. He has received four
    corporate Chairman’s and President’s Awards for Innovation
    for work on GaAs power HEMT MMIC development and InP
    HEMT MMIC development. He also received a Paper of the
    Decade Award for the International Conference on InP and
    Related Materials and was honored with the Jet Propulsion
    Laboratory’s Award for Excellence for his work on cryogenic
    InP HEMT MMIC development. He has authored and coau-
    thored over 150 papers, patents, and conference presentations
    in the area of advanced GaAs- and InP-based device and
    circuit technology, establishing world-record performance for
    low-noise, high-frequency, and power amplifiers. He received



Technology Review Journal • Spring/Summer 2006                      77
Low-Temperature, Hermetic, High-Yield Wafer-Level Packaging Technology



                             his BS from the University of Illinois, Urbana-Champaign, and
                             his MS and PhD from the University of Michigan, Ann Arbor,
                             all in electrical engineering.

                             richard.lai@ngc.com

                             Aaron K. Oki is a Technical Fellow and deputy director of
                             Northrop Grumman Space Technology’s Microelectronics
                             Center. Previously, as manager of the Microelectronic Products
                             and Technology Development departments, he was respon-
                             sible for the development and production of GaAs, InP, GaN,
                             and other advanced technologies. He has led the work on
                             advanced GaAs and InP HBT technologies since 1985.
                             He holds 18 U.S. patents on III-V semiconductor technology
                             and has coauthored over 200 publications on GaAs and InP
                             technologies. He received a BS from the University of Hawaii
                             and an MS from the University of California, Berkeley, both in
                             electrical engineering.

                             aaron.oki@ngc.com




78                       Technology Review Journal • Spring/Summer 2006

				
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Description: Package can also be said that the semiconductor integrated circuit chip with the installation of the shell, which not only plays placed, fixed, sealed, protecting the chip and enhanced the role of thermal conductivity, but also inside the chip to communicate with the outside world, a bridge circuit - chip Contacts with a wire connected to the package shell pins, these pins and wires through the printed circuit board to establish a connection with other devices. Thus, for many IC products, the packaging technology are very crucial aspect.