VHDL - PowerPoint by xiangpeng



Rabee Shatnawi
 Rami Haddad
What is this presentation
 This presentation will introduce
the key concepts in VHDL and the
  important syntax required for
       most VHDL designs,
     Why to use VHDL?
In most cases, the decision to use
VHDL over other languages such as
Verilog or SystemC, will have less to do
with designer choice, and more to do
with software availability and company
decisions…. Or the professor's choice
• Verilog has come from a „bottom-up‟
 tradition and has been heavily used by the
 IC industry for cell-based design,
• whereas the VHDL language has been
 developed much more from a „topdown‟

     Of course, these are generalizations and
      largely out of date in a modern context
Entity: model interface

• The entity defines how a design element
  described in VHDL connects to other VHDL
  models …
• and also defines the name of the model.
• It allows the definition of any parameters
  that are to be passed into the model using
Entity definition

entity test is
 end entity test;

• or:
entity test is
end test;

• How to connect Entities together?

 -The method of connecting entities together is
  using PORTS.
- PORTS are defined in the entity using the
  following method:

port (
...list of port declarations...
• The port declaration defines the type of
 connection and direction where

port (
in1, in2 : in bit;
out1 : out bit
Entity Port Modes

• in:
   – signal values are read-only

• out:
   – signal values are write-only

• buffer:
   – comparable to out
   – signal values may be read, as well

• inout:
   – bidirectional port

If the model has a parameter, then it is
  defined using generics.

generic (
 gain : integer := 4;
 time_delay : time = 10 ns

• It is also possible to include model specific
  constants in the entity using the standard
  declaration of constants method

constant : rpullup : real := 1000.0;
a complete examples, meet
our first Entity……. test
entity test is
port (
in1, in2 : in bit;
out1 : out bit
generic (
gain : integer := 4;
time_delay : time := 10 ns
constant : rpullup : real := 1000.0;
end entity test;
Architecture: model behavior
• Implementation of the design
• Always connected with a specific entity
  – one entity can have several architectures
  – entity ports are available as signals within the

• Contains concurrent statements
Basic definition of an architecture

• While the entity describes the interface
 and parameter aspects of the model
• the architecture defines the behavior.
• There are several typesanyVHDL signals or
                          of local
 architecture and ….
• VHDL allows different architectures to be
 defined for the same entity. be declared
architecture behaviour of test is
..architecture declarations
...architecture contents
end behaviour;
• Signals are the primary objects describing
  the hardware system and are equivalent
  to “wires”.
• They represent communication channels
  among concurrent statements of system
• Signals can be declared in:
  – Package declaration
  – Architecture
  – Block:
  – Subprograms:
Hierarchical design

• Functions
• Packages
• Components
• Procedures

• A simple way of encapsulating behavior in
 a model that can be reused in multiple

• Can be defined locally to an architecture
 or more commonly in a package
• The simple form of a function is to define
 a header with the input and output
 variables as shown below:

function name (input declarations)
   return output_type is
... variable declarations
... function body
function mult (a,b : integer) return integer is
return a * b;
                          The header:
                  is the place where the types
Package :                containers
              Functionand functions are
package name is
...package header contents
end package;
package body name is
... package body contents
end package body;       package body:
                      where the declarations
                           take place
library ieee;
use ieee.std_logic_1164.all;
-- here is the entity
entity halfadd is
port (a, b : in std_logic;
sum, c : out std_logic);
end halfadd;
architecture comp of halfadd is
-- a concurrent statement implementing the and gate
c <= a and b;
-- a concurrent statement implementing the xor gate
sum <= a xor b;
end comp;
library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port (ina, inb, inc : in std_logic;
sumout, outc : out std_logic);
end fulladd;
architecture top of fulladd is
component halfadd
port (a, b : in std_logic;
sum, c : out std_logic);
end component;
signal s1, s2, s3 : std_logic;
-- a structural instantiation of two half adders
h1: halfadd port map( a => ina, b => inb,
sum => s1, c => s3);
h2: halfadd port map( a => s1, b => inc,
sum => sumout, c => s2);
outc <= s2 or s3;
end top;

• Case insensitive
• Comments: '--' until end of line Statements
    are terminated by ';'
    (may span multiple lines)
•   List delimiter: ','
•   Signal assignment: '<=„
•    User defined names:
    – letters, numbers, underscores
    – start with a letter
VHDL …. Identifier
• (Normal) Identifier Letters, numerals,
• Case insensitive
• No two consecutive underscores
• Must begin with a letter
• Not a VHDL keyword
                        mySignal_23 -- normal identifier
                        rdy, RDY, Rdy -- identical identifiers
                        vector_&_vector -- X : special character
                        last of Zout -- X : white spaces
                        idle__state -- X : consecutive underscores
                        24th_signal -- X : begins with a numeral
                        open, register -- X : VHDL keywords
VHDL Structural Elements

• Entity : Interface Architecture :
• Implementation, behavior, function
• Configuration : Model chaining, structure,
• Process : Concurrency, event controlled
• Package : Modular design, standard
• data types, constants
• Library : Compilation, object code
Hierarchical Model Layout

• VHDL allows for a hierarchical model layout, which means
  that a module can be assembled out of several
  submodules. The connections between these submodules
  are defined within the architecture of a top module. As
  you can see, a fulladder can be built with the help of two
  halfadders (module1, module2) and an OR gate
   Component :example
ENTITY half_adder IS
 PORT ( A, B : IN STD_LOGIC;                 begin
      sum, carry : OUT STD_LOGIC );
END half_adder;                                 MODULE1: HALFADDER
ARCHITECTURE structural OF half_adder IS         port map( A, B, W_SUM, W_CARRY1 );
COMPONENT xor2                           entity FULLADDER is
 PORT ( a, b : IN STD_LOGIC;               port (A,B, CARRY_IN: in bit;
                                                MODULE2: out bit);
                                                SUM, CARRY: HALFADDER
       c : OUT STD_LOGIC );                      port map ( W_SUM, CARRY_IN,
                                         end FULLADDER;
END COMPONENT;                           architecture STRUCT SUM, W_CARRY2 );
                                                                 of FULLADDER is
COMPONENT and2                       begin signal W_SUM, W_CARRY1, W_CARRY2 : bit;
     ENTITY b : IN
 PORT ( a, and2 IS STD_LOGIC;                   MODULE3: ORGATE
                                            component HALFADDER
       c : OUT STD_LOGIC );
      PORT ( a, b : IN STD_LOGIC;                port
                                        MODULE1: :map ( in bit;
                                             port (A, B HALFADDER
          output : OUT                            SUM, CARRY : out bit);
                                             W_CARRY2, W_CARRY1, CARRY ); A,
                                                         port map ( A            =>
BEGINEND and2;                              end component;
                                                                      SUM => W_SUM,
     : xor2 PORT MAP ( a => a, b IS
 ex1 ARCHITECTURE gate OF and2 => b, c => sum ); ORGATE
                                             end STRUCT;
 or1 : and2 PORT MAP ( a => a, b => b, c => carryB); in bit;
                                             port (A, :               B        => B,
     BEGIN                                                            CARRY => W_CARRY
END structural;                                   RES : out bit);
      output <= ( a AND b ) AFTER 5ns; ); end component;
     END gate                             ..
                                       . begin
                                   end STRUCT;
• The process in VHDL is the mechanism by
 which sequential statements can be
 executed in the correct sequence, and
 with more than one process, concurrently.
  – Contains sequentially executed statements
  – Exist within an architecture,
  – only Several processes run concurrently
  – Execution is controlled either via sensitivity list
    (contains trigger signals), or wait-statements
       JustToShow: process                     JustToShow: process
       Begin                                   Begin
              Some statement 1;                   Some statement 1;
              Some statement 2;                   Some statement 2;
              Some statement 3;                   Some statement 3;
              Some statement 4;                   Some statement 4;
              Some statement 5;                   wait<condition>;
       end process JustToShow;                 end process JustToShow;

•   Wait for type expression   Wait for 10ns
•   Wait until condition       Wait until CLK=‘1’
•   Wait on sensitivity list   Wait on Enable
•   Complex wait               Wait unit date after 10ns
• VHDL provides a
JustToShow: process
                             JustToShow: process (        )

   construct called

   sensenitivity list of
   Some statement 1;
                                Some statement 1;
                                Some statement 2;
   a process
   Some statement 2;
                                Some statement 3;
•  Some statement 3;
         list specified
   The statement 4;
   Some                         Some statement 4;
              the process
   next toSomeSig
   wait on                      end process JustToShow;
    process JustToShow;
• The same as wait
    on sensitivity_list at
    the end of a
JustToShow: process (signa1,signal2,signal3)
   Some statement 1;
   Some statement 2;
   Some statement 3;                           Signal2 has changed
                                                    Signal3 has changed
   Some statement 4;
   Some statement 5;
end process JustToShow;
JustToShow: process (signal1,signal2,signal3)   Signa1= 0
Begin                                           Signal3=5   6
        Some statement 1;
        Some statement 3;
        Some statement 4;
        Some statement 5;
end process JustToShow
begin          A=1   A<=D+1
                     A<=2      3
  A<=2;        B=1             2
  B<=A+C;      C=1
end process;   E=1   E<=A*2;   2

• Variables are available within processes
    – Named within process declarations
    – Known only in this process
• Immediate assignment
• An assignment to a variable is made with := symbol.
• The assignment take instance effect and each variable can be
  assigned new values as many times as needed.
• A variable declaration look similar to a signal declaration and starts
  with variable keyword
• Keep the last value
• Possible assignments
    – Signal to variable
    – Variable to signal
    – Types have to match
Variables vs. Signals
• Signals
  – In a process, only the last signal assignment is carried
  – Assigned when the process execution is suspended
  – “<=“ to indicate signal assignment
• Variables
  – Assigned immediately
  – The last value is kept
  – “:=“ to indicate variable assignment
Variables vs. Signals
signal A, B, C, X, Y : integer;   signal A, B, C, Y, Z : integer;
begin                             signal M, N : integer;
  process (A, B, C)               begin
    variable M, N : integer;        process (A, B, C, M, N)
  begin                             begin
    M := A;                           M <= A;
    N := B;                           N <= B;
    X <= M + N;                       X <= M + N;
    M := C;                           M <= C;
    Y <= M + N;                       Y <= M + N;
 end process;                       end process;
        A                                C
            +       X                        +       X
        B                                B
                C                                C
                        +   Y                            +   Y
                B                                B
Variable Av,Bv,Ev :integer :=0;
  Ev <= Av*2;
  A <=Av;
  B <=Bv;
  E <=Ev;
end process
The world is not sequential
• Its convention to specify
    things in a sequential way,
    this is not the simplest way to
    describe reality.
•   Processes are concurrent
•   Several processes run parallel
    linked by signals in the
    sensitivity list
•   sequential execution of
•   Link to processes of other
    entity/architecture pairs via
    entity interface
   Architecture SomeArch of SomeEnt is
   End process P1;
 End process P1;
  End process P1;
end Architecture SomeArch ;
  IF Statement:
entity IF_STATEMENT is
   port (A, B, C, X : in bit_vector (3 downto 0);
         Z         : out bit_vector (3 downto 0);
architecture EXAMPLE1 of IF_STATEMENT is architecture EXAMPLE2 of IF_STATEMENT is
begin                                    begin
  process (A, B, C, X)                     process (A, B, C, X)
  begin                                    begin
    Z <= A;
     if (X = "1111") then                     if (X = "1111") then
       Z <= B;                                  Z <= B;
     elsif (X > "1000") then                  elsif (X > "1000") then
       Z <= C;                                  Z <= C;
     end if;                                  else
  end process;                                  Z <= a;
end EXAMPLE1;                                 end if;
                                           end process;
                                         end EXAMPLE2;
  Case statement
entity RANGE_1 is                              entity RANGE_2 is
port (A, B, C, X : in integer range 0 to 15;   port (A, B, C, X : in bit_vector(3 downto 0);
       Z        : out integer range 0 to 15;          Z           : out bit_vector(3 downto 0);
end RANGE_1;                                   end RANGE_2;

architecture EXAMPLE of RANGE_1 is             architecture EXAMPLE of RANGE_2 is
begin                                          begin
  process (A, B, C, X)                           process (A, B, C, X)
  begin                                          begin
    case X is                                      case X is
       when 0 =>                                      when "0000" =>
         Z <= A;                                        Z <= A;
       when 7 | 9 =>                                  when "0111" | "1001" =>
         Z <= B;                                        Z <= B;
       when 1 to 5 =>                                 when "0001" to "0101" =>         -- wrong
         Z <= C;                                        Z <= C;
       when others =>                                 when others =>
         Z <= 0;                                        Z <= 0;
    end case;                                      end case;
  end process;                                   end process;
end EXAMPLE;                                   end EXAMPLE;
For loop

• entity FOR_LOOP is
    port (A : in integer range 0 to 3;
          Z : out bit_vector (3 downto 0));
   end FOR_LOOP;
  architecture EXAMPLE of FOR_LOOP is
    process (A)
      Z <= "0000";
       for I in 0 to 3 loop
         if (A = I) then
            Z(I) <= `1`;
         end if;
       end loop;
    end process;
  end EXAMPLE;
entity CONV_INT is
   port (VECTOR: in bit_vector(7 downto 0);
        RESULT: out integer);
 end CONV_INT;
architecture A of CONV_INT is   architecture B of CONV_INT is    architecture C of CONV_INT is
begin                           begin                            begin
  process(VECTOR)                 process(VECTOR)                  process(VECTOR)
    variable TMP: integer;          variable TMP: integer;            variable TMP: integer;
                                                                      variable I     : integer;
  begin                           begin                            begin
    TMP := 0;                       TMP := 0;                         TMP := 0;
                                                                      I := VECTOR'high;
    for I in 7 downto 0 loop        for I in VECTOR'range loop        while (I >= VECTOR'low)
      if (VECTOR(I)='1') then         if (VECTOR(I)='1') then    loop
         TMP := TMP + 2**I;              TMP := TMP + 2**I;              if (VECTOR(I)='1') then
      end if;                         end if;                               TMP := TMP + 2**I;
    end loop;                       end loop;                            end if;
                                                                         I := I - 1;
    RESULT <= TMP;                  RESULT <= TMP;                    end loop;
  end process;                    end process;                        RESULT <= TMP;
end A;                          end B;                             end process;
                                                                 end C;
Exit & Next

• The exit command allows a FOR loop to be exited completely. This can be
   useful when a condition is reached and the remainder of the loop is no
   longer required. The syntax for the exit command is shown below:
        for i in 0 to 7 loop
        if ( i = 4 ) then

• The next command allows a FOR loop iteration to be exited, this is slightly
   different to the exit command in that the current iteration is exited, but the
   overall loop continues onto the next iteration. This can be useful when a
   condition is reached and the remainder of the iteration is no longer
   required. An example for the next command is shown below:
        for i in 0 to 7 loop
        if ( i = 4 ) then
  Conditional Signal Assignment
     port (A, B, C, X : in bit_vector (3 downto 0);
             Z_CONC : out bit_vector (3 downto 0);
             Z_SEQ : out bit_vector (3 downto 0));
     -- Concurrent version of conditional signal assignment
     Z_CONC <= B when X = "1111" else
                     C when X > "1000" else
                                                            •   TARGET <= VALUE;
     -- Equivalent sequential statements
                                                                TARGET <= VALUE_1 when
     process (A, B, C, X)
                                                                CONDITION_1 else
                                                                          VALUE_2 when
         if (X = "1111") then
                                                                CONDITION_2 else
           Z_SEQ <= B;
         elsif (X > "1000") then
           Z_SEQ <= C;
           Z_SEQ <= A;
         end if;
     end process;
   end EXAMPLE;
  Selected Signal Assignment
    port (A, B, C, X : in integer range 0 to 15;
           Z_CONC : out integer range 0 to 15;
           Z_SEQ : out integer range 0 to 15);

  -- Concurrent version of selected signal assignment
     with X select
        Z_CONC <= A when 0,
                        B when 7 | 9,
                        C when 1 to 5,
                        0 when others;
     with EXPRESSION select
          TARGET <= VALUE_1 statements
     -- Equivalent sequentialwhen CHOICE_1,
     process (A, B, C, X)
     begin           VALUE_2 when CHOICE_2 | CHOICE_3,
        case X is    VALUE_3 when CHOICE_4 to CHOICE_5,
          when 0     · · · => Z_SEQ <= A;
                           => Z_SEQ others;
          when 7 | 9VALUE_n when <= B;
          when 1 to 5 => Z_SEQ <= C;
          when others => Z_SEQ <= 0;
     end process;
   end EXAMPLE;

 Miscellanies           **    abs   not
 Multiplying operators * /    Mod   rem
 Signed operator        +     -
 Adding operator        +     -     &
 Shift operator         sll   srl   sla    sra
                        rol   ror
 Relational operation   =     /=    <      <=
                        >     >=
 Logical operator       and   or    nand
                        nor   xor   xnor

• Functions
   –    function name can be an operator
   –   arbitrary number of input parameters
   –   exactly one return value
   –   no WAIT statement allowed
   –   function call <=> VHDL expression
• Procedures
   – arbitrary number of parameters of any possible direction
   – RETURN statement optional (no return value!)
   – procedure call <=> VHDL statement
• Subprograms can be overloaded
• Parameters can be constants, signals, variables or files
architecture EXAMPLE of FUNCTIONS is
function COUNT_ZEROS (A : bit_vector)
  return integer is
    variable ZEROS : integer;           begin
  begin                                   WORD_0 <= COUNT_ZEROS(WORD);
    ZEROS := 0;                           process
    for I in A'range loop                 begin
      if A(I) = '0' then                    IS_0 <= true;
         ZEROS := ZEROS +1;                 if COUNT_ZEROS("01101001") > 0 then
      end if;                                  IS_0 <= false;
    end loop;                               end if;
    return ZEROS;                           wait;
  end COUNT_ZEROS;                        end process;
                                        end EXAMPLE;
  signal WORD: bit_vector(15 downto 0);
  signal WORD_0: integer;
  signal IS_0:        boolean;
• architecture EXAMPLE of PROCEDURES is
    procedure COUNT_ZEROS
                            (A: in bit_vector;signal Q: out integer) is
      variable ZEROS : integer;
      ZEROS := 0;
      for I in A'range loop
        if A(I) = '0' then
           ZEROS := ZEROS +1;
        end if;
      end loop;
      Q <= ZEROS;
   signal COUNT: integer;
    signal IS_0:     boolean;
      IS_0 <= true;
      COUNT_ZEROS("01101001", COUNT);
      wait for 0 ns;
      if COUNT > 0 then
         IS_0 <= false;
      end if;
    end process;
Data Types

• Each object in VHDL has to be of some type, which
    defines possible values and operations that can be
    performed on this object (and other object of the
    same type) .
•   VHDL is strongly typed language which causes
    that two types defined in exactly the same way
    but differing only by names will be considered
•   If a translation from one type to another is
    required, then type convention must be applied
    even if the two types are similar.
Data Types

Scalar      Composite      Access          Anphysical type is a scalar type
                                            A integer type is a is aadiscrete
                                               enumeration type is whose
                                           A floating point typenumeric type
 type         type          type           approximation to definedof listing
                                           whose values are some physical
                                            for representing the set by
                                           set of values include integerreal
                                           numbers in specific explicitly.
                                           (enumerating) them range.
                                            quantity, such as mass, length,
                                           numbers in a specified range. time
  Integer                                   or voltage.
    type                                   type byte_int is range 0 to 255;
                                                 signal_level (unknown, low,
                                           type logic_level isis range –10.00
                                           type voltage_level is range 0 to 5;
                                            type distance is
                                           undriven, high); range 0 to 1E5
                                           to +10.00;
 Floating                                   units
   point                                    um;
                                            mm = 1000 um;
Enormous                                    In_a=25400 um;
  type                                      end units;
                                            Variable Dis1,dis2 :Distance;
 Physical                                   Dis1:=28mm;
Data Types

                           A record type allows declaring composite
                           objects whose elements can be from
                           different types.

                              Type RegName is (AX,BX,DX);
                              Type Operation is record
                                     Mnemonic:string (1 to 10);
     Is an indexed collection of elements all of the same type. Arrays may be one-
                                      multidimensional (with a downto indices).
     dimensional (with one index) orOpCode:Bit_Vector(3 number of0);
     • type VAR is array (0 to 7)Op1,op2,Reg:RegName;
                                      of integer;
                              End record;
        constant SETTING: VAR := (2,4,6,8,10,12,14,16);
                              Variable Instr3:= natural range
     • type VECTOR2 is array (natural range <>, Operation; <>) of std_logic;
        variable ARRAY3x2: VECTOR2 (1 to 3, 1 to 2)) := ((„1‟,‟0‟), („0‟,‟-„), (1, „Z‟));
                              Instr3. Mnemonic:= “Mul AX, BX”;

• A type with a constraints. A value belong
 to a subtype of a given type if it belongs
 to the type and satisfied the constraints.
  – Subtype Digits is Integer range 0 to 9;
• Integer is a predefined type and the
 subtype digits will constraints the type to
 ten values only.
Standard Data Types
                        package STANDARD is
                         type BOOLEAN is (FALSE,TRUE);
• Every type has a       type BIT is (`0`,`1`);
  number of possible     type CHARACTER is (-- ascii set);
  values                 type INTEGER is range
• Standard types are                        -- implementation_defined
  defined by the
  language               type REAL is range
• User can define his                      -- implementation_defined
  own types              -- BIT_VECTOR, STRING, TIME
                        end STANDARD;

• Signal Instruction :Bit_vector(15 downto 0);
  – Alias   OpCode : Bit_vector(3 downto 0) is
    Instruction(15 downto 12);
  – Alias Source : Bit_vector(1 downto 0) is
    Instruction(11 downto 10);
  – Alias design : Bit_vector(1 downto 0) is
    Instruction(9 downto 8);
  – Alias Immdata : Bit_vector(7 downto 0) is
    Instruction(7 downto 0);
• A basic operation that combines one or more values into a
  composite value of a record or array type;
   – Variable data_1 :Bit_vecot(0 to 3) := („0‟,‟1‟,‟0‟,‟1‟);
   – Variable data_1 :Bit_vecot(0 to 3) := (1=>„1‟,0=>‟0‟,
   – Signal data_Bus :std_logic_vector (15 downto 0)
     data_Bus<=(15 downto 8 => „0‟, 7 downto 0 =>‟1‟);
   – Signal data_Bus :std_logic_vector (15 downto 0)
     data_Bus<=(14downto 8 => „0‟, others=>‟1‟);
   – Signal data_Bus :std_logic_vector (15 downto 0)
   – Type Status_record is record
        Name:string(1 to 4);
     End record;
     Variable Status_var: Status_record :=(code=>57,

• architecture EXAMPLE_1 of CONCATENATION is
    signal BYTE           : bit_vector (7 downto 0);
    signal A_BUS, B_BUS : bit_vector (3 downto 0);
    BYTE <= A_BUS & B_BUS;
  end EXAMPLE;

• Variable Bytedat : bit_vector(7 downto 0);
  Alias Modulus: bit_vector(6 downto 0) is bytedat(6 downto 0);
  Bytedate:=„1‟ & modulas;
• Attributes are a feature of VHDL that allow you to extract additional
   information about an object (such as a signal, variable or type) that may
   not be directly related to the value that the object carries.
    – Type table is array (1 to 8) of Bit;
      Variable array_1: table:=„00001111‟;
      Arrat_1‟left, the leftmost value of table array is equal to 1;
    – architecture example of enums is
           type state_type is (Init, Hold, Strobe, Read, Idle);
           signal L, R: state_type;
           L <= state_type’left; -- L has the value of Init
           R <= state_type’right; -- R has the value of Idle
        end example;
    – (clock'EVENT and clock='1')
    – type state_type is (Init, Hold, Strobe, Read, Idle);
      variable P: integer := state_type’pos(Read); -- P has the value of 3
    – type state_type is (Init, Hold, Strobe, Read, Idle);
      variable V: state_type := state_type’val(2); -- V has the value of Strobe

• http://www.seas.upenn.edu/~ese201/vhdl/v
• http://www.vhdl-online.de/~vhdl/tutorial/
• http://tams-www.informatik.unihamburg .de
  /vhdl/doc/cookbook/VHDL Cookbook .pdf

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