# PULSE AND DIGITAL CIRCUITS by eswarblog

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Code No: V0421                                                                    SET - 1
II B.Tech II Semester (R07) Regular/supply Examinations, Apr- 2010

PULSE AND DIGITAL CIRCUITS
(Common to ECE, BME, E.Con.E, ECC, ICE)
Time: 3 Hours                                                                   Max Marks: 80
All Questions carry equal marks

1. a) A symmetrical periodic square waveform with peak amplitude of ‘V’ volts, and time
period of ‘T’ is applied to an RC integrator circuit as an input. Find the steady state
voltage across each element in the circuit.
b) An ideal 1µs pulse is applied to an RC circuit. Calculate and plot the output waveform
when the upper 3 dB frequency is 10 MHz and 0.1 MHz.

2. a) With the help of piecewise linear transfer characteristics, explain the operation of a
clipping circuit at two independent levels.
b) A pulse of 12 V and duration of 5 µs is applied to the circuit shown in Fig.1.1.
Assuming that the capacitor in the circuit is initially uncharged, and the diode ‘D’ is
ideal, determine v0(t) and sketch the same with respect to time.

3. a) Explain how a transistor can be used as an electronic switch.
b) Design a high speed transistor switch shown in Fig.1.2 for the given specifications:
VCC = 12, VBB =10, IC = 8 mA, hFE(min) = 30, and R2 = 3R1. Assume suitable saturation,
cut off voltages for the given transistor.

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Code No: V0421                                                                      SET - 1
4. a) Draw the self biased symmetrical binary circuit and derive the necessary relations for
steady state analysis of the circuit.
b) Discuss about different triggering methods used in multivibrator circuits.

5. a) Discuss about general considerations of Miller and Bootstrap time base generators.
b) Design a free running UJT sweep waveform generator with the sweep amplitude of 6
V. The sweep interval of the waveform is expected to be 3 ms with negligible retrace
interval. The slope error is 0.75. Determine the values of RB1, RB2, VBB, R, and C.

6. a) Illustrate the terms ‘Synchronization’ and ‘frequency division’ of a sweep generator.
b) A free running relaxation oscillator has sweep amplitude of 100 V and a period of 1
ms synchronizing pulses are applied to the device such that breakdown voltage is lowered
by 50 V at each pulse. The synchronizing pulse frequency is 4 kHz. What is the
amplitude and frequency of synchronized oscillator waveform?

7. a) With neat diagrams, explain the principle of operation of four diode bidirectional
sampling gate. Compare the performance of the circuit with that of six diode bidirectional
sampling gate.
b) Describe the errors encountered in series sampling and what is the design procedure
that is adopted to minimize these errors.

8. a) With the help of neat circuit diagram and truth table, explain the working of three input
DTL NAND gate.
b) What do you mean by ‘fan in’ and ‘fan out’? Discuss about the DTL NAND gate
circuit which can improve Fan out of the gate.

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Code No: V0421                                                                      SET - 2
II B.Tech II Semester (R07) Regular/supply Examinations, Apr- 2010

PULSE AND DIGITAL CIRCUITS
(Common to ECE, BME, E.Con.E, ECC, ICE)
Time: 3 Hours                                                                      Max Marks: 80
All Questions carry equal marks

1. a) A low pass RC network is fed by an exponential input voltage. Obtain steady state
voltage across both the elements.
b) Prove that an RC low pass circuit behaves as reasonably good integrator if the time
constant of the circuit is fifteen times the time period of an input signal of V sin( t).

2. a) Draw the clipper circuit using transistor, and explain the operation of it using suitable
waveforms.
b) Sketch the voltage v0(t) across the diode of Figure.2.1 for the input signal shown in the
same Figure.

3. a) What are the important parameters to be observed when the transistor is operated as
electronic switch? Explain them.
b) Discuss about the switching characteristics of a PN junction diode.

4. a) With the aid of circuit diagram, obtain the mathematical relation that a collector
coupled astable multivibrator can function as a voltage to frequency converter.
b) Consider a symmetrical collector coupled astable multivibrator using n-p-n Si
transistors. The circuit and device parameters are: VCC = 6 V, RC = 560 , R = 5.6 k , C
= 50 pF, hFE = 40, and r’bb = 100 . Calculate (i) the waveforms at the base and collector
of one transistor and plot to the scale. Also find the recovery time and frequency of
oscillations.

5. a) Explain the working of transistor based Bootstrap time base generator circuit, and draw
the necessary waveforms.
b) In the circuit shown in Fig. 2.2, VCC = 20 V, L = 200 mH, the inductors internal
resistance is 20 , Rd = 200 . For a 500 µs sweep, draw the waveforms of inductor
current and the voltage between collector and emitter of the transistor. Calculate slope
error of the sweep.

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Code No: V0421                                                                    SET - 2

synchronized?
6. a) How an astable multivibrator can be synchronized? Illustrate with waveforms.
Germanium
b) A symmetrical astable multivibrator using Germanium transistors and operating from a
10 V collector supply voltage has a free period of 1ms. Triggering pulses whose spacing
capacitor
is 750 µs are applied to one base through a small capacitor from a high impedance
source. Find the minimum triggering pulse amplitude required to achieve 1:1
synchronization. Assume that the timing portion of the base waveform is linear.

grams,
7. a) With neat diagrams, explain the principle of operation of six di diode bidirectional
sampling gate.
Give
b) Describe the operation of chopper amplifier. Give the operation of the transistor as a
chopper switch in ON state and in OFF state.
c) Describe the operation of balanced choppers.

8.     Write the following: (a) DTL NAND gate, (b) RTL NOR gate, (c) Prove that NAND and
NOR gates are universal gates.

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Code No: V0421                                                                       SET - 3
II B.Tech II Semester (R07) Regular/supply Examinations, Apr- 2010

PULSE AND DIGITAL CIRCUITS
(Common to ECE, BME, E.Con.E, ECC, ICE)
Time: 3 Hours                                                                       Max Marks: 80
All Questions carry equal marks

1. a) Derive the expression for the percentage tilt when the time constant of an RC high pass
circuit is very large as compared to the period of input symmetrical square waveform.
b) When a ramp signal is transmitted through a linear RC network, the output departs
from the input. Deduce the relation for transmission error for different time constants of
the circuit as compared to the duration of the ramp signal.

2. a) List out the types of clamping circuits used in the industry. Give the circuit diagram of
each type. Explain the operation of a clamping circuit whose output signal has negative
offset.
b) Design a diode clamper circuit to restore the positive peaks of 1 kHz input signal to a
voltage level equal to 5V. Assume that the diode voltage during forward bias condition is
0.7 V.

3. a) Describe the sequence of events that lead to reverse recovery time, storage time, and
transition time in a semiconductor diode.
b) Calculate the output levels ‘v0’ of the circuit shown in Fig. 3.1 for inputs vi = 0 V, and
vi = - 8V. Verify whether the circuit acts as an inverter or not. What is the maximum
value dc current gain required. Select standard junction voltages for the Si transistor
during cut off and saturation, and assume an ideal diode in the circuit.

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Code No: V0421
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4. a) Explain the operation of an emitter coupled monostable multivibrator circuit.
b) Design a collector coupled monostable multivibrator circuit for the given
specifications: VCC = 8V, VBE = -1V, IC(sat) = 2 mA, period of the quasi stable state is 2.5
µs. hFE(min) = 20, the ON transistor (Si) has base current which is 50% in excess of
minimum base current. Assume R2 = 2R1, and ICBO = 0. Assume suitable data.

5. a) With the help of circuit diagram, explain the principle of operation of a constant
current sweep circuit.
b) Design a transistor bootstrap ramp generator to provide an output amplitude of 12 V
over a time period of 2 ms. The input signal is a negative going pulse with an amplitude
of 5 V, a pulse width of 2 ms and the time interval between pulses is 0.5 ms. The load
resistance is 2 k and the ramp is to be linear within 1%. The supply is to be ±15 V.
Assume hFE(min) = 80.

6. a) Describe the frequency division employing a transistor monostable multivibrator.
b) A UJT sweep circuit operates with a valley voltage of 3 V and a peak voltage of 16 V.
A sinusoidal synchronizing voltage of 2 V peak is applied between bases. The intrinsic
stand-off ratio is 0.5. If the natural frequency of the sweep is 1 kHz, over what range of
synchronization signal frequency will the sweep remain in 1:1 synchronization with the
synchronization signal?

7. a) Sketch circuit of a simple diode bidirectional sampling gate and describe its
functioning with neat waveforms. Obtain the expressions for gain A, and the two
minimum control voltage levels.
b) Describe the operation of chopper amplifier. Give the operation of the transistor as a
chopper switch in ON state and in OFF state.

8. a) Realize two input TTL NAND gate truth table and explain its operation with suitable
circuit diagram.
b) With the help of neat circuit diagram and truth table, explain the working of diode
logic AND gate, and RTL AND gate.

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Code No: V0421                                                                        SET - 4
II B.Tech II Semester (R07) Regular/supply Examinations, Apr- 2010

PULSE AND DIGITAL CIRCUITS
(Common to ECE, BME, E.Con.E, ECC, ICE)
Time: 3 Hours                                                                       Max Marks: 80
All Questions carry equal marks

1. a) Give quantitative analysis of compensated and uncompensated attenuators. Give
suitable examples for each case.
b) A 12 Hz symmetrical square wave whose peak- to-peak amplitude is 5V is impressed
upon a high pass circuit whose lower 3 dB frequency is 15 Hz. Determine the peak to
peak amplitude of the output waveform. Find the corner voltages of the output waveform.
Also sketch the input and output waveforms on the same scale.

2. (a) State and explain clamping circuit theorem. Discuss about the practical clamping
circuit with suitable sketches.
b) A rectangular waveform of Vp-p =10 V, with T1 = 2 ms, and T2 = 20 ms is applied to
the dc restorer circuit. The circuit has source resistance Rs = 0 ohms, diode forward
resistance Rf =10 , cutin voltage V = 0 V, Rr = , R = 500 , C = 0.1µF. Compute the
steady state output waveform. Repeat the same for R = 1M .

3. a) Define rise time, storage time, fall time, and turn off time in the case of transistor as a
switch.
b) Design a common emitter transistor switch operating with two power supplies VCC =
18 V, -VBB = -12 V. The transistor is expected to operate at IC = 8 mA, and IB = 0.75 mA.
The static current gain is 25. Assume Si transistor, and R2 = 5R1.

4. a) Explain the operation of a emitter bistable multivibrator circuit with suitable sketches.
b) Design a Schmitt trigger circuit to have UTP = 6 V, LTP = 3 V using silicon
transistors whose hFE(min) = 40. Assume necessary data.

5. a) Define the three errors that occur in a sweep circuit and obtain an expression for these
errors for an exponential sweep circuit.

b) Explain with suitable circuit diagram, the working of a UJT relaxation oscillator and
obtain the expression for the intrinsic standoff ratio.

6. a) Discuss about synchronization of a sweep circuit with symmetrical signals.
b) How a monostable multivibrator circuit can be used for frequency division? Explain
with suitable sketches.
c) What do you mean by phase delay and phase jitters?

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Code No: V0421
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7. a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for
multiple inputs.
b) Explain the operation of a two input sampling gate which does not have any loading
effect on control signal.
c) Give the importance of chopper amplifier.

8. Explain the following terms:
a) Realization of AND and OR gates using universal gates,
b) What do you mean by ‘fan in’ and ‘fan out’? Discuss about the DTL NAND gate
circuit which can improve ‘fan out’ of the gate.

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