COMPUTER ARCHITECTURE

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```					                        Homework1
CAP 208

INTRODUCTION TO COMPUTER ORGANISATION AND ARCHITECTURE

SUBMITTED TO-

Anjlee Mam

SUBMITTED BY-
SACHIN RAJ
B34
D3901
Part-A

Q1. Write the largest decimal number that can be represented by 8-
bit binary word?
Ans-
11111111 = 27 + 26 + 25 + 24 + 23 + 22 + 21 + 20 = 128 + 64 + 32 + 16 + 8 + 4
+ 2 + 1 = 2n+1 - 1 = 255(Highest)
smallest = 0

Q2. Perform the following conversions:
i. (234)10 = (?)2
iii. (10111.101)2 = (?)10
iv. (B9C)2 = (?)8
1.
Ans-

i.   2|234
------------
|117- 0
------------
|58- 1
------------
|29- 0
------------
|14- 1
------------
|7-     0
------------
|3-     1
------------
|1-     1
------------

Ans-11101010

ii. A*16^2+D*16^1+E*16^0
10*16^2+13*16^1+14
2560+208+14
2782 ANS

iii. 1*2^4+1*2^2+1*2^11*2^0+1*2^-1+1*2^-2+1*2^-3
16+4+2+1+0.5+0.125
23+0.5+0.125
23.625 ANS

iv. 101    110    011 100
5(8)   6(8)   3(8) 4(8)

(5634)8 ANS
Q3. Subtract (100)2 from (10111)2 using 2’s complement.
Ans- 100->011(After 1’s complement)
Now, we have find 2’s complement…
011
+1
1 0 0(2’s complement)

Now,
10111
+ 0 0 1 00
1 1 0 1 1 Ans-
Part-B

Q4. How can we use NOR gate as inverter?

Ans-

The inverter-An inverter has exactly one input and one output. The
value of the output is 1 if and only if the input is 0. Otherwise, the
output is 0. In other words, the value of the output is the exact
opposite of the value of the input.

In circuit diagrams, we draw the inverter like this:

The truth table for an inverter looks like this:

x|y
-----
0|1
1|0

The nor-gate

The nor-gate is an or-gate with an inverter on the output. So instead
of drawing several gates like this:

We draw a single or-gate with a little ring on the output like this:
The nor-gate, like the or-gate can take an arbitrary number of inputs.

The truth table for the nor-gate is like the one for the or-gate, except
that all output values have been inverted:

xy|z
-------
00|1
01|0
10|0
11|0
Q5. What is race condition? How do we avoid that?
Ans-
Race conditions occasionally occur in logic gates when certain inputs
come into conflict. Because the gate output state takes a finite,
nonzero amount of time to react to any change in input states,
sensitive circuits or devices following the gate may be fooled by the
state of the output, and thereby caused to not operate properly.
A race condition is an undesirable situation that occurs when a device
or system attempts to perform two or more operations at the same
time, but because of the nature of the device or system, the
operations must be done in the proper sequence in order to be done
correctly.
In computer memory or storage, a race condition may occur if
commands to read and write a large amount of data are received at
almost the same instant, and the machine attempts to overwrite some
or all of the old data while that old data is still being read.
WE CAN REMOVE THIS PROBLEM BY USING MASTER SLAVE J-
K FLIP FLOP
In JK flipflop if both the inputs are high,then the output q and
qbar toggles for each clock .to rectify it keep clock duration less
than the propagation delay
Q6. Minimize the following Using K-Map and realize it with NAND
Gates:
F (A, B, C, D) = Ʃm (2, 3, 4, 5, 13, 15) + Ʃd (8, 9, 10, 11)
Ans-
Ʃm (2, 3, 4, 5, 13, 15)
2-0010
3-0011
4-0100
5-0101
13-1101
15-1111
Y=_ _ _ _ _        _ __ _ _            _
A BCD+A BCD+AB CD+ABCD +ABCD+ABCD

_ _          _                           _
C D          C D          C D          C D
_   _                                 1            1
A   B
_           1            1
A   B
A   B                    1            1

_
AB

Ans- _ _ _ _          _
F= AB C +A B C+ABD+BC D

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