Counters and Shift Registers

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Chapter 9 – Part A                                    Types
                                                      Design of State Table
Counters and Shift Registers                        Shift Registers
                                                      SR Based Counters


Counters and Shift Registers                       Counter Terminology – 1
 Counter: A Sequential Circuit that counts          A Counter is a digital circuit whose
 pulses. Used for Event Counting, Frequency         outputs progress in a predictable
 Division, Timing, and Control Operations.          repeating pattern. It advances on state
 Shift Register: A Sequential Circuit that          for each clock pulse.
 moves stored data bits in a specific direction.
 Used in Serial Data Transfers, SIPO/PISO           State Diagram: A graphical diagram
 Conversions, Arithmetic, and Delays.               showing the progression of states in a
                                                    sequential circuit such as a counter.

                                              3                                               4

Counter Terminology – 2                            Counter Modulus
 Count Sequence: The specific series of output      Modulus of a counter is the number of states
 states through which a counter progresses.         through which a counter progresses.
 Modulus: The number of states a counter            A Mod-12 UP Counter counts 12 states from
 sequences through before repeating (mod-n).        0000 (010) to 1011 (1110). The process then
 Counter directions:                                repeats.
   UP - count high to low (MSB to LSB)              A Mod-12 DOWN counter counts from 1011
   DOWN - count low to high (LSB to MSB).           (1110) to 0000 (010), then repeats.

                                              5                                               6

                                              MOD 12 Counter State
State Diagram                                 Diagram
 A diagram that shows the progressive          With each clock pulse the counter
 states of a sequential circuit.               progresses by one state from its
 The progression from one state to the         present position on the state diagram to
 next state is shown by an arrow.              the next state in the sequence.
   (0000 ⇒ 0001⇒ 0010).
                                               This close system of counting and
 Each state progression is caused by a         adding is known as modulo arithmetic.
 pulse on the clock to the sequential

                                         7                                           8

MOD 12 Counter State
Diagram                                       Truncated Counters – 1
                                               An n-bit counter that counts the
                                               maximum modulus (2n) is called a full-
                                               sequence counter such as Mod 2, Mod
                                               4, Mod 8, etc.
                                               An n-bit counter whose modulus is less
                                               than the maximum possible is called a
                                               truncated sequence counter, such as
                                               mod 3 (n = 2), mod 12 (n = 4).
                                         9                                          10

Truncated Counters – 2                        Truncated Counters – 3
 A 4-bit mod 12 UP counter that counts
 from 0000 to 1011 is an example of a
 truncated counter.
 A 4-bit mod 16 UP counter that counts
 up from 0000 to 1111 is an example of
 a full-sequence counter.

                                         11                                         12

Counter Timing Diagrams – 1                Counter Timing Diagrams – 2
 Shows the timing relationships between     The outputs (Q0 ⇒ Q3) of the counter
 the input clock and the outputs Q3, Q2,    can be used as frequency dividers with
 Q1, …Qn of a counter.                      Q0 = clock ÷ 2, Q1 = clock ÷ 4, Q2 =
                                            clock ÷ 8, and Q3 = clock ÷ 16.
 For a 4-bit mod 16 counter, the output
                                            The frequency is based on T of the
 Q0 changes for every clock pulse, Q1       output, not a transition on the output.
 changes on every two clock pulses, Q2
                                            The same is true for a mod 12, except
 on four, and Q3 on 8 clocks.               Q3 = clock ÷ 12.

                                      13                                         14

Counter Timing Diagrams – 3                Counter Timing Diagrams – 4

                                      15                                         16

Synchronous Counters                       Synchronous Counters
 A counter whose flip-flops are all
 clocked by the same source and change
 state in synchronization.
 The memory section keeps track of the
 present state.
 The control section directs the counter
 to the next state using command and
 status lines.

                                      17                                         18

Analysis of Synchronous                                   Analysis of Synchronous
Counters – 1                                              Counters – 2
  Set equations for the (JK, D, T) inputs in                   Determine the result on each FF in the
  terms of the Q outputs for the counter.                      counter and place this in the next state.
  Set up a table similar to the one in Table 9.5
                                                               Enter the next state on the present
  and place the first initial state in the present
  state column (usually all 000).
                                                               state line 2 and repeat the process until
                                                               you cycle back to the first initial state.
  Use the initial state to fill in the Inputs that
  will cause this state on a clock pulse.

                                                19                                                                  20

Analysis of Synchronous
Counters – 3                                              State Table For Figure 9.11

                                                     Present State           Synchronous Inputs            Next State
                                                        Q2Q1Q0        J2K2         J1K1           J0K0     Q2Q1Q0
                                                         000         01   (R)    00   (NC)      11   (T)      001
                                                         001         01   (R)    11       (T)   11   (T)      010
                                                         010         01   (R)    00   (NC)      11   (T)      011
                                                         011         11   (T)    11       (T)   11   (T)      100
                                                         100         01   (R)    00   (NC)      01   (R)      000

                                                21                                                                  22

Basic Design Approach – 1                                 Basic Design Approach – 2
                                                               Use FF Excitation Tables to determine
                                                               FF (JK, D, T) inputs for each present ⇒
Draw a state diagram showing state                             next state transition.
changes and inputs and outputs.
                                                               Specify inputs equations for each input
Create a present/next state table.                             and simplify using Boolean reductions.
List present states in binary order and                        A VHDL design for counters is done
next states based on the state diagram.                        more easily and is not as time

                                                23                                                                  24

Basic Design Approach – 3                                 VHDL Process Statements
  The previous two slides describe the                       Sequential counters use a process
  process for designing counters by                          statement to control transitions to the
  deriving and simplifying Boolean                           next count state.
  equations for a counter (classical                         A VHDL Attribute is used with an
  approach).                                                 identifier (signal) to define clock edges.
  VHDL design for counters is done more                      Clock uses an attribute called EVENT
                                                             such as (clk’EVENT AND clk=‘1) to
  easily and is not as time consuming.                       define a rising edge clock event.

                                                     25                                                     26

VHDL UP Counter                                           VHDL UP Counter Entity
    -- simple_int_counter.vhd                                 ENTITY simple_int_counter IS
    -- 8-bit synchronous counter with asynchronous                PORT(
                                                                         clock : IN STD_LOGIC;
    -- Uses INTEGER type for counter output.
                                                                         reset : IN STD_LOGIC;
    LIBRARY ieee;
                                                                         q     : OUT INTEGER RANGE 0 TO 255);
    USE ieee.std_logic_1164.ALL;
                                                              END simple_int_counter;

                                                     27                                                     28

VHDL UP Counter Architecture                              VHDL UP Counter Architecture
–1                                                        –2
ARCHITECTURE counter OF simple_int_counter IS
                                                                   IF (clock’ EVENT AND clock = ‘1’) THEN
                                                                         count := count +1;
    PROCESS (clock, reset)
                                                                   END IF;
        VARIABLE count : INTEGER RANGE 0 to 255;
                                                                 END IF;
        BEGIN                                                    q <= count;
        IF (reset = ‘0’) THEN                                END PROCESS;
         COUNT : = 0;                                     END counter;

                                                     29                                                     30

 VHDL UP Counter Summary                                       LPM Counters – 1
   PROCESS statement monitors the two                             The Altera LPM (Library of
   inputs clock and reset, which controls                         Parameterized Modules) counter can be
   the state of the counter.                                      used to create counter designs in VHDL.
   A variable count holds the present                             This is a structured design approach
   value of the counter.                                          that uses the LPM-counter as a
   The IF statement evaluates the clock                           component in a hierarchy.
   and reset inputs to determine whether                          The LPM counter is instantiated in the
   the counter should increment or clear.                         structured design.

                                                    31                                                                  32

 LPM Counters – 2                                              VHDL LPM Library Declaration
                                                                  The Altera LPM Library must be added
The basic parameters of the LPM                                   to the usual STD_LOGIC after the ieee
counter, such as width, are defined with                          library has been declared
a generic map.
The port map is used to connect LPM                                   LIBRARY ieee;
counter I/O to the actual VHDL design                                 USE ieee.std_logic_1164.ALL;
entity.                                                               LIBRARY lpm;
                                                                      USE lpm.lpm_components.ALL;

                                                    33                                                                  34

 VHDL LPM Entity                                               VHDL LPM Architecture
   Entity for an 8-bit mod 256 counter.                  ARCHITECTURE count OF simple_lpm_counter IS
   LPM requires the use of STD_LOGIC                       SIGNAL clrn : STD_LOGIC;--internal signal for active low clr.
   data types.                                           -- Instantiate 8-bit counter.
                                                           count : lpm_counter
ENTITY simple_lpm_counter IS                                 GENERIC MAP (LPM_WIDTH => 8)
   PORT(                                                     PORT MAP ( clock => clk,
                                                                          aclr => clrn,--Intrnal clear mapped to async. clr.
        clk, clear : IN STD_LOGIC;
                                                                          q     => q_out (7 downto 0 ));
        q        : OUT STD_LOGIC_VECTOR (7 downto 0));       clrn <= not clear;--Input port inverted mapped to internal clr.
END simple_lpm_counter;                                  END count;

                                                    35                                                                  36

Entering Simple LPM Counters                Entering Simple LPM Counters
in Quartus II                               in Quartus II
 Use either the MegaWizard Plug in
 Manager or manually enter the LPM
 Refer to Chapter 9, Entering Simple
 LPM Counters with the Quartus II Block

                                      37                                             38

Entering Simple LPM Counters
in Quartus II                               LPM Counter Features – 1
                                             Parallel Load: A function (syn/asyn) that
                                             allows loading of a binary value into the
                                             counter FF.
                                             Clear: asynchronous or synchronous
                                             Preset: A set (syn. Or asyn.).

                                      39                                             40

LPM Counter Features – 2                    LPM Counter Features – 3
 Counter Enable: A control function that     There are other features for LPM
 allows a counter to count the sequences     counters that are given in the Altera
 or disable the count.                       Reference Data Sheets.
 Bi-Directional: A control line to switch    The same holds true for other LPM
 the counter from a count up to a count      functions, such as arithmetic and
 down.                                       memory.

                                      41                                             42

4-Bit Parallel Load Counter – 1              4-Bit Parallel Load Counter – 2
 A preset counter (parallel load) has an      An asynchronous load counter uses an
 additional input (load) that can be          asynchronous clear or preset to force
 synchronous or asynchronous and four         the counter to a known state (usually
 parallel data inputs.                        0000 or 1111).
 The load pulse selects whether the
 synchronous counter inputs are
 generated by count logic or parallel load
                                       43                                         44

4-Bit Parallel Load Counter – 3              4-Bit Parallel Load Counter – 4

                                       45                                         46

4-Bit Parallel Load Counter – 5              4-Bit Parallel Load Counter – 6

                                       47                                         48

Count Enable Logic                          Bi-Directional Counter
 As shown in Figure 9.46, adding             Adds a direction Input (DIR) to the
 another AND gate to each FF input           counter and the control logic for up or
 inhibits the count function.                down counting.
 This has the effect of inhibiting the       Basic counter element is shown in
 clock to the counter (a clock pulse has     Figure 9.50.
 no effect).                                 The control logic selects the up or down
 Outputs remain at the last state until      count logic depending on the state of
 the counter is enabled again.               DIR.

                                       49                                         50

Terminal Count Decoding – 1                 Terminal Count Decoding – 2
 Uses a combinational decoder to detect
 when the last state of a counter is
 reached (terminal count).
 Determines a maximum count out for
 an UP counter and a minimum for a
 DOWN counter.

                                       51                                         52

Terminal Count Decoding – 3                 Terminal Count Decoding – 2
                                             The terminal count decoder generates a
                                             RCO (ripple carry out) when the
                                             terminal count is reached (a high pulse
                                             for 1 clock period).

                                       53                                         54

       Terminal Count Decoding – 3                                        VHDL Counter (8-Bit) – 1
                                                                            -- Pre-settable_8bit_counter_sync_load
                                                                            -- 8-bit pre-settable counter with
                                                                            -- clear and load and terminal count
                                                                            -- using STD_LOGIC types

                                                                            LIBRARY ieee;
                                                                            USE ieee.std_logic_1164.ALL;
                                                                            USE ieee.std_logic_unsigned.ALL;

                                                           55                                                                     56

       VHDL Counter (8-Bit) – 2                                           VHDL Counter (8-Bit) – 3
ENTITY presettable_8bit_counter_sync_load IS
                                                                  ARCHITECTURE a OF presettable_8bit_counter_sync_load IS
  PORT(                                                                SIGNAL terminal_count : STD_LOGIC_VECTOR (8 downto 0);
   clk, count_ena         : IN STD_LOGIC;
                                                                    PROCESS (clk) -- Since all functions are synchronous only clk is on
   clear, load, direction : IN STD_LOGIC;
                                                                                  -- the sensitivity list.
   p                      : IN STD_LOGIC_VECTOR (7 downto 0);
   max_min                 :OUT STD_LOGIC;                               IF (CLK’EVENT AND clk = ‘1’) THEN
   q                   : BUFFER STD_LOGIC_VECTOR (7 downto 0));            IF (clear = ‘0’) THEN -- Synchronous clear.
                                                                               q <= (others => ‘0’);
END presettable_8bit_counter_sync_load;                                    ELSIF (load = ‘1’) THEN – Synchronous load.
                                                                               q <= p;
                                                           57                                                                     58

       VHDL Counter (8-Bit) – 3                                           Terminal Count Code

        ELSIF (count_ena = ‘1’ and direction = ‘0’) THEN
                                                                          -- Terminal count decoder (combinational)
           q <= q –1;
                                                                          Terminal_count <= direction & q;
        ELSIF (count_ena = ‘1’ and direction = ‘1’) THEN
                                                                             WITH terminal_count SELECT
           q <= q+1;
                                                                                  max_min <= ‘1’ WHEN “000000000”,
        END IF;
                                                                                              ‘1’ WHEN “111111111”,
      END IF;
                                                                                              ‘0’ WHEN others;

                                                           59                                                                     60

      8-Bit Counter Summary – 1                                               8-Bit Counter Summary – 2
                                                                                 q increments if there is a positive clk
                                                                                 edge, count_ena = 1, and direction =
      After the PROCESS statement.                                               1).
      q = 0 (if clear = 0).                                                      q decrements if there is a positive clk
      q = p (if clear = 0 and load = 1).                                         edge, count_ena = 1, and direction =
                                                                                 q remains the same if above conditions
                                                                                 are not met.

                                                                 61                                                                62

      8-Bit Counter Summary – 3                                               LPM Counter Functions
                                                                                 LPM counters can be used as a simple
                                                                                 8-bit counter.
                                                                                 The component lpm_counter has a
                                                                                 number of other functions that can be
                                                                                 implemented using specific ports and
                                                                                 parameters. These functions are
                                                                                 indicated on Table 9.12.

                                                                 63                                                                64

      LPM Counter VHDL Code – 1                                               LPM Counter VHDL Code – 2
-- pre_lpm8
                                                                      ENTITY pre_lpm8 IS
-- 8-bit presettable counter with asynchronous clear and load,            PORT(
-- count enable, and a directional control port.                            clk, count_ena               : IN STD_LOGIC;
                                                                            clear, load, direction : IN STD_LOGIC;
LIBRARY ieee;                                                               p                      : IN STD_LOGIC_VECTOR (7 downto 0);
USE ieee.std_logic_1164.ALL;                                                q_out                  : IN STD_LOGIC_VECTOR (7 downto 0));
                                                                      END PRE_LPM8;
USE lpm.lpm_components.ALL;

                                                                 65                                                                66

   LPM Counter VHDL Code – 3                     Homework
ARCHITECTURE a OF pre_lpm8 IS                     Chapter 9
 BEGIN                                              4, 6 (Modulus)
    counter 1: lpm_counter
        GENERIC MAP (LPM_WIDTH => 8)                12 (Synchronous Counter)
        PORT MAP (clock => clk,                     20 (T Flip-flop Synchronous Counter)
                  updown => direction,
                  cnt_en => count_ena,              22 (VHDL for 6-Bit Counter)
                  data     => p,
                                                    32 (Down Counter)
                  aload => load,
                  aclr     => clear,                39 (Generic Width Counter)
                  q       => q_out;
END a;
                                            67                                             68

   ACLU #17
      A counter is to count the Gray code
      pattern “000”     “001”    “011”
      “010”    “110”     “111”    “101”
      “100”    “000”     etc.
      The inputs are Clk, ClkEn, and the
      counter outputs are Gray, and Cout.
      Write the entity statement
      Complete the Architecture



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