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Counters (PowerPoint)

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					Digital Electronics
  Electronics Technology

     Landon Johnson

          Counters
         Counter Competencies
29. Given the schematic diagram of a counter circuit, the student
will determine if this counter is synchronous or asynchronous.


30. Given a schematic of an asynchronous counter, the
student will identify the LSB flip-flop.


31. Given a schematic of a synchronous counter, the
student will identify the LSB flip-flop.


32. Given the schematic of a counter and the value currently
on the counter, the student will determine the new counter
value if an instructor specified number of pulses are applied
to the counter
         Counter Competencies
33. Given a modulus number from 16 to 32, the student will draw
a schematic of flip-flops and NAND gates that will count this
modulus starting with zero.


34. Given the schematic diagram of a synchronous counter
circuit, the student will determine the modulus of the counter.


35. Given the schematic diagram of a synchronous counter
circuit, the student will determine the counting sequence
and list the sequence in decimal.

36. Given the schematic diagram of a counter and the clock input
frequency, the student will determine the output frequency of
the counter.
        COUNTER UNIT

•   Asynchronous up and down counters
•   Asynchronous modulus counters
•   Seven segment displays/ BCD coding
•   Synchronous Counters
•   Pre-settable Counters
•   Ring Counters
COUNTERS CHARACTERISTICS

 1. MODULUS- number of counts in one cycle

 2. Up or down count

 3. Asynchronous or synchronous operation

 4. Free running or self stopping
   ASYNCHRONOUS COUNTERS
•Only LSB flip-flop controlled by the clock input

•Also known as a RIPPLE COUNTER

•Two or more “T” flip-flops interconnected, output
 of each flip-flop connected to clock input of the next.

•Modulus- number of stable states in each flip-flop cycle
                 N
•Modulus =   2       N= number of flip-flops
                                    N 1
•Highest number in count =      2
BUILD A 4 BIT RIPPLE COUNTER
   1. 4 JK flip-flops in toggle mode- all JK inputs tied high

   2. Q outputs connected to clock input of following flip-flop

   3. FF A = LSB (one with clock input); toggles when input clock
      toggles from high to low; FF D = MSB
   4. FF B, C, D do not toggle till receive NGT from proceeding FF

   5. Direction of count can be reversed by complementing
   each FF’s output or complementing each FF’s input

      D                 C                 B                 A

          D     J   1       C     J   1       B     J   1       A     J   1
              CLK               CLK               CLK               CLK
          D     K   1       C     K   1       B     K   1       A     K   1
                              TEST
1. What is the term for the number of counts in one counter cycle?
   Modulus of the counter

2. How is the modulus determined?
   2 N N  number of flip  flops
3. Since only the first flip-flop of a ripple counter is controlled by a clock,
   the counter is ____________________?
    Asynchronous
4. What is the mod number of a counter containing 5 flip-flops?
   32
5. What is the highest count of a four bit counter?
   31
PROGRAMMING A RIPPLE COUNTER
         •Counters may be made to recycle after any desired count
         by using a gate to reset the counter.


          CONVERT MOD 8 TO MOD6
                                                                   INPUT CLK
     C                     B                 A
                                                                               C   B   A
                                                                       0       0   0   0
          C       J    1       B     J   1       A         J   1       1       0   0   1
              CLK                  CLK                   CLK           2       0   1   0
                                         1                     1       3       0   1   1
          C       K    1       B     K           A         K
                                                                       4       1   0   0
                                                                       5       1   0   1
                                                                                           UNSTABLE
                                                                       6       1   1   0
              B                                                                             STATE
                      master                                           7
                      reset
              C




3 FLIP FLOPS
2  MOD 8
 3




HIGHEST COUNT  2  1  7                            3
HOW TO BUILD A COUNTER TO GO
FROM ZERO TO MOD NUMBER X
  1. Determine smallest number of FF’s such that   2 X
                                                   N



   IF 2  X , SKIP STEPS 2 AND 3
         N




  2. Connect a NAND gate output to asynchronous clears of all FF’s



  3. Determine which FF’s will be high at count = X
     Connect the Q outputs of these FF’s to NAND gate inputs
BUILD A COUNTER THAT COUNTS
FROM ZERO TO NINE (X=MOD 10)
 1. Determine smallest number of FF’s such that                   2 XN



   2  8 and 2  16
    3                 4
                                    thus 4 FF’s are required
 2. Connect a NAND gate to asynchronous clears of all FF’s

 3. Determine which FF’s will be high at count = X
    Connect the Q outputs of these FF’s to NAND gate inputs
      1            0           1             0
        D                 C                 B                 A

            D     J   1       C     J   1       B     J   1       A       J   1
                CLK               CLK               CLK               CLK
            D     K   1       C     K   1       B     K   1       A       K   1
      SELF-STOPPING COUNTER

•Counters may be made to stop counting after any desired count
by using a gate to inhibit the clock.

•Stop at desired count:
                             Stop at 1010  1010 2


  1                 0                 1                 0

      D     J   1       C     J   1       B     J   1       A     J   1
          CLK               CLK               CLK               CLK
      D     K   1       C     K   1       B     K   1       A     K   1

                                                D
                                                C
                                                B
                                                A
    PROGRAMMING COUNTERS
       USING JK INPUTS
•Counters can be controlled using the JK inputs

•Low on JK of 1st FF will cause it to stop toggling on any count

•High or low at JK inputs forces counter to skip states


      1                 1                 0                 0

          D     J   1       C     J   1       B     J   1       A     J
              CLK               CLK               CLK               CLK
          D     K   1       C     K   1       B     K   1       A     K


                                                   C

                                                   D
ASYNCHRONOUS DOWN COUNTER
          •Direction of count can be reversed by
             (a) complementing each FF’s output or
             (b) complementing each FF’s input


      D             C             B             A
          CLK           CLK           CLK           CLK
      D             C             B             A



  D             C             B             A


      D             C             B             A
          CLK           CLK           CLK           CLK
      D             C             B             A
             COUNTER PROBLEM
1. What is the value of the last usable state before the NAND gate
resets the circuitry? 11012  1310
2. What value does the NAND gate reset the value to? 1000 2  810
3. What is the modulus of this counter?    6
4. If count starts at decimal 11 and receives seven clock pulses, what
is the new value on the counter? 1210
5. What is the unstable state of the counter? 1110 2  1410
                        A            B            C             D




       0V         S            S            S             S
                J   Q        J   Q        J   Q         J   Q
                CP           CP           CP            CP
                K QN         K QN         K QN          K QN
                  R            R            R             R
               COUNTER PROBLEM
1. What is the value of the unstable state, in decimal? 1112  710
2. At what value does the NAND gate set the counter to? 0112  310
3. If QA=1, QB=1, and QC=0, and 5 clock pulses are applied:
    QC= 1         QB= 0          QA= 0
4. What is the modulus of this counter? 4
                             1                2                4
                             A                B                C


                 +V              +V               +V
                       S                S                S
          0V         J   Q            J   Q            J   Q
                     CP               CP               CP
                     K QN             K QN             K QN
                  +V   R                R                R
IC ASYNCHRONOUS COUNTERS
                Logic Diagram for 7493

  ___   J   Q           J   Q          J   Q              J   Q
  CPo   CP              CP             CP                 CP
        K QN            K QN           K QN               K QN
          R               R              R                  R
  ___
  CP1
                Qo              Q1                   Q2           Q3
  MR1           (LSB)           *All J, K inputs internally       (MSB)
  MR2                           connected HIGH


                                                           ___
                                                           CP1
                               7493
                                                           ___
                                                           CPo



                                 Q3   Q2   Q1   Qo
                   MR 1 MR 2
7493 AS A MOD-16 COUNTER
                        Logic Diagram for 7493

    ___         J   Q           J   Q          J   Q           J   Q
    CPo         CP              CP             CP              CP
                K QN            K QN           K QN            K QN
                  R               R              R               R
    ___
    CP1
                        Qo              Q1               Q2            Q3
   MR1                  (LSB)           *All J, K inputs internally    (MSB)
   MR2                                  connected HIGH



                                                                           ___
                                                                           CP1
                                7493                                             10 kHz
                                                                           ___
                                                                           CPo

                                                        Qo
         MR 1             MR 2 Q3       Q2       Q1



                                                                 F= 10 kHz/16 = 625 Hz
                          TEST
Build a MOD 10 counter with a 7493
         Logic Diagram for 7493

 ___     J   Q           J   Q          J   Q           J   Q
 CPo     CP              CP             CP              CP
         K QN            K QN           K QN            K QN
           R               R              R               R
 ___
 CP1
                 Qo              Q1               Q2            Q3
 MR1             (LSB)           *All J, K inputs internally    (MSB)
MR2                              connected HIGH



                                                                    ___
                                                                    CP1
                          7493                                            10 kHz
                                                                    ___
                                                                    CPo

                                                  Qo
       MR 1          MR 2 Q3       Q2      Q1



                                                                   F= 10 kHz/10 = 1KHz
                        BCD COUNTER
•Binary counter that counts from 0000 to 1001 before it recycles (MOD-10).

•Widespread applications where pulses or events are to be counted
and the results displayed on a decimal numerical read-out.

•Also used for dividing a pulse frequency exactly by 10.

      Hundreds                     Tens                    Units

           BCD                     BCD                     BCD             Input
          counter                 counter                 counter

      D     C   B   A         D     C     B   A       D     C      B   A

    Decoder/display         Decoder/display         Decoder/display
         0-9                     0-9                     0-9



   Cascading BCD counters to count and display from 000 to 999.
           MOD-60 COUNTER

       MOD 6                                   MOD 10


                             ___                                   ___
                             CP1                                   CP1
    7493                                     7493
                             ___                                   ___
                             CPo                                   CPo
                                                                         fin
                     Qo                                       Qo
 MR 2 Q3   Q2   Q1                 MR 1   MR 2 Q3   Q2   Q1
                       not
                      used




fout = fin/60                       fin/10

Two 7493s can be combined to produce a MOD-60 Counter
DIGITAL CLOCK
          COUNTERS
          ASYNCHRONOUS

 S                 S               S               S
J   Q         J   Q            J   Q           J   Q
CP            CP               CP              CP
K QN          K QN             K QN            K QN
  R             R                R               R



              SYNCHRONOUS

      S            S           S           S
  D       Q    D       Q   D       Q   D       Q
  CP QN        CP QN       CP QN       CP QN
    R            R           R           R
SYNCHRONOUS COUNTERS
•Two or more FF’s connected as “T” FF’s.

•All FF’s in the counter are clocked at the same time.

•Advantage over the ripple counter is speed and accuracy but more complex.



5V                                                                     5V
                                                                       +V

                S                S                 S              S
            Q    J           Q    J            Q    J         Q    J
                CP               CP                CP             CP
            QN K             QN K              QN K           QN K
              R                R                 R              R
5V
                                                                            0V




        D                C                 B              A
SYNCHRONOUS COUNTERS
       MOD <2
              N


•A NAND control gate is used to clear the counter before the full count.


                                                                  5V
                                                                  +V


                         S              S                  S
         S           Q    J         Q    J             Q    J
     Q    J              CP             CP                 CP
         CP          QN K           QN K               QN K
     QN K                                                R
                       R              R
       R
                                                                   0V



         D               C                  B              A
SYNCHRONOUS COUNTERS
      UP/DOWN
                       0V



                                 5V

     Q    J             Q    J        0V
              Q    J
         CP       CP        CP
     QN K     QN K      QN K
       R        R         R
5V




                        5V
PRESETTABLE COUNTERS
  Can be preset to any desired count. To operate:
      1. Apply desired count to parallel data inputs P2, P1, P0.
      2. Apply a low pulse to the parallel load input PL.
               P2               P1              Po           PA RALLEL
                                                             DA TA INPUTS




                                                                5V
                                                                +V
                        S                S               S
                    Q    J           Q    J          Q    J
                        CP               CP              CP
                    QN K             QN K            QN K
                      R                R               R
                                                                       5V


                                                                     CLOCK
 PA RALLEL
  LOA D
 __
 PL
           COUNTER TYPES
Asynchronous Counter (a.k.a. Ripple or Serial Counter):
each FF is triggered one at a time with output of one FF serving as clock
input of next FF in the chain.
Synchronous Counter (a.k.a. Parallel Counter): all the FF’s in the
counter are clocked at the same time.
Up Counter: counter counts from zero to a maximum count.
Down Counter: counter counts from a maximum count down to zero.
BCD Counter: counter counts from 0000 to 1001 before it recycles.

Pre-settable Counter: counter that can be preset to any starting count
either synchronously or asynchronously

Ring Counter: shift register in which the output of the last FF is
connected back to the input of the first FF.

Johnson Counter: shift register in which the inverted output of the last
FF is connected to the input of the first FF.
       74193 COUNTER
MOD-16 PRESETTABLE UP/DOWN COUNTER
                 RING COUNTER
Shift register counter with feedback from Q of last FF back to first FF input
                             RING COUNTER


     5V


                     S             S           S              S
                 D       Q     D       Q   D       Q      D       Q
                 CP QN         CP QN       CP QN          CP QN
            5V     R             R           R              R


           0V


          clk
            JOHNSON COUNTER
Shift register in which the inverted output of the last FF is fed back to the input
of the first FF.




5V


                S               S               S                 S
            D       Q       D       Q       D       Q         D       Q
            CP QN           CP QN           CP QN             CP QN
       0V     R               R               R                 R


      0V


     clk
Lab 18.

A PROGRAMMABLE COUNTER
 Design a four-bit counter controlled by two control lines X and Y
 that behaves according to the truth table.



               PROGRAM                   COUNTER
                 SWITCH                   MODE
               X        Y
               0        0               NO COUNT
               0        1                MOD 5
               1        0                MOD 10
               1        1                MOD 12
Lab 18.

A PROGRAMMABLE COUNTER
   5V
                                                                        Q1 CP1
                                                                        Q2 CP2


                  S                      S            S            S
              Q    J                 Q    J       Q    J       Q    J
          D       CP                     CP           CP           CP
              QN K            C      QN K     B   QN K     A   QN K
                R                      R            R            R



                            _
                            XY AC


                             _
                            XY BD



                             XY CD


                                                                                 X
  1       1             21 DOM
  1       0             01 DOM
  0       1             5 DOM                                                    Y
  0       0            TNUOC ON
  X       Y
   HCTI WS              EDOM
  MARGORP              RETNUOC
              RIPPLE COUNTER
                                            Binary Output
Clock Input
                                              1111
                                              0000

       8
       7
       6
       5
       4
       3
       2
 Pulse 1




                  PS and next clock pulse states and
                    On 4-bit counter All J-K flip-flops
                  This theCLR input has 16(8) all FFs
                                            in the
               will count are because each will receive
                          from
                  will toggle binary 0000 through 1111
                       INACTIVE
                    a H-to-L pulse- one TOGGLE MODE
                                        after 0000.
                       and then reset back to another.
                    The counter ripple thru the counter.
               Watch the counthas a modulus of 16.
RIPPLE COUNTER WITH WAVEFORMS
                 Binary Output
 Clock Input
                   100
                  0011

        5
        4
        3
        2
  Pulse 1




                                      Clock input


                    FFs triggered on 1s output
                       H-to-L pulse.
                    CLK toggles 1s FF.
                    1s FF toggles 2s FF.2s output
                    2s FF toggles 4s FF.

                                       4s output
               DECADE COUNTER
                                           Binary Output
 Clock Input
                                            1000
                                            0111

        8
        7
        6
        5
        4
        3
        2
  Pulse 1
                                                       Short negative pulse

                                                                   To clear input
                                                                    of each FF



All J & K inputs = 1
 All PR inputs = 1


                    To change mod-16 counter to decade counter:
                                   Count is at 1001.
                      Reset count to 0000 after 1001 (9) count.
                     Next clock pulse will increment counter for a
                         When count hits 1010 reset to 0000.
                 short time to 1010 which will activate the NAND gate
                     See added 2-input NAND gate that clears all
                             and reset the counter to 0000.
                          JK FFs to 0 when count hits 1010.
             DOWN COUNTER

                                            000
                                            111



      4
      2
Pulse 1
      5
      3




              Changes from Ripple Up Counter are
          wiring from Q’ outputs (instead of Q outputs)
                 to the CLK input of the next FF.
 SELF-STOPPING DOWN COUNTER


                                                                     The count remained
                                                     111
                                                     000               at binary 000.



           2
           4
           3
           6
           5
           8
     Pulse 1
           7




                               This is a 3-bit down counter.
                The 1s FF is in TOGGLE mode when counting (J & K = 1).
The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate
               when the count decrements to 000. The count stops at 000.
COUNTER USED FOR FREQUENCY DIVISION

                                              4
                           8        200 Hz

                            100 Hz            400 Hz
                  50 Hz                            2
                     16

    Clock Input



     800 Hz
USING THE 7493 COUNTER IC
          • Counters are available in IC form.
          • Either ripple (7493 IC) or synchronous
            (74192 IC) counters are available.

                                 ? Hz
                                400 Hz
                   ? Hz
                  100 Hz                     ? Hz
                                            800 Hz



1600 Hz


                                                     7493 Counter IC
                                                     wired as a 4-bit
                                                     binary counter
MAGNITUDE COMPARATOR
A magnitude comparator is a combinational logic device
that compares the value of two binary numbers and
responds with one of three outputs (A=B or A>B or A<B).


                        A(0)
                        A(1)     74HC85
  Input binary 0111
   Input binary 1111
    Input binary 0001
                        A(2)
                               Magnitude
                               Comparator
                        A(3)
                                       A>B   HIGH
                        B(0)
                                       A=B   HIGH
                        B(1)
               0111
  Input binary 0110
   Input binary 1100                   A<B   HIGH
                        B(2)

                        B(3)
TROUBLESHOOTING EQUIPMENT

  •   Logic Probe
  •   Logic Pulser
  •   Logic Clip (logic monitor)
  •   Digital IC Tester
  •   DMM/Logic Probe
  •   DMM or VOM
  •   Dual-trace Oscilloscope
  •   Logic Analyzer
SIMPLE TROUBLESHOOTING HINTS

 • Feel top of IC to determine if it is hot
 • Look for broken connections, signs of
   excessive heat
 • Smell for overheating
 • Check power source
 • Trace path of logic through circuit
 • Know the normal operation of the circuit

				
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