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How to Efﬁciently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K Anirudh Devgan Hao Ji Wayne Dai IBM Microelectronics UC Santa Cruz CE Dept. UC Santa Cruz CE Dept. Austin, TX 78758 Santa Cruz, CA 95064 Santa Cruz, CA 95064 devgan@us.ibm.com hji@cse.ucsc.edu dai@cse.ucsc.edu Abstract veloped the algorithm, FastHenry [5], to solve for effective On-chip inductance extraction and analysis is becom- inductance from partial inductances with multi-pole accel- ing increasing critical. Inductance extraction can be difﬁ- eration. cult, cumbersome and impractical on large designs as in- Nonetheless, the partial inductance approach, which as- ductance depends on the current return path — which is signs portions of the loop inductances to segments along typically unknown prior to extracting and simulating the the loop, results in a large, densely-coupled network repre- circuit model. In this paper, we propose a new circuit ele- sentation, which makes subsequent circuit simulation prac- ment, K , to model inductance effects, at the same time be- tical only for small examples. Moreover, unlike capaci- ing easier to extract and analyze. K is deﬁned as inverse of tance matrices which can be truncated to represent only partial inductance matrix L, and has locality and sparsity localized couplings, simply discarding distant mutual in- normally associated with a capacitance matrix. We pro- ductances can result in an unstable equivalent circuit model pose to capture inductance effects by directly extracting (positive poles) [6]. and simulating K , instead of partial inductance, leading As an alternative to simple truncation, a shift-truncate to much more efﬁcient procedure which is amenable to full potential method was proposed by Krauter, et al [7, 6]. chip extraction. This proposed approach has been veriﬁed This shift-truncate potential method assumes that segment through several simulation results. currents return at a ﬁnite radius r0 , instead of inﬁnity. Therefore, segments spaced more than r0 apart have no in- ductive coupling. This technique can guarantee to generate 1 Introduction positive deﬁnite sparse approximations of the original par- tial inductance matrix. Nevertheless, to determine a proper Increasing clock speeds, die sizes, and power dissipations value of r0 to ensure a desired accuracy involves com- have driven VLSI manufacturers to abandon the simple plicated schemes and iterations. Moreover, this approach scaling approach of interconnect wiring. Instead, they em- does not work well for long wires. Shepard, et al proposed ploy a hierarchy of metal wiring levels. Thinner wiring the concept of “return-limited loop inductance” to sparsify levels are used at the circuit level where density is re- the partial inductance matrix [8]. It is based on the assump- quired, and thicker layers at the top or global levels in or- tion that the currents of signal lines return within the re- der to route low-skew clock trees, low-loss power distribu- gion enclosed by the nearest same-direction power-ground tion buses, and the fastest signal interconnects. This trend, lines. However, this may not be true when power-ground coupled with the recent introduction of copper wiring (be- lines are of same order of dimensions as signal lines. Re- cause its resistivity is approximately half that of aluminum cently, Lin developed the 2x mutual inductance screening wiring) has made on-chip inductance modeling necessary rule [9]. Since this rule basically discards the consideration for clocks and the fastest signal interconnects. of circuit topology, it cannot be applied to some complex Inductance extraction is difﬁcult because mutual induc- interconnect topology, such as mesh ground plane [6]. tance depends on the current return path — which is un- Thus, unlike capacitance extraction, where only the known prior to extracting and simulating a circuit model. nearest neighbor conductors need to be considered, in in- Rosa introduced the concept of partial inductances to avoid ductance extraction, a large number of conductors are in- this difﬁculty by assuming that each segment has a return volved. Techniques used in capacitance extraction, such current at inﬁnity [2]. Ruehli introduced partial inductance as library construction and analytical formulas cannot be to modern ICs and proposed the PEEC (Partial Equivalent applied to inductance extraction. Element Circuits) model to handle general three dimen- However, although C matrix is sparse, the inverse of C sional interconnects [3, 4]. Kamon, et al more recently de- has been observed to be dense. We speculated that if L is This work was supported, in part, by IBM Corporation and Ultima Inter- dense, then the inverse of L may be sparse. In this paper, connect Technology, Inc. we introduce a new circuit element to represent inductance effect, while still preserve locality for large systems. This " new circuit element, K , is basically the inverse of partial 0 Z Z Ij dl da Aij = 4a a l rij inductance. j j (2) j j j Therefore, we proposed to capture on-chip inductance effect by directly extracting and simulating K , instead of where rij is the geometric distance between two points in partial inductance. Since K has locality, we only need to segment i and j . consider a small number of neighbors. As the result, the Substitute Eq. (2) into Eq. (1), we can get K matrix for circuit simulation is very sparse. Thus it can " save a great amount of CPU time and memory usage when 0 Z Z Z Z dli dlj da da Lij = 4a a capturing on-chip inductance effect. Moreover, we can fur- i j a a l l rij i j (3) ther construct libraries or analytical formulas for K , which i j i j will enable this K -based method to be a practical one to The partial inductance matrix for a set of n conductors predict and capture inductance effect for the whole chip. is an nn real symmetric matrix. The corresponding linear This new concept has been veriﬁed by the simulation re- system is given by sults of practical examples. 2 P R n 3 2 Partial Inductance 2 L11 L12 32 I1 3 1 6 i=1 a1 A1i dl1da1 7 6 L21 L22 76 . 7 = 6 7 Since our proposed K is deﬁned as the inverse of the partial 4 . 54 . 5 6 . 6 . . . 7 7 . . . Lnn In 4 P R n 5 inductance, we begin with a brief review of partial induc- tance. . . 1 an Ani dlndan i=1 It’s well known that inductance is a property of closed (4) loops. Since for on-chip interconnects, the induced cur- From Eq. (3), we can see that the partial inductance Lij rent return paths are unknown, the prevailing inductance only depends on the relative position and length of seg- models are built on partial inductance concepts. Partial in- ment i and j , and is independent of the existence of other ductance are best understood in terms of the normalized conductors. That is to say, the existence of other conduc- magnetic vector potential drop along a conductor segment tors has no shielding effect on the inductive coupling be- due to current in that, or another segment. Consider the tween segment i and j , under this partial inductance def- two conductor segments, i and j , as shown in Fig. 1. inition. Furthermore, since the integral kernel of Lij is rij , the off-diagonal elements in the partial inductance ma- trix decrease very slowly (at the order of log rij ) with the d a 00000 111111111111111111111111 000000000000000000000000 11111 00000 111111111111111111111111 000000000000000000000000 11111 11111 00000 111111111111111111111111 000000000000000000000000 increase of spacing rij . Because of this long range induc- 00000 000000000000000000000000 111111111111111111111111 11111 11 A00 11111 000000000000000000000000 111111111111111111111111 00000 tive coupling effect for partial inductance of on-chip wires, Ajj 00 11 000000000000000000000000 111111111111111111111111 00000 11111 11 00 ij 11111 111111111111111111111111 000000000000000000000000 00000 00 11 11111 00000 000000000000000000000000 111111111111111111111111 capturing inductive couplings becomes much more difﬁ- 11111 00000 111111111111111111111111 000000000000000000000000 cult than capturing capacitive couplings, which is known 11111 111111111111111111111111 000000000000000000000000 00000 to be local. Moreover, it is understood that making the 00000 000000000000000000000000 111111111111111111111111 11111 00000 000000000000000000000000 111111111111111111111111 11111 matrix sparse by merely discarding the smallest terms can b 111111111111111111111111 000000000000000000000000 11111 00000 c render the matrix indeﬁnite and thereby introduce positive Ij pole(s) in subsequent circuit simulations. Figure 1: Partial inductance associated with magnetic vec- tor potential drop along the conductor segments. Both seg- 3 Circuit Element K ment loops are assumed to close at inﬁnity. 3.1 Deﬁnition of K K is deﬁned as inverse of partial inductance matrix L. The partial inductance Lij between segment i and j is given by K = L ,1 (5) hR R i 1 ai ai lj Aij dli dai This deﬁnition originated from the well known relation- Lij = Ij (1) ship between capacitance and inductance for transmission line structures, where Aij is the magnetic vector potential along segment Lloop = 0 0 C0 ,1 (6) i due to the current Ij in segment j . Segment i has a cross section aj . In magneto-statics, the relationship between the where 0 and 0 are permittivity and permeability in free magnetic vector potential Aij and the current Ij is given by space, respectively. C0 is the capacitance matrix which would result if all dielectric layers were replaced by free space. This relationship inspired us that for structures other than transmission lines, although the inverted inductance of the above structure shown in Fig. 2 using FastCap [10]. matrix, K (or L ,1 ), is not proportional to capacitance 2 3 matrix, C0 , K may still have similar local property as 555 ,202 ,43:8 ,23:5 ,20:9 C0 . If this is true, then we can apply K extraction lo- 6 6 ,202 631 ,187 ,37:0 ,23:5 7 7 cally, and derive RKC equivalent circuit models, instead C =6 4 , : ,187 43 8 634 ,187 ,43:9 7 5 pF of RLC models to model the inductance effect. , : ,37:0 23 5 ,187 631 ,202 Here, we should emphasize that Lloop have complete , : ,23:5 20 9 ,43:9 ,202 555 different meaning with L . The element in Lloop is loop (9) inductance, and it was calculated with a pre-deﬁned ground It can be observed the amazing similarity of the decreas- return path. That is to say, there is only an n , 1 ing trend of the off-diagonal elements in both K and C ma- n , 1 Lloop matrix for an n conductor system. While trix. For example, the absolute value of mutual capacitance the element in L matrix is partial inductance, and it was jC51 j is about 20.9/555 or 3:8% of the self capacitance C11 . assumed all current return in inﬁnity. For an n conductor That is to say, the off-diagonal elements in K matrix system, an n n L matrix is obtained. Therefore, although, decrease faster than that of the partial inductance matrix, the K matrix has similar locality as the C matrix, it is not and at a similar speed as that in capacitance matrix, which related to the capacitance matrix. we call K matrix has locality. The physical explanation of this locality for K matrix is provided in [1]. 3.2 Locality of K 3.3 K -based method The following example demonstrate the locality of K ma- trix. Consider a layout example with ﬁve parallel buses, Since K has locality, we only need to consider a small shown in Fig. 2. The length of all buses is 20 m, the cross number of conductors enclosed in small window when ex- section is 2x2 m, and the spacing between the buses is 5 tracting K . Our approach can be summarized as follows. m. Calculate the partial inductance matrix, L, of a small structure which is enclosed in a small window. Calculate the small K matrix by inverting the corre- sponding L matrix. l Compose the big Kall matrix by the column in each small K matrix, which is corresponding to the aggres- sor, like the techniques used in capacitance extraction. h 1 2 3 4 5 Simulate the subsequent RKC equivalent circuit. w s As we mentioned before, in order to be a practical ap- Figure 2: Layout Example with 5 Parallel Buses proach, K -based method has to guarantee the stability of the subsequent RKC equivalent circuit. The proof of the stability abide by the following steps [1]: We calculated the partial inductance matrix, L, using K matrix in general is diagonal dominant. FastHenry [5], The sparse Kall matrix constructed by K -based 2 3 method is still diagonal dominant. 11 4 : : 1:79 1:38 : 4 26 2 54 Kall matrix is positive deﬁnite. Therefore, the subse- 6 6 : 4 26 : : 2:54 1:79 11 4 4 26 7 7 quent RKC equivalent circuit is stable. L =6 4 : 2 54 : : 4:26 2:54 4 26 11 4 7 5 pH; (7) Due to space limitation, please reference [1] for detailed : 1 79 : 11:4 4:26 : 2 54 4 26 proof. : 1 38 : 4:26 11:4 : 1 79 2 54 Therefore, for a large system, K -based method will and then inverted L to get K matrix. generate a very sparse and stable system in later circuit simulation. Thus it can save a great amount of CPU time 2 103 ,34:1 ,7:80 ,4:31 ,3:76 3 and memory usage when capturing on-chip inductance ef- 6 ,34:1 114 ,31:6 ,6:67 ,4:31 7 9 ,1 fect. K = 6 ,7:80 ,31:6 115 ,31:6 6 4 ,4:31 ,6:67 ,31:6 114 ,7:80 710 H 7 ,34:1 5 ,3:76 ,4:31 ,7:80 ,34:1 103 4 Experiment Results (8) To simply illustrate the accuracy of K -based method, we From Eq. (7) and Eq. (8), we can see that the partial mu- still use the 5 parallel buses example shown in Fig. 2. We tual inductance L51 is 1.38/11.4 or 12:1% of the partial self calculate the loop inductance between bus 1 and 5 with inductance L11 , while jK51 j is only 3.76/103 or 3:7% of and without the coupling term K15 . That is we calculate the self term K11 . the loop inductance between bus 1 and 5 associated with Meanwhile, we also calculated the capacitance matrix matrix K and K 0 , stated in Eq. 8 and Eq. 10, respec- tively. Since directly calculating loop inductance using K matrix involves complicated calculation, we use the corre- meshed into 100 equal 10 mm square segments along the sponding partial inductance matrices, L and L0 , stated x direction, and uniform current ﬂow was assumed along in Eq. 7 and Eq. 11, respectively. all segments (FastHenry parameters nhinc and nwinc were 2 3 set to one). 103 ,34:1 ,7:80 ,4:31 0 Firstly, to visualize the decrease speed of the off- 6 ,34:1 114 ,31:6 ,6:67 ,4:31 7 9 ,diagonal elements in L matrix and K matrix, we plotted K0 = 6 6 4 ,7:80 ,31:6 115 ,31:6 ,7:80 710 H the normalized mutual couplings between the left-bottom 7 5 1 ,4:31 ,6:67 ,31:6 114 ,34:1 most segment and other segments in the same power plane 0 ,4:31 ,7:80 ,34:1 103 with respect to the self term of the left-bottom most seg- (10) ment for both L and K matrix, depicted in Fig. 4 and Fig. 5, respectively. We observed that the off-diagonal elements in 2 : : 2:42 1:60 0:89 3 K matrix decrease much faster than those of the partial in- ductance matrix, which again illustrated the locality of K 11 3 4 17 6 : 4 17 : 11 4 4:20 2:46 1:60 7 matrix compared to L matrix. Since K has locality, we L0 = 6 6 4 : 2 42 : 4 20 7 pH; 11:4 4:20 2:42 7 : : 4:20 11:4 4:17 5 only need to consider a small number of conductors en- closed in small window when extracting K . 1 60 2 46 : 0 89 : 1 60 2:42 4:17 11:3 (11) As we all know, Lloop15 = L11 + L55 , L15 , L51 . With the coupling term K15 , we get Lloop15 = 2 11:4 , 1:38 = 20:04pH . Without the coupling term K15 , we 1 get L0 15 = 2 11:3 , 0:89 = 20:82pH , which is 0.8 11 Normalized mutual L vs. L loop 3.9% more than the exact value Lloop15 . However, if we i1 0.6 approximate Lloop15 by directly ignoring L15 in L matrix, we will get L00 15 = 2 11:4 = 22:8pH , which is 13.8% 0.4 loop overestimation, a much larger error compared to K -base 0.2 0 method. 0 Next, consider the two power planes depicted in Fig. 3. 2 4 10 This is the same example presented in Fig. 5 of [7]. When power plane inductance and K matrix are modeled, power 6 8 6 8 4 planes such as these are meshed into separate x and y con- 2 10 0 x y ductor segments. (Even solid power planes are meshed into separate x and y conductors.) Because orthogonal conduc- Figure 4: Normalized mutual couplings between the left- tors do not couple magnetically, the resulting inductance bottom most segment and other segments in the same matrix and K matrix are block diagonal matrices. power plane with respect to the self term of the left-bottom most segment for L matrix plane thickness = 0.025 mm z 10 cm y 10 cm 1 x 0.8 Normalized mutual Li1 vs. L11 0.1 mm 0.6 0.4 0.2 Figure 3: Two Power Planes for Inductance Effect Model- ing 0 0 2 4 10 8 6 To compare our approach with the conventional and the 8 4 6 2 shift-truncate method in [7], we calculate the eigenvalues 10 0 y x of partial inductance matrix in the conventional and the shift-truncate method by strictly following Krauter’s paper Figure 5: Normalized mutual couplings between the left- [7]. bottom most segment and other segments in the same That is, for the two planes depicted in Fig. 3, we created, power plane with respect to the self term of the left-bottom using FastHenry [5], a partial inductance matrix to model most segment for K matrix the magnetic coupling in the x direction. Each plane was Secondly, from this FastHenry partial inductance ma- also be the inverse of those of L matrix. For better illustra- trix, we created two sparse approximations of the full ma- tion, we plotted the inverse of K ’s eigenvalues in Fig. 8. trix. The ﬁrst approximation was formed using the shift- In observing Fig. 7, note that the approach of simply dis- truncate procedure. That is, we set the current return radius carding the smallest terms in the inductance matrix, yields r0 equal to 12 mm, and when the result was negative, the both an inaccurate and an unstable approximation as it fails matrix term was set to zero. The projection on x-y coor- to match the eigenvalues of the full matrix at both extremes dinate of the small representing structure enclosed in the and in the middle. Although the smallest 100 eigenvalues current return shell is shown in Fig. 6. of the shift-truncate method match those of the full L ma- trix, and shows the same discontinuous jump between the 1 cm 100th and 101st eigenvalue, there are signiﬁcant difference for larger eigenvalues between the shift-truncate method y and the full matrix. 2e-08 r0 1 cm x full L matrix sparse K matrix 1.5e-08 current return shell 1e-08 eigenvalues (H) Figure 6: The Representing Structure in Modeling the Two Power Planes 5e-09 The second sparse approximation was formed by dis- carding all mutual inductances less than 0.75 nH. In both 0 cases, 38,160 of the total 40,000 matrix terms were set to zero, (i.e. both approximations were 95% sparse). Fi- nally, the eigenvalues of the full matrix and the two sparse -5e-09 0 20 40 60 80 100 120 140 160 180 200 approximations were computed. The 200 eigenvalues for eigenvalue # each matrix are plotted in Fig. 7. Figure 8: Eigenvalues for Full L matrix and 95% Sparse 2e-08 K Matrix Modeling the Two Power Planes in Fig. 3 full L matrix truncation only Fig. 8 shows the excellent match of the eigenvalues be- tween sparse K matrix and full L matrix. 1.5e-08 shift-truncation Finally, to compare the effects of full inductance ma- 1e-08 trix and sparse K matrix in circuit simulations, we choose a structure presented in Fig. 8(b) of Krauter’s paper [7]. eigenvalues (H) The circuit is illustrated in Fig. 9. We deliberately chose 5e-09 this circuit topology because the current loops were larger than that in Fig. 8(a) of Krauter’s paper [7]. Thus, it will be more obvious whether or not the K -based method can 0 capture enough mutual inductance coupling. In this struc- ture, each conductor has cross section of 2x2 m square, -5e-09 d1 = 10m, d2 = 40m, and d3 = 1600m. Each con- 0 20 40 60 80 100 eigenvalue # 120 140 160 180 200 ductor was broken into forty equal segments in order to create a large yet illustrative partial inductance matrix. Figure 7: Eigenvalues for Full and 95% Sparse L Matrices To make the inductive effects dominate, Rs and Rt were Modeling the Two Power Planes in Fig. 3 set to 1 and 10 ohms, and a rise time (0.1ns) was employed to simulate the frequency of on-chip interconnect applica- In our K -based approach, we calculated the K matrix tion. In our approach, the window size was assumed to in- of the conductor segments included in the small window as clude at most 3 segments of each conductor. The sparsity those enclosed in the current return shell in shift-truncate of the resulted K matrix is about 92.6%. The circuit sim- method to ensure same sparsity. Therefore, the whole K ulation is performed by Ksim [1], which simulates RKC system has exactly same sparsity ( 95%) as those in shift- equivalent circuit, instead of RLC . The simulation results truncate and truncation only method. Since K matrix is the inverse of L matrix, the eigenvalues of K matrix should is shown in Fig. 10. We can see good agreement in terms truncation only method. d1 We further understand the physical meaning of K and the reason that K has local property [1]. Most importantly, Rt it can be proved that the sparse system matrix constructed Rs d2 by ignoring far away mutual K is positive deﬁnite [1]. Therefore, we can later construct libraries or analytical d3 formulas for K , which will enable this K -based method to be a practical one to predict and capture inductance effect for the whole chip. Figure 9: Circuit Example same as Fig. 8 from Krauter’s paper[7] References of circuit simulation results between the full L matrix and [1] H. Ji, A. Devgan, and W. Dai, “Ksim: A stable and the sparse K matrix. efﬁcient RKC simulator for capturing on-chip induc- tance effect,” UCSC Technique Report, UCSC-CRL- 1.2 Simulation results of V_34 for full matrix and sparse matrices modeling the circuit with 4 conductors 00-10, Apr. 2000. input full L matrix K-based method [2] E. Rosa, “The self and mutual inductance of linear 1 conductors,” in Bulletin of the National Bureau of Standars, pp. 301–344, 1908. 0.8 [3] A. Ruehli, “Inductance calculations in a complex in- tegrated circuit environment,” IBM Journal of Re- V_34 (V) 0.6 search and Development, pp. 470–481, Sept. 1972. 0.4 [4] A. Ruehli, “Equivalent circuit models for three- dimensional multiconductor systems,” IEEE Trans. on MTT, pp. 216–220, Mar. 1974. 0.2 [5] M. Kamon, M. J. Tsuk, and J. K. White, “FAS- 0 THENRY: A multipole-accelerated 3-D inductance 0 0.05 0.1 0.15 0.2 0.25 time (ns) 0.3 0.35 0.4 0.45 0.5 extraction program,” IEEE Trans. on MTT, pp. 216– 220, Sept. 1994. Figure 10: Simulation Results for Circuit Example in Fig. 9 [6] Z. He, M. Celik, and L. Pileggi, “SPIE: Sparse par- tial inductance extraction,” in Proc. 34-th Design Au- tomation Conference, pp. 137–140, June 1997. 5 Conclusion [7] B. Krauter and L. Pileggi, “Generating sparse par- tial inductance matrixes with guaranteed stability,” in Partial inductance are extremely useful in modeling circuit Proc. IEEE International Conference on Computer inductances when the induced current loops are unknown. Aided Design, pp. 45–52, Nov. 1995. Unfortunately, these matrices are dense and defy conven- tional simpliﬁcations (i.e. the smallest matrix cannot be [8] K. L. Shepard and Z. Tian, “Return-limited induc- indiscriminately discarded). tances: A practical approach to on-chip inductance In this paper, we introduce a new circuit element, K , extraction,” in Proc. IEEE Custom Integrated Circuits as the inverse of partial inductance. We found out that K Conference, pp. 453–456, 1999. is capable of capturing inductance effect, while still pre- serve locality. Since K matrix is a sparse diagonally dom- [9] S. Lin, N. Chang, and S. Nakagawa, “Quick on-chip inant matrix, we only need to consider a small number of self- and mutual-inductance screen,” in Proc. IEEE neighbors. Therefore, we proposed to capture on-chip in- 1st International Symposium on Quality Electronic ductance effect by directly extracting and simulating K , Design, pp. 513–520, Mar. 2000. instead of partial inductance. As the result, the K matrix for circuit simulation is very sparse. Thus it can save a [10] K. Nabors and J. K. White, “FastCap: a multipole ac- great amount of CPU time and memory usage when cap- celerated 3-D capacitance extraction program,” IEEE turing on-chip inductance effect. This new concept has Trans. on CAD, pp. 1447–1459, Nov. 1991. been veriﬁed by the simulation results of practical exam- ples, and showed remarkable accuracy over other sparsi- ﬁcation techniques, such as the shift-truncate method and