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					                                                  About This Issue

Accellera Workshop Showcases SystemVerilog
3.0

December 2 to 6, 2002 By Peggy Aycinena
Read business product alliance news and analysis of weekly happenings




A truce is called in the system-level language wars


The foot soldiers in the system-level language wars appear to have climbed out of the trenches and
traded in their battle fatigues for suits and ties. Looking and sounding for all the world like
distinguished diplomats negotiating a peace accord, representatives from two of the previously
warring factions - SystemVerilog and SystemC - shared a stage in front of a sold-out crowd in
Santa Clara, CA on November 5th and spoke enthusiastically about mutual cooperation and respect
for their various technology initiatives.


The day-long Accellera workshop sponsored by Synopsys, Mentor Graphics, and Real Intent -
“Accellera's Verilog Evolution: An Introduction to SystemVerilog” - heard both sides pledge to move
forward on behalf of beleaguered chip designers, to provide integrated language options for
everything from system specification to gate-level layout and design verification. This level of
bonhomie would have been unthinkable a few short years ago, but the perseverance of the hard-
working committees at Accellera seems to have paid off - aided, undoubtedly, in no small measure
by the Synopsys acquisition of Co-Design earlier this year.


Accellera - itself a peace initiative created in 2000 out of two previous standards bodies, VHDL
International and Verilog International - was chartered to find a common ground between the two
HDL constituencies. Meanwhile, Co-Design, home to Verilog author, Phil Moorby, was the spring
board for the Verilog-turned-system-spec-language, Superlog.


Subsequently, Accellera benefited from Co-Design's donation of the synthesizable portion of
Superlog, Verplex's donation of assertion libraries, and Real Intent's and Co-Design's donations
of assertion syntax and semantics and the move was on to create SystemVerilog - an extension of
the IEEE 1364 Verilog-2001 standard - and take the HDL to a higher level of existence as a system
specification language meeting designers' demands in the emerging era of system-on-a-chip (SoC).


However, not everyone agreed that system specifications could be articulated by limited HDL
constructs. Critics believed that higher level languages had to be the source of an over-arching
language for system specification, hardware design, and verification. From various corners in the
industry, C-based system languages sprang up and gathered momentum - System C, in particular,
benefiting from high-profile encouragement from Synopsys and other EDA players.


It was of no small import that the software guys wanted to see things progress in the C direction -
a language they were raised on - while the hardware guys were equally determined to see their
beloved HDLs win the day. As it turns out, the truce in the language wars - at least between
SystemC and SystemVerilog - currently succeeds in moderately satisfying both sides.
SystemVerilog 3.0 has been beefed up with a host of assertion constructs to meet verification
demands while SystemC has been legitimized as a robust solution for system-level specifications.
Accellera and Synopsys are commending both languages.


Following a keynote address by Mentor Graphics' Dennis Brophy, Stu Sutherland of Sutherland
HDL, Inc. presented a detailed tutorial on SystemVerilog 3.0. Then Steve Meier of Synopsys and
Rajeev Ranjan of Real Intent expanded on Sutherland's tutorial with discussions of the assertion-
based verification and formal verification components of SystemVerilog.


Sutherland said the 3.0 release offers capabilities that exceed previous releases by orders of
magnitude. He emphasized that Accellera is attempting to move at a faster pace than the
infamously slow IEEE committees to establish and document the SystemVerilog 3.0 standard. He
said working specs should be made available and put to good use earlier than traditional IEEE
practices allow for. As such, Accellera hopes to have full documentation and code for SystemVerilog
3.0 ready by Q2 2003 in time for DAC. Asked what happens to the SystemC initiative with the
introduction of SV 3.0, Sutherland said, “SystemVerilog won't replace SystemC. SystemVerilog will
make it possible for software people to work in SystemC and hardware designers to work in Verlog.
It will allow the integrations of both of their effots.”


If ever there was an enthusiastic evangelist for Superlog - and SystemVerilog - that would have
been Co-Design's Dave Kelf , now Senior Director of Marketing, Verification Technology Group, at
Synopsys. Dave's contagious optimism today is directed at the new language cohesion in the
industry: He says there's been a “bit of a re-org” within Synopsys and the SystemVerilog people
and the SystemC people are now working side-by-side. “It's great,” he says. If Dave Kelf sees the
move to promote both languages as a positive one, who dares argue?


Industry News


Agere Systems Inc. introduced the FlexPHY IC, a new single-chip physical layer (PHY) transceiver
that reduces space and power by 50+ percent over existing two-chip solutions, and enables high
transmission signal quality for multi-service metropolitan edge-to-core networks. A PHY transceiver
chip transmits and receives data between the physical (optical fiber) and information processing
layers. On a network line card, Agere's FlexPHY chip resides at the boundary between the protocol
framer and the optics. The FlexPHY device addresses jitter margins, power consumption and
integration for system vendors targeting 10-gigabit SONET/SDH, Ethernet, and Fibre Channel
networks. Samples of the FlexPHY chip are expected to be available in Q1 of 2003, with volume
production expected by Q2. The market for 10-gigabit PHYs is expected to increase from $276
million in sales in 2003 to $780 million in 2006.


Aldec, Inc. announced that designers who use Xilinx Foundation legacy schematics in their
designs can port them directly into Aldec's Active-HDL's high-performance, mixed-language
simulator to be implemented in any Xilinx device. The ported schematics are translated into HDL
block diagrams and are graphically represented as native schematics files that previously existed in
Foundation. Designers can use the pre-existing schematic modules instead of having to re-create
the designs in HDL code. By supporting both schematics and HDL modules in a single environment,
Active-HDL allows designers to re-use legacy designs in support of new Xilinx devices. Aldec
initially authored and developed all design editors and project managers for the Xilinx Foundation
Series software.


ARM announced that more than 25 partners have signed up to provide support and technical
contributions towards the development of the next generation of the AMBA (Advanced
Microprocessor Bus Architecture) specification. AMBA is an open standard, on-chip bus specification
freely available from ARM that details a strategy for the interconnection and management of
functional blocks that make up an SoC. AMBA 3.0 technology will be available for public release in
Q1 of 2003.


Twenty-five companies have collaborated on the development of the AMBA 3.0 standard, including:
Agere Systems, Agilent, Atmel, Cadence Design Systems, Inc., Conexant Systems,
CoWare Inc., Infineon, LSI Logic, Mentor Graphics, Micronas, Motorola, NEC Electronics
Corp., NEC Electronics (Europe), Philips Semiconductors, Samsung, STMicroelectronics,
Synopsys, Toshiba Corp., and Verisity.


Rafi Kedem, Senior Director of the Processor Cores Technology Group at LSI Logic said, “AMBA
3.0 technology introduces new capabilities, not just at the protocol level, but also to ease physical
implementation of the bus in deep-submicron technologies. LSI Logic is already implementing
targeted peripherals and subsystems based on the draft AMBA 3.0 standard.”


Circuit Semantics Inc. announced that Telairity Semiconductor, Inc. has chosen Circuit
Semantics' DynaCell and DynaCore as characterization solutions for its intellectual property (IP)
design flow. Telairity design engineers use DynaCell to automatically characterize standard cell
libraries for timing and power - the libraries are then used as building blocks for proprietary IP
designs. Telairity's IP is designed to achieve specific timing goals. DynaCore is used to measure,
verify and report timing for the block-level design. DynaCore uses the combination of a
characterization engine and a static timing engine to provide accurate, automated timing results.
Initial applications will be targeted for the communications and consumer markets.


Esterel Technologies announced 30 additional universities have joined the company's academic
program since March 2002, for a total of 50 universities worldwide. Esterel's donations to these
universities exceeds $37.5 million. Under the program, participating universities may license up to
20 seats of Esterel's SCADE and up to 20 seats of Esterel Studio at no charge, provided that the
software is used for educational purposes only. The program enables students to learn how to
design and verify embedded software and automatically verifiable RTL. New program enrollees
include among others U.C. Santa Cruz, University of Minnesota, Embry Riddle Aeronautical
University, Tata Institute of Fundamental Research, Université de Bretagne Occidentale,
ENSTA, Ecole Centrale de Lille, University of Calgary, Linkoping University, and Ecole
d'ingénieurs de Genève.
Mentor Graphics Corp. announced co-verification model support for the ARCtangent user-
customizable RISC/DSP core from ARC International, a provider of configurable SoC platform
technologies. Comprehensive development platforms may include pre-verified peripherals, system
software, embedded middleware and tools. The ARCtangent microprocessor is a user-customizable
RISC/DSP core that allows developers to modify and extend the architecture for specific
applications. Mentor Graphic's Seamless verification tool will help designers of ARCtangent
microprocessor-based systems to model the customized interactions between components in a
virtual environment and reduce resource allocations for physical prototyping.


Monterey Design Systems announced the latest release of the company's tool set: IC Wizard
hierarchical design planner, Sonar physical synthesis and prototyping tool, and Dolphin physical
implementation system. Release 2.5 of the Monterey tool set is the fastest, highest capacity, and
most functionally complete product line offered to date by the company. Recently announced tape-
outs and target designs include consumer electronics chips, streaming data processors, and switch
fabrics ranging in size from one million to 20 million gates on process technologies of .15 micron,
.13 micron, and 90 nanometers.


Prior releases of IC Wizard were optimized to deal with hundreds of hard blocks, but worked best
when standard cells were clustered into blocks at the top level. IC Wizard 2.5 support un-clustered
standard cells at the top level and automatically configures the timing and physical constraints
taking into consideration all instantiations of the block within the context of the chip-level design
plan. Sonar and Dolphin 2.5 offer improvements in circuit performance of 10%-15% by
incorporating new physical synthesis and placement algorithms. Memory utilization has been
improved to handle designs twice as large as prior versions increasing the flat capacity beyond 5
million gates. When combined with the hierarchical capabilities in IC Wizard, capacity scales
upwards of 100 million gates.


Nassda Corp. announced that National Semiconductor has adopted Nassda's HSIM hierarchical
full-chip simulator and analysis tool for the design and verification of complex ICs. Under a multi-
year agreement, National is deploying HSIM licenses worldwide and standardizing on the simulator.
HSIM provides detailed circuit-level analysis of timing and power behavior and signal integrity
effects, analyzing circuit behavior while taking into account the electrical and parasitic effects of
nanometer-scale silicon.


Novas Software, Inc. announced that Sanyo Semiconductor Co. (SSC) has adopted the Novas
Debussy Knowledge-Based Debug System as its standard IC debug system. SCC is the one of the
Sanyo group companies involved in developing system LSIs with microcomputers and system LSIs
for digital consumer devices. SCC signed a multi-year purchase agreement with Novas for broad
deployment of Debussy within the LSI System Division, enhancing product development with more
functionality, higher quality, and greater reliability for digital cameras and digital TVs. The Debussy
debug system automates the tracing, visualization, and analysis of causes and effects in Verilog,
VHDL and mixed-language descriptions.


Oridus, Inc. announced a licensing agreement with Cadence Design Systems, Inc. Under the
terms of the agreement, Oridus will equip Cadence field application engineers and customer
support centers with its SpaceCruiser client/server software for real-time desktop sharing and web
conferencing. Oridus' cross-platform and cross-network products utilize the Internet and corporate
intranets and allow customers to control software and capabilities deployed into their network
environment. The products employ several levels of security including 128-bit SSL encryption,
LDAP integration, and role-based authentication procedures.


Additionally, Oridus and UMC announced that UMC has expanded its on-line customer services
with Oridus' web-based mask data MEBES (Manufacturing Electronic Beam Exposure System 2)
reader tool, MebesCruiser. UMC customers can view and browse their MEBES database of an IC, or
link teams of engineers for collaboration via web conferencing in a highly secure, on-line mask data
environment. MebesCruiser, when integrated into UMC's web environment, displays a multi-
gigabyte mask file onto desktop PCs or workstations running Windows, UNIX, or Linux operating
systems.


SiRF Technology, Inc. and Motorola, Inc.'s Semiconductor Products Sector (SPS), announced
an agreement to integrate SiRFstarII Global Positioning System (GPS) cores with Motorola wireless
baseband and applications processors. Motorola plans to incorporate SiRF's GPS technology into a
line of location-aware wireless baseband and applications processor chipsets. The chipsets will
utilize SiRF's SiRFstarII GPS baseband and RF IC core technology. Motorola intends to implement
an enhanced version of SiRF's RF IC technology using the Silicon Germanium-Carbon module of its
advanced RF BiCMOS wafer process.


Verisity Ltd. and Novas Software, Inc. announced that Novas has joined Verisity's LicenseE
program. As a member of the program, Novas will implement support for Verisity's e verification
language in its debug systems, as well as participate in the e language standardization efforts.
Verisity also announced that it will join Novas' Harmony program to promote verification
methodologies and tool interoperability. By joining the LicenseE program, Novas will build on
existing data transfer integration between Specman Elite and the Debussy Knowledge-Based Debug
System. Verisity's LicenseE program was created to facilitate verification tool interoperability and
standardization. Program members receive open access to the e language, including a stand-alone
e parser, and participate in the e Steering Committee.


Xilinx, Inc. and Tarari, Inc. announced that Tarari has selected Xilinx reprogrammable chip
technology in the development of the Tarari Content Processing Platform. Tarari content processors
are hardware and software-based subsystem building blocks that snap into servers, appliances and
network devices, and allow for the inspection of application layer content at network speeds. Tarari
and Xilinx plan to continue to work together in the development of next generation products for the
application-layer content-processing markets.


Coming soon to a theater near you


IEEE International Electron Devices Meeting - December 8th to the 11th, San Francisco and the
Hilton Hotel will plays host to IEDM, the premier scientific meeting covering advances in electron
devices. Annually a showcase for future trends in transistor physics and material science, the
leading lights from academia and industry will present their latest R&D. The plenary talks on
Monday feature presentations on “Lithography for Sub-100nm Applications,” “Chip Technologies for
Entertainment Robots: Present and Future,” and “Photonic Bandgap Based Designs for Photonic
Integrated Circuits.” The keynote speaker at Tuesday's lunch will be Intel's Dr. Andrew Grove
discussing: “Changing Vectors of Moore's Law.” Proving that even engineers can party hardy, the
ever-popular Tuesday evening wine-and-cheese panel sessions will offer attendees a choice:
“Embedded Memories for SoC - What Makes Sense, Cents?” or “Will SOI Ev! er Become a
Mainstream Technology?” See www.his.com/~iedm/index.html for registration information.


Electronic Design and Solution Fair 2003 - The 3rd annual conference is taking place in
Yokohama, Japan on January 30th and 31st and will run concurrently with the FPGA/PLD Design
Conference and the University Plaza exhibition. EDSFair aims to provide technology interchange
between industry, academia, and government organizations and will focus on SoC product
development. Organizers report that EDSFair was developed as a platform for publicizing the
newest developments combining leading-edge EDA technologies, devices, and IP design services.
In 2002, EDSFair established a cooperative relationship with EDAC and was viewed as one of the
largest comprehensive exhibitions in Asia. Details are available at www.edsfair.com.


International Conferences on VLSI and Embedded Systems Design - 2003 will be the first
year in which the 16th International Conference on VLSI Design and the 2nd International Conference
on Embedded Systems Design will be held jointly. The conference will take place next month in
New Delhi, India, from January 4th to 8th and is being sponsored by the VLSI Society of India, the
Ministry of Information & Communications Technology for the Government of India, IEEE,
ACM, and NASSCOM. The theme of the conferences is “Design Convergence in SoC Design.”
Business leaders and designers from all over India - and outside of India - participate in the
conference. The program will include two full-day tutorials, technical paper sessions, panel
discussions, and an exhibition. Advance program and registration information is available on the
conference w! ebsite at www.vlsidesign.org.


OEA International, Inc. is sponsoring a free technical seminar on December 12th from 9 AM to 5
PM at the San Diego Marriott in La Jolla, CA. The seminar - “RF Passive Components and On-chip
Critical Net Design and Analysis” - will address extraction issues that impact the quality of critical
net and passive component design. Topics will include: accurate clock skew prediction, interconnect
modeling with inductance, accurate substrate models, incremental extraction of critical paths, and
low-power design. Registration information is available on the company's website.


Newsmakers


Numerical Technologies, Inc. named Dr. Naren Gupta as the company's interim president and
CEO. He replaces Larry Hollatz, whose resignation is effective immediately. A search for a
permanent president and CEO is under way. Gupta said, "The company is financially strong and will
continue to move forward on its goals of enabling sub-wavelength lithography during the interim
period and beyond. We expect to attract an exceptional executive who complements the
management team at Numerical.”
Gupta has served as an advisor to the company and a member of Numerical's Board of Directors
since 1977. Gupta co-founded Integrated Systems Inc. in 1980 and served as President and
CEO through 1994. He was Chairman of Integrated Systems until it merged with Wind River
Systems, Inc. in 2000. Gupta is currently Vice Chairman of the Board at Wind River. Hollatz took
the helm at Numerical in August when founder and former CEO, Dr. Y.C. (Bruno) Pati stepped into
the role of Chairman of the Board.


In the category of ...


FUD on the Ropes


Fear, Uncertainty, and Doubt may be the stuff of great suspense novels, but they've got no
business in a healthy economy. FUD has occupied center stage in the tech sector for over two
years now and the question is - when will it fade from view? The recent spate of financial report
cards coming out of various players in high tech companies may offer an answer to the question -
or at least a hint.


Agilent President and CEO Ned Barnholt said, “After five consecutive quarters of operating losses,
breaking even this quarter was gratifying. We delivered results at the top end of company
expectations. These results demonstrate that we're making progress in our drive to restore Agilent
to financial health. But we remain cautious going forward, and we still have a lot of work to do in a
difficult economic environment.”


Similarly guarded optimism came from Nick Csendes, President and CEO of Ansoft: “Although
business conditions continue to be tough, we saw momentum building throughout the quarter and
expect sales to continue to improve back to record levels by our fourth quarter. We also made
some critical decisions to refocus our core software business which should bring us back to
profitability in [the next quarter]."


From Mentor Graphics' recent announcement: “Mentor bookings are expected to grow almost 20
percent in 2003. Half of that growth is expected to be a result of acquisitions made in 2002, IKOS
emulation in particular, and the other half organic growth, led by the Calibre product family. We
expect to build significant backlog in 2003 and anticipate closing the year with a very healthy book-
to-bill.”


Synopsys' Chairman and CEO, Aart de Geus, described the cup as half full: “2002 was a year of
tremendous achievement for Synopsys. Despite the challenging market environment, we were able
to maintain our focus to deliver best-in-class products to our customers. At the same time, we
successfully completed the Avanti acquisition, which is the most important strategic acquisition in
our company's history. Though we remain cautious about the overall economic environment, we
enter 2003 excited about our prospects ahead.”


And in line with the blues lament, “been down so long, bottom looks like up,” Texas Instruments
said the company expects revenue for the fourth quarter of 2002 to be better than previously
estimated. TI's Semiconductor revenue is now expected to decline about 2 percent sequentially,
instead of the 5 percent originally noted in the company's earnings report on October 21. Total TI
revenue is now expected to be down about 7 percent instead of 10 percent, mostly reflecting the
seasonal drop in calculator shipments. TI's CFO Bill Aylesworth said, “The improvement in fourth-
quarter expectations comes primarily from stronger demand for our wireless and high-performance
analog products.”


You heard it. Aylesworth said, “wireless.” No doubt about it. There are stirrings of life in the tech
sector. Barring negative developments in international affairs, there's reason to hope that FUD is
on the ropes.




AND MORE…..
News for the last 31 days.                                                            Older


      Nassda Announces Full-Chip Critical Timing Analyzer for Cell-Based Designs [10 Dec 2002]
      Axis Systems' Names Gary Kiaski North American Sales Vice President [10 Dec 2002]
      e*ECAD Offering Temento Systems FPGA Debugging and Verification Tool [10 Dec 2002]
      HP Showcasing Itanium-based Superdome Server Running HP-UX, Windows and Linux
       Concurrently [09 Dec 2002]
      Cadence Partners with Leading Test Equipment Vendors to Provide Early System Verification
       for 2.5/3G and 802.11 Wireless Applications [09 Dec 2002]
      VitalCom Named Agency of Record for Axis Systems and Summit Design [06 Dec 2002]
      Venture Capital Investments Continue Decline In Q3 2002 [05 Dec 2002]
      Synopsys Posts Strong Financial Results for Fourth Quarter 2002 [04 Dec 2002]
      Esterel Technologies Teams with Universities to Educate Students in Advanced Methods for
       Software Development and Hardware Design [04 Dec 2002]
      Nassda's Verification and Analysis Software Adopted by National Semiconductor [04 Dec 2002]
      Artisan Components and Cadence Team to Manage Nanometer Design Risk [04 Dec 2002]
      Mentor Graphics Provides Outlook for 2003 [04 Dec 2002]
      HP Reduces Cost and Complexity in Dense Server Environments with New ProLiant Servers
       [04 Dec 2002]
      Agere Systems Provides Atrenta's SpyGlass to Customers for Comprehensive ASIC Handoff
       [03 Dec 2002]
      Aldec Releases Xilinx® Foundation Series™ Legacy Design Import Utility [03 Dec 2002]
      Chip Sales up 20% in October Compared to Last Year [03 Dec 2002]
      ADVISORY/Cadence President and Chief Executive Officer H. Raymond Bingham to Present
       at the Credit Suisse First Boston Annual Technology Conference [02 Dec 2002]
      FREE SEMINAR: Design of RF-Passive Components & Critical Nets [02 Dec 2002]
      Verisity, Novas Facilitate Standardization and Extend Debug Interoperability For Advanced
       Chip and System Verification [02 Dec 2002]
      Mentor Graphics Offers Co-Verification Model Support for ARCtangent User-Customizable
       RISC/DSP Designs [02 Dec 2002]
      Telairity Adopts Circuit Semantics' Characterization Tools to Streamline IP and ASIC Design
       Flow Methodology [02 Dec 2002]
      Oridus' SpaceCruiser Web Collaboration Solution Deployed by Cadence for Enhanced
       Customer Support [02 Dec 2002]
      HP Claims No. 1 Worldwide Position for UNIX, Windows and Linux Servers [29 Nov 2002]
      Sanyo Semiconductor Company Standardizes On Novas Debug Software With Multi-Year
       Agreement [29 Nov 2002]
      TI's Strategy in the Slump: "Play Offense" - Feature Article from BusinessWeek [29 Nov 2002]
      Processing the Changes in Chips - Feature Article from BusinessWeek [28 Nov 2002]
      Philips' Expanding Asian Connections - Feature Article from BusinessWeek [27 Nov 2002]
   The Reverse Brain Drain - Foreign-born techies head home as they lose their jobs--and
    work visas - Feature Article from Fortune Magazine [26 Nov 2002]
   Acer and Cadence Announce Strategic Alliance to Cultivate World-Class Talents in Analog IC
    Design [26 Nov 2002]
   HP Again No. 1 in High Performance Computing Revenues [26 Nov 2002]
   InTime Expands Executive Team, Raises Follow-On Funding [25 Nov 2002]
   Mentor Graphics and Genesys Logic Deliver Integrated USB 2.0 Intellectual Property
    Solution [25 Nov 2002]
   Cadence Completes Purchase of Antrim Assets [25 Nov 2002]
   Accelerated Technology Works with Nucleus Developers to Enhance Networking Software
    [22 Nov 2002]
   HP Delivers New Notebook PC with Desktop Performance and Larger Display [22 Nov 2002]
   ASE Establishes Cadence Design Flow to Provide High-Performance IC Packaging Solutions
    [21 Nov 2002]
   Accelerated Technology Announces E-SIM Prototyping Technology Extended to Nucleus
    Applications [21 Nov 2002]
   Cadence Strengthens Management Team With Key Promotion of Charlie Huang [21 Nov 2002]
   HP Reports 4th Quarter 2002 Results - Beats Earnings Forecast [20 Nov 2002]
   ADVISORY/Nassda's CEO Sang Wang to Present at the edaForum02 [20 Nov 2002]
   Accelerated Technology's EDE Benefits From New Features in Microsoft Visual Studio .NET
    [20 Nov 2002]
   TSMC and Cadence Collaborate To Solve Nanometer Design Challenge On Signal Integrity
    Closure [20 Nov 2002]
   Accelerated Technology Announces First Integrated Product Since Company's Acquisition,
    XRAY Software Developer's Kit [19 Nov 2002]
   Physical Synthesis Customers NEC and AMCC Adopt Cadence NanoRoute Ultra for
    Nanometer Design [19 Nov 2002]
   Atrenta Opens Office in France, Appoints New European Sales Director [19 Nov 2002]
   HP Marks Integration of Workstation Product Lines with Launch of New Systems [19 Nov 2002]
   Artisan Components and Cadence Team to Manage Nanometer Design Risk [19 Nov 2002]
   ADVISORY/Cadence Chief Financial Officer Bill Porter to Present at the Lehman Brothers
    Semiconductor & Computer Systems Conference [18 Nov 2002]
   Agilent Technologies Reports Fourth Quarter Results at Breakeven [18 Nov 2002]
   Novas Software Expands Lead in RTL Market Share [18 Nov 2002]
   Esterel Technologies and TekSci Announce Partnership to Promote Efficient DO 178B
    Development For Avionics [18 Nov 2002]
   Fujitsu Deploys Cadence Nanometer Analysis Technology to Achieve Timing Closure for
    High-end ASIC Designs [18 Nov 2002]
   Synplicity Grows Market Share Lead In FPGA Synthesis [15 Nov 2002]
   HP Retains No. 1 Position in TOP500 Supercomputer Ranking [15 Nov 2002]
   Silicon Canvas Partners with GSMC to Distribute Laker Technology Files [15 Nov 2002]
   ADVISORY/Axis System CEO Mike Tsai to Speak at Lehman Brothers Semiconductor and
    Computer Systems Conference [14 Nov 2002]
   Cadence v. Avant! Litigation Settled [14 Nov 2002]
   0-In Delivers CheckerWare Monitors for Leading Interface Standards [13 Nov 2002]
   Zenasis Technologies Forms Technical Advisory Board [13 Nov 2002]
   X-FAB Adds Support for Mentor Graphics Calibre and xCalibre [13 Nov 2002]
   AccelChip and Aldec Partner to Give DSP Designers FPGA Implementation Flexibility
    [12 Nov 2002]
   Altium pushes design capture into the next dimension [12 Nov 2002]
   Sun Microsystems Licenses Circuit Semantics' Modeling and Characterization Solutions
    [12 Nov 2002]
   Axis Systems' Xtreme Verification System Increases Chip Quality for Matsushita's Newest
    Digital Video Camera [12 Nov 2002]
   Sequence Takes Low-Power Design Seminar Online November 20 [12 Nov 2002]
   HP Announces Departure of Michael D. Capellas [11 Nov 2002]
   Get2Chip, Mentor Graphics Team Up On Emerging Technology Seminar November 14 in
    Santa Clara, Calif. [11 Nov 2002]
   Ewald Detjens Takes Helm At Circuit Semantics [11 Nov 2002]
   ADVISORY/Axis Systems CEO Mike Tsai to Speak at Morgan Stanley Semiconductor Private
    Company Conference [11 Nov 2002]
   ADVISORY/Nassda CEO Sang Wang and CFO Tammy Liu to Present At The AeA Classic
    [11 Nov 2002]