Elance Proposal Sample - PDF

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					CTI
                  CTI
CircuiT Design
    Bench TesTing
        Closed-Loop
           Solid-staTe
                Real-Time
                  Modeling
                     Analysis
                         MOSFEt
                           OpAmpS
Signal Processing               DEBUG
     Troubleshooting
          Prototyping
             Data Comm
                 Interface
                    Routing
                        DigiTal
                        Layout
                           FPGAs
                                PLDs
                                 Code
                  CTI
I/O Conditioning
 DaTa ConverTers
   Microprocessors
          Transducers
               MagneTics
                   DigiTal
                    FerriTes
                      Sensors
                           ADCs
                             DACs
  DisTribuTionS                 PICs
   MonTe-Carlo
        Document
         Six-Sigma
             S-and-H
                ANOVA
                  FMEA
                    DFM
                      WCA
                        LEDs
                                           CTI
                                            PREFACE

After several attempts at compressing the size of the diagrams, photographs, and figures that
were embedded within the original hardcopy of the portfolio, I am resorting to providing
hyperlinks to these diagrams and figures. These ‘picture’ files will reside on a different server
with sufficient memory to accommodate the size of these jpeg, png, and gif files. The ‘drawing
file set’ should be opened in another “window” or session in order to view the portfolio
drawing and the portfolio text simultaneously. * I have indicated the URL for each diagram
within the document where the figure would normally have been located. I have also included a
separate file within the ELANCE PORTFOLIO set of files called “Portfolio Drawings” which
lists all the drawings together with the “live” hyperlinks similar to this section. This file was
added to the PORTFOLIO for more flexibility and to increase the number of drawings that can
be viewed at any given time. There are not an excessive number of drawings within the
document (a total of 9); most of which are located in the last half of the portfolio. I apologize for
any inconvenience.

Sec    Description of Drawing or Document

                                              URL (Uniform Resource Locator)
0-0    Cover Page
                       http://cipherlabs.freewebspace.com/portfolio/image002.jpg

8-1    Bill-of-Material (for Stepper Motor Design)
                      http://cipherlabs.freewebspace.com/portfolio/image006.jpg

9-2    RS-422 Assembly: Component Placement
                   http://cipherlabs.freewebspace.com/portfolio/image008.jpg

12-1   PCB Schematic Page 1 of 2
                   http://cipherlabs.freewebspace.com/portfolio/image095.jpg

12-2   PCB Schematic Page 2 of 2
                   http://cipherlabs.freewebspace.com/portfolio/image097.jpg



*In order to open a second window in which to view the drawing, point the mouse cursor
(symbol) to the desired hyperlink ‘linking’ the diagram and click the left mouse button. Next,
depress the Ctrl key located on the keyboard, and then select the option “Hyperlink.” When the
subsequent pull-down menu appears, select the option: “Open in New Window” from this pull-
down menu. A new window should now appear and the drawing should begin downloading.


                                                  i
                                        CTI
                                   PREFACE (CONTINUED)

12-3   PCB System Block Diagram
                   http://cipherlabs.freewebspace.com/portfolio/image099.jpg

13-2   Recommendation from Andrew Corp.
                   http://cipherlabs.freewebspace.com/portfolio/image101.jpg

13-3   Recommendation from FlightSafety International
                   http://cipherlabs.freewebspace.com/portfolio/image103.jpg

14-1   Photograph of Printed Circuit
                     http://cipherlabs.freewebspace.com/portfolio/image089.jpg

14-2   Photograph of Test Lab Built
                     http://cipherlabs.freewebspace.com/portfolio/image107.jpg

15-1   Reprint of MSEE Diploma
                    http://cipherlabs.freewebspace.com/portfolio/image109.gif

15-2   Certificate from the American Society of Quality Control: CQE
                      http://cipherlabs.freewebspace.com/portfolio/image111.jpg

15-3   Provisional Teaching Certificate: Community Colleges of Arizona
                     http://cipherlabs.freewebspace.com/portfolio/image113.jpg

15-4   ACT-SO Program Volunteer: Maricopa County Chapter
                   http://cipherlabs.freewebspace.com/portfolio/image115.jpg

16-1   IEEE Membership for 2005
                   http://cipherlabs.freewebspace.com/portfolio/image117.jpg

16-2   IEEE Standards Association Membership for 2005
                    http://cipherlabs.freewebspace.com/portfolio/image119.jpg

16-3   IEEE Vehicular Technology Society Membership for 2005
                    http://cipherlabs.freewebspace.com/portfolio/image121.jpg


                                   Cover Page Hyperlink:

                  http://cipherlabs.freewebspace.com/portfolio/image002.jpg


                                              ii
                           CTI
                         CONTENTS

                               1

   PROPOSAL EXAMPLES, SAMPLE QUOTES & SCHEDULES-OF-WORK

                               2

                     ABOUT THE COMPANY…

                               3

                   CONTRACTOR’S FACT SHEET

                               4

                            RESUME

                               5

                PROFILES OF CORPORATE CLIENTS

                               6

               CONTRACT / CONSULTING AGENCIES

                               7

SURVEY OF ELECTRONIC & COMPUTER-AIDED-DESIGN (CAD/CAM) TOOLS &
                          UTILITIES

                               8

          PARTS LIST & BILL-OF-MATERIAL (BOM) EXAMPLES



                               i
               CTI
       CONTENTS CONTINUED


                   9

       PRINTED CIRCUIT BOARDS
          COMPONENT PLACEMENT

        CIRCUIT LAYOUT GUIDELINES

         BENCH TEST PROCEDURES

          CONFIRMATORY TESTING

                   10

           PRINTED CIRCUIT

      ELECTRICAL TEST PLAN (ETP)

                   11

ANALYSIS EXAMPLE: SIGNAL CONDITIONING
  EXHAUST GAS TEMPERATURE SENSOR RANGE

                   12

       ELECTRICAL SCHEMATICS

                   13

          CLIENT REFERENCES
          ANDREW CORPORATION

       FLIGHTSAFETY INTERNATIONAL

         ADDITIONAL REFERENCES




                    ii
            CTI
     CONTENTS CONTINUED


                14

          PHOTOGRAPHS



                15

CERTIFICATES & COMMUNITY RELATIONS



                16

    PROFESSIONAL AFFILIATIONS



                17

      CONTACT INFORMATION




                iii
             CTI 1


PROPOSAL EXAMPLES, SAMPLE QUOTES &
       SCHEDULES-OF-WORK




                1-0
                              CTI
DOC. NO. ___
TITLE: STATEMENT OF WORK FOR PROJECT ID NUMBER ______




                        PROJECT ID NO. (IR-264)

                SUB-COMPACT EPIDURAL ENDOSCOPE




                             PREPARED BY
                    CIPHER TECHNOLOGIES INC.
                    890 CHERRY VALLEY ROAD
                 VERNON HILLS, ILLINOIS 60061-2626



                               FOR THE
                   BIO-MEDICS DEV. CORPORATION
                       3201 ROXY PARK CIRCLE
                  NASHVILLE, TENNESSEE 37918 USA




     17 February 2005
                 Cipher Technologies Inc.




                        STATEMENT OF WORK FOR
                     PROJECT ID NUMBER (TBD) –
               SUB-COMPACT EPIDURAL ENDOSCOPE




PREPARED BY:                                                       DATE:
               Phillip Joseph, Consulting Engineer




                             CIPHER   TECHNOLOGIES INC.
                         890 CHERRY VALLEY ROAD SUITE 302
               VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
            Cipher Technologies Inc.
                      RECORD OF CHANGES

REV.   PAGES CHANGED              DESCRIPTION OF CHANGE             DATE
 -            -              Original Issue                        12-08-04




                        CIPHER   TECHNOLOGIES INC.
                   890 CHERRY VALLEY ROAD SUITE 302
          VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                      Cipher Technologies Inc.

LETTER OF INTRODUCTION


Dear Mr. Najmi,

Thank you for the opportunity to submit a quotation for evaluating your design and
schematics for the EPIDURAL SUB-COMPACT ENDOSCOPE. Specifically, the
objective of the evaluation has been set forth as follows:

      1. Evaluate the electronic circuitry for robustness and manufacturability,
      2. Determine the potential for reducing the board size, i.e. surface area and
         component profile occupied by the present design.

It is my hope that I may be of assistance in helping you meet your requirements
pertaining to this project. I look forward for the opportunity to further discuss the
project details and finalize any specifics or requirement necessary before commencing
the evaluation.



Most respectfully submitted,

Phillip J. Joseph

Phillip Joseph
Consulting Engineer
Cipher Technologies Inc.



/PJ




                                   CIPHER   TECHNOLOGIES INC.
                               890 CHERRY VALLEY ROAD SUITE 302
                    VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                      Cipher Technologies Inc.
1   CONTRACTOR REQUIREMENTS

The contractor shall perform design services and produce data for the customer in
accordance with this Statement of Work (SOW). Services shall consist of providing a
confidential report describing the evaluation and meeting the requirements described
above (refer to the Letter of Introduction).

The contractor shall be available to answer questions and resolve any problems as
necessary.

    CONTRACTOR PROFILE

Contractor expertise is in the design and development of analog and digital electronic
circuits and assemblies. The contractor has been responsible for a number of electronic
designs through the full product development cycle, i.e. from early concepts through
production pilot runs. The contractor has formally trained in designing products for
manufacturability (DFM). The contractor has also led several workshops on this
important subject.

The contractor has spent well over twenty (20) years in the electronics industry, most
recently serving in the capacity of an independent consultant. Early professional years
were in a direct capacity (captive employee) for several Fortune 500 companies. The
contractor has been fortunate enough to work for a number of engineering groups serving
both privately- and publicly-owned enterprises. These companies represent a wide cross-
section or segment of the front-runners leading advances in the high-tech market place.

The contractor completed the post-secondary requirements for a Bachelor and a Master of
Science degree in Electrical Engineering from the Illinois Institute of Technology,
located in Chicago, Illinois. The contractor chose his graduate degree specialty in the
area of Circuits and Electronics.

Involved with various little ‘pet’ projects and gadgets, the contractor is a home hobbyist
and ‘tinkerer’ when time permits.

3 APPLICABLE DOCUMENTS

The following documents form a part of this statement-of-work to the extent specified
herein:

All work will conform to the IPC-D-330 Design Guide for Printed Wiring Boards.




                                  CIPHER   TECHNOLOGIES INC.
                             890 CHERRY VALLEY ROAD SUITE 302
                   VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                    Cipher Technologies Inc.

4 PROJECT DELIVERABLES

  4.1. The customer will receive a confidential report that will summarize the
       evaluation; including the results obtained the conclusions reached, etc. The
       customer will be offered recommendations or suggestions in going forward.

  4.2. Budget and Schedule

     4.2.1. The contractor will provide an estimate of time and costs associated with
            various stages of the evaluation.

     4.2.2. The contractor is responsible for maintaining and reporting schedule
            results and/or deviations as requested.

     4.2.3. The quotation and schedule of work will be submitted in a separate
            attachment accompanying this SOW.

5 DOCUMENTATION REQUIREMENTS

   The report deliverable will be in hard copy and in electronic document form using
   Microsoft Word 2000 Office application. If requested, a Windows NTTM or
   compatible CD-ROM disk will be supplied containing a copy of the evaluation
   report.

6 PROJECT BID FIGURES

  6.1. The total project budget estimate is between $2,550 and $5,640 U.S. dollars.
       These figures are from an estimate of the total man-hours required for project
       completion ranging between 30 and 66 hours with the hourly rate schedule of
       $85 U.S. dollars per hour.

  6.2. The bid figures were obtained without benefit of knowing the complexity of the
       design circuitry, or the number of separate circuit functions/sections contained
       within the design. Eight (8) separate sections or block functions within the
       schematic was the ‘guesstimate’ used in arriving at most of the estimates in the
       quotation. The component count provided for the three circuit boards was
       estimated to be between 125 and 150 parts.




                                CIPHER   TECHNOLOGIES INC.
                           890 CHERRY VALLEY ROAD SUITE 302
                 VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                      Cipher Technologies Inc.
7 TERMS OF AGREEMENT BETWEEN EMPLOYER AND CONTRACTOR

    7.1. The contractor has read the statement of work provided by the customer and is of
         the belief that he/she is qualified to complete the project with excellence.

    7.2. The professional profile of the contractor within this document as well as the
         information describing the services and qualifications, etc. on the CTI website is
         accurate with respect to the contractor’s skills, availability, contact information,
         credentials, etc.

    7.3. The contractor will be prompt and courteous at all times when responding to the
         employer when he/she attempts to contact the contractor.

    7.4. The contractor will invoice and receive payment from the employer for said
         services in a timely fashion, preferably within 4 weeks upon delivery of the
         evaluation to the customer, not to exceed 8 weeks after completion.


8   NOTES




                                   CIPHER   TECHNOLOGIES INC.
                              890 CHERRY VALLEY ROAD SUITE 302
                    VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.



                          2


        ABOUT THE COMPANY…




                         2-0



              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                    Cipher Technologies Inc.
About CIPHER TECHNOLOGIES



Cipher Technologies
incorporated the first year of the new millennium, year 2000, set forth with the
mission to provide the product development and manufacturing community with
the opportunity of securing fast and reliable designs, without the excessive
overhead or the long and costly development cycle. The founder and principal
engineer, P. Joseph, is a graduate of Tufts University, located in Medford,
Massachusetts, from which he received his Bachelors Degree in Electrical
Engineering in 1982 with a specialization in Power Systems. He began his
engineering career with the Components Division of Motorola Inc. in Franklin
Park, Illinois, starting as a quality engineer. A few years later, he moved into the
base development group within the Fixed Products Division located in
Schaumburg, Illinois. During this period he attended the Illinois Institute of
Technology in Chicago, Illinois, where he was awarded a Masters degree in
Electrical Engineering with a concentration in Circuits & Electronics. Mr. Joseph
has spent over twenty years in product development and research groups,
mostly with Fortune 500 companies. He has spent over eleven years designing
communications equipment for major technology leaders such as GTE, AT&T,
and the Boeing Corporation. He has worked on a number of teams developing
wireless communication products. Mr. Joseph has industry experience with
automotive and industrial products, engine control modules, and electronic-power
steering systems. Mr. Joseph's experience includes airborne data recorders and
signal data computers for the military, including safe-arm-and fire devices
developed for several missile defense programs.

With just over thirteen years in consulting, Mr. Joseph has served his community
as Membership Chairperson of the Alumni Extension of the National Society of
Engineers (CAE), and is a past member of the Arizona Council of Engineers and
Scientists. He has served on the Phoenix Urban League Advisory Board for the
Employment Skills Enrichment Consortium. He is a past member of the American
Society for Quality Control (ASQC); he is a past-certified Quality Engineer. He is
a member of the Institute for Electrical and Electronic Engineers (IEEE), the
Circuits and Systems Society of the IEEE (CAS), and the Chicago/Rockford
chapter of the IEEE Consultants' Network. Mr. Joseph was recently a voting
member of the IEEE P1616 (Draft) Standards Committee for Motor Vehicle
Emergency Data Recorders released in September of 2004 (ISBN: 0-7381-4498-
3).




                                CIPHER   TECHNOLOGIES INC.
                           890 CHERRY VALLEY ROAD SUITE 302
                  VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.


                          3


        COMPANY FACT SHEET




                         3-0




              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                   Cipher Technologies Inc.
                                      Professional

Over eighteen (18) years of experience in electronic product design and engineering for
predominantly Fortune 500 companies
Eleven (11) years of experience designing communications equipment; six (6) of those years
developing mobile communications hardware
Over four (4+) years experience in automotive and industrial electronics equipment, i.e.
microprocessor-based engine control modules (ECM), electronic-power steering (EPS)
systems …
Experience in the development of high-quality electronic systems for the defense industry, i.e.
signal data computers, crash and structural data recorders, safe-arm-and-fire-devices …
Experience in the development of medical products and systems driven by advances in
biotechnology
Twelve (12) years of experience as an independent contractor and consultant

                                          Degrees

MSEE awarded from the Illinois Institute of Technology (IIT), Chicago, IL, with a
concentration in Circuits and Electronics, 1988.
BSEE awarded from Tufts University, Medford, MA, 1982.

                                      Certifications

American Society for Quality Control (ASQC) Quality Engineer Certification, 1983

                                       Affiliations

Member of the Institute for Electrical and Electronics Engineers (IEEE)
Member of the IEEE Circuits and Systems Society (CAS)
Past Member of the IEEE Vehicular Technology Society (VT)
Member of the IEEE Consultants’ Network Chicago/Rockford Chapter
Past member of the American Society for Quality Control (ASQC)

                                      Recognition

Listed in the 2002-2003 Edition of Strathmore’s Who’s Who Registry and Global Network




                                 CIPHER   TECHNOLOGIES INC.
                           890 CHERRY VALLEY ROAD SUITE 302
                 VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.

                       Products

       Barcode printers and printing products
     Signal data computers and event recorders
        Electrical Power Steering controllers
         Electronic Engine Control Modules
                    Smart Antennas
                   Beam Simulators
       Cellular (GSM) switch/base simulators
         Subscriber Line Interface Circuits
                   Flight Simulators
            Digital Control Audio Systems
        Cabin attendant/Flight deck handsets
                  Telecom line cards
                  Telecom Test Units
              Microwave radio modems
          Trunked base stations/repeaters
                   RF control boards
      Temperature-controlled crystal oscillators
                    Oven oscillators




              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.


                          4


                   RESUME




                         4-0




              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                        Cipher Technologies Inc.

Professional   Design of analog, digital, and mixed-system industrial, automotive, medical, telecom, wireless, and
 Summary       avionic products/equipment through full development cycle and delivery to manufacturing.
               Concept-to-manufacture. Electronic and PC-driven test and design verification. In-circuit test
               (ICT) design. Broad analog and microprocessor-based multi-layer board experience, some
               embedded application/test software and hardware descriptive languages. Experience with military
               and commercial electronics. Proven record of accomplishment in multi-tasking, meeting project
               schedules, goals. Assertive, motivated and results-oriented. Ability to plan and work
               independently without supervision. Strong technical writing with extensive EMI/EMC background.
               Good interpersonal/communication skills. Solid work ethic. Team player.

 Education                             Illinois Institute of Technology Chicago, Illinois 1988
                                       MSEE Master of Science in Electrical Engineering
                                               Field of concentration: Circuits and Electronics
                                                 Tufts University Medford, Massachusetts 1982
                                        BSEE Bachelor of Science in Electrical Engineering

Professional                   Member of the Institute of Electrical and Electronics Engineers (IEEE)
Affiliations                       Member of the IEEE Circuits and Systems Society (CAS)
                                    Member of the IEEE Standards Association (IEEE-SA)
                                  Member of the IEEE Chicago/Rockford Consultants’ Network
                                     Member of the IEEE Communications Society (COM)


Professional   2002-2003             Under contract to BAXTER HEALTHCARE CORPORATION
Experience     Electrical Engineer
               Fenwal Division, Round Lake, Illinois Design and development of the Automatic, Mixing and Dosing System
               (AMD) for reconstitution, dose metering, and delivery of pathogen-inactivated red blood cells (medical
               instrumentation). Design and development through two revisions of the Sensor Data Acquisition Printed Circuit
               Card, providing the major sensor requirements for the AMD system. Digitized sensor information and status
               provided to master (rack) system controller via the Philips P89C668 microcontroller, Altera MAX7000 128-
               macrocell CPLD, RS-485 serial communications interface, 8-single and 16-differential-ended sensor channels,
               analog-to-digital conversion/signal acquisition circuits, switch-mode and linear DC power regulation. Additional
               design features of the 822-component, 6-layer circuit board include in-system programming (ISP) capability, RS-
               232 serial debug interface, JTAG in-circuit programming and data-download mode, I/O-latched data capture,
               external sensor power supplies. EMI suppression filtering for signal conditioning, toroids, inductors, ferrite
               beads, common-mode block filtering, ESD protection devices, RS-232/485 transceivers, LM12H458 12-Bit
               Data Acquisition System, dual voltage micro-monitor, zero-drift, low-bias, and ultra-low offset op amps,
               precision voltage references, 16-Bit Serial ADC, LDO, switched-capacitor and negative voltage regulators,
               TLC16C550C asynchronous communications element (UART), 14-Bit DAC, ultra high-speed signal line
               drivers/receivers/buffers, low-leakage analog mux. Responsible for all prototype bench and system-specific
               confirmatory testing. Low-level signal and noise measurements. Analysis of test results, evaluation of distortion
               and noise source failure mechanism(s), and successful implementation of corrective-action measures. Extensive
               noise-reduction analyses and EMI studies. Responsible for prototyping, simulation, FMEA, and design
               presentation during formal design reviews. Printed circuit board layout and design support and supervision.
               Responsible for formal documentation including Design Description (43 pgs.) and Electrical Test Plan (33 pgs).
               Knowledge/’hands-on’ experience with ANSI EIA/TIA standards RS-232-C, RS-422-A and RS-485, and IEEE
               1149.1 Joint Test Action Group (JTAG). IPC-D-330 Design Guide - Institute for Interconnecting and Packaging
               Electronic Circuits. OrCAD Family Release 14.0 and 9.2 (Capture CIS), GerbTool Version 12.0, AHDL,


                                        CIPHER    TECHNOLOGIES INC.
                                  890 CHERRY VALLEY ROAD SUITE 302
                     VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
         Cipher Technologies Inc.
MAX+PLUS II 10.2 Baseline, Flash Magic ISP Software Version 1.74 (Embedded Systems Academy), Keil
uVision2 IDE and 8051C Debugger, Philips WinISP Version 2.29, IBM Lotus Notes 6, Microsoft Office
Outlook 2000, Excel 2000, Power Point 2000, Word 2000, Windows NT/97, Windows ME, Publisher 2000,
Internet Explorer 6.0, Xeltek Super Pro 2000+ Universal Programmer, Adobe Distiller/Acrobat 5.0



2001-2002 Under contract to L-3 COMMUNICATIONS, Electrodynamics, Inc.
Electrical Engineer
Electrical Engineering, Rolling Meadows, Illinois Design and development of military aircraft data recorders for
flight-event, crash, and structural data recording. Design and development of arming devices for missile
programs, i.e. Hellfire and Legacy. Hardware consisting of 8/16-bit micros MC68661, 80C286, 8086, 8088,
80287 math coprocessor, and various system peripherals such as 82C284 and 82C84A clock generators,
AM9513A system timing controller, 82C54 programmable interval timer, 82C59A interrupt controller, 82C88
bus controller and 82C87 data bus transceiver, 82C55A programmable peripheral interface (PPI), 8-bit equal-to
comparators, programmable timers. Various memory devices including ASICs, FPGAs, PALs, PLAs, SRAM,
EEPROM, EPROM, NOVRAM, and Flash. FAST, HCMOS, CMOS, HMOS, AC, FACT, ALS, and LS logic
families of buffers, counters, latches, registers, etc. Precision instrumentation and operational amplifiers,
comparators, analog switches, analog and digital data selectors, multiplex, decoders, bus transceivers, line drivers,
parity generators and checkers, bit-rate generators. Various discrete devices including FETs, reference diodes,
switches, rectifiers, bipolars, peak-detectors, tranzorbs, transient voltage suppressors, TVS arrays, pulse
transformers, gap switches, high-voltage capacitors. Responsible for design and development of rocket-deployed
safe-and-arm land-based device. Clean-sheet design of RS-422/485 data communications interface. Design of
safe-separation timing circuits and supply-line low-pass filtering. Clean-sheet design of test circuits, interface
cards, and test cables for safe-and-arm device. Development of automatic and manual test procedures and suites.
Development of layout rules and design guidelines for multi-layered printed circuit boards. Responsible for
coordinating and approving printed circuit designs and FPGA VHDL-93 and test-bench development activities.
Responsible for the re-design of analog and vibration circuit cards (the exhaust gas temperature sensor and
tachometer input-channel circuits processing engine over-speed detection) for next-generation advanced-signal
data computer. Derivative-product development of analog conditioning cards for signal computer. Firmware
modifications to vibration processor circuit card. Responsible for troubleshooting and testing of structural data
collector and crash data recorder utilizing ATE and bench test equipment (i.e. Tektronix logic analyzers).
Analysis of test results, evaluation of failure mechanism(s), and successful implementation of corrective-action.
Responsible for design, simulation, worst-case analysis, documentation and presentation of designs in formal
design review settings. Knowledge of ANSI EIA/TIA standards RS-422-A and RS-485. IPC-D-330 Design
Guide, Institute for Interconnecting and Packaging Electronic Circuits. P-CAD 2001, OrCAD Pspice A/D
Release 9.1, OrCAD (Schematic) Capture, Microsoft Office Outlook, Excel, Power Point, Word 97, Windows
NT/97, Publisher, Internet Explorer 6, Adobe Acrobat 5

2000-2001 Under contract to ZEBRA TECHNOLOGIES CORPORATION
Electrical Engineer
New Product Engineering, Vernon Hills, Illinois Design and development of bar code printing
products utilizing uP-based controller for management and deployment of various label printing
operations and functions including DC stepper-motor drive control, media, ribbon, and print head
sensor circuits. 32-bit Hitachi Super H (SH7790A) RISC engine, DRAM, ASICs, FPGAs,
HCMOS, and LS logic. Design of pulse detection circuits for management of ribbon spindle
speed. Clean-sheet design of control panel test circuits. Derivative product development of next-
generation printer products. Development of component requirements. Precision op amps,
comparators, A/D converters, SMT fuses, econo resets, differential line drivers
and receivers, heat-sinks, various discretes. Responsible for circuit design,


                          CIPHER     TECHNOLOGIES INC.
                    890 CHERRY VALLEY ROAD SUITE 302
      VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
         Cipher Technologies Inc.
simulation, worst-case analysis, design verification and technical documentation. Knowledge of
ANSI EIA/TIA standards RS-422-A, RS-423-A, RS-485, and CCITT Recommendation V.11.
Protel 99 SE Design Explorer and Schematic Capture Version 6.5.2, Electronics Workbench
Professional Edition Version 5.12, MathCAD 2000
Professional, Microsoft Office Outlook, Excel, Word 97, Windows NT Version 4.0, Internet
Explorer 5, Adobe Acrobat 4



2000                             Under contract to MOTOROLA INC.
Electrical Engineer
Automotive and Industrial Electronics Group, Northbrook, Illinois Design and development of electrically-
powered steering assembly utilizing uP-based controller for control of the instantaneous electric current provided
to 3-phase motor in response to various vehicle and sensor inputs. 32-bit Infineon C167CS processor providing
MOSFET-bridge drive and safety-related functions interfaced to power electronics, sensor input-conditioning
circuits, application-specific IC’s, DC-link circuits, and various analog inputs. Precision low-noise op-amps,
comparators, multiplexers, clock drivers, voltage regulators, relays, CMOS transistor switches and drivers, CAN
interface circuits, EEPROM, HEXFETs, and various discrete devices. Common and differential mode chokes
for power and EMC filtering, thermistors, sense resistors and rectifiers. Responsible for circuit analyses, power
dissipation studies, worst-case analyses, PCB layout support, development of electrical test requirements, design
verification testing, specification of component requirements and testing of component prototypes. PWM
modulation techniques and motor speed control technologies. Knowledge of ISO 9141 (K-link), CAN2.0B
(SAE J1583), RS-232 (TIA/EIA-232-F). Mentor Graphics Design Architect and Board Station, Windows 2000,
Microsoft Word 2000, Excel 2000 and Outlook 2000

1996–1999                        Under contract to MOTOROLA INC.
Electrical Engineer
Automotive and Industrial Electronics Group, Northbrook, Illinois Design and development of natural gas and
diesel electronic engine control modules (ECMs) for automotive and high-horsepower industrial, marine, and
locomotive applications. MC68376/MC68302 platform, analog, digital, and mixed signal circuitry for engine
sensor and various I/O functions including spark-drive and timing, injector-firing, fuel and mixer-inlet pressures,
engine speed and position, engine knock, high and low-side drive circuits for lamps and relays. Precision and
low-noise op amps, comparators, multiplex, knock-signal processors, A/D and D/A converters, serial and parallel
FET pre-drivers. FLASH memory, DPRAM, ASICs, several FET technologies including MOS, TEMP, PRO
and TMOS E-FET. Bipolar and CMOS transistor amplifiers and switches, PWM power controllers, precision
voltage references and regulators, data com drivers and controllers. Power devices including transformers,
chokes, coils, ferrites and power resistors. Responsible for circuit development, simulation, verification testing,
troubleshooting and failure-mode analysis. Responsible for development and release of new component
specifications and requirements. Responsible for ECM test procedures. Filter compensation and stability
analysis for fly-back power converter, transient and bode (gain-phase) analyses, control-loop compensation and
stability analysis for linear regulation, worst-case circuit analysis (WCA), failure mode and effects (FMEA).
Knowledge of TIA/EIA-232-F (RS-232) and TIA/EIA-485-A (RS-485), SAEJ1583 (CAN2.0B), SAEJ1587,
SAEJ1939, SAE/TMC J1922, DIN19245 (PROFIBUS). Windows NT/4.0/95/3.1, MicroSim Pspice A/D
8.0/7.1, MicroSim Schematics, MathCAD 8 Professional, Microsoft Excel 4.0, Microsoft Word 6.0, Microsoft
Internet Explorer 3.0, Adobe Acrobat Reader 3.0, Netscape Navigator 3.0, MS-DOS 6.0

1995–1996            Under contract to ANDREW CORPORATION
System Engineer
Research and Development, Orland Park, Illinois Multi-beam cellular and PCS base station
‘smart-antenna’ developed from concept to fully working prototype. Responsible for design of
system and subsystem assemblies including wireless receivers, embedded control electronics,



                          CIPHER    TECHNOLOGIES INC.
                   890 CHERRY VALLEY ROAD SUITE 302
      VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                        Cipher Technologies Inc.
               RF beam switching. Developed software and hardware requirements, features, interface
               requirements and specifications. Responsible for system capacity and throughput analysis, assisted
               in adaptive- control algorithm development. Performance prediction techniques, system test
               procedures, performance analyses for receiving and switching systems. System connectivity and
               mechanical packaging utilizing VME platform.
               Engineering Consultant
               Assisted in establishment of electronics facility, equipment procurement and personnel resources.
               Responsible for specifying electronic, embedded, and RF lab equipment, software development
               tools and packages, research materials, reference and data books. Assisted with staffing and
               personnel search. Reviewed resumes and assisted with interviews of prospective technical staff.
               Design Engineer
               Development of processor-controlled beam selector switch for smart-antenna system and PC-controlled beam
               simulator. Responsible for circuit design utilizing LSI, VLSI, and RF components. Test software development
               and programming. RF system testing of 800 MHz receivers, power-splitters, combiners, attenuators, protection
               circuits, front panel displays. Responsible for PCB layout development. Knowledge of EIA/TIA-204-D,
               ANSI/EIA-152-C, EIA/IS-20-A, TIA/EIA/IS-53-A, TIA/EIA/IS-54-A, TIA/EIA/IS-56-A. Windows 3.1, MS-
               DOS 6.0, CA-Clipper 5.3, EasyPlot, AutoCad 12

               1994–1995                     Under contract to MOTOROLA INC.
               Electrical Engineer
               European Cellular Subscriber Division, Libertyville, Illinois Troubleshooting of cellular switch-base simulator
               implementing GSM Layer 1 transceiver protocols to landline interface. VME bus-based test bed utilizing high-
               speed timing and control logic, DSP56001 speech processing, programmable logic, high-speed memory, buffers,
               timers, discrete logic. Knowledge of TDMA and CDMA modulation techniques, speech and channel coding,
               SSI and SCI data protocols. Corrected state-machine design utilizing combinatorial and registered
               programmable logic using PALASM programmable logic software. Responsible for troubleshooting of
               subscriber landline circuit cards. 6-pole Tschebyshev VF transmit and receive filters, 2-to-4 wire audio hybrids,
               off-hook and ring detection circuits, DTMF generators, A/D and D/A converters, PCM codecs-filters, echo
               cancellation circuits. Transmission testing. Employed EMI noise-suppression and elimination techniques.
               Developed EMI/EMC design guidelines. Developed printed circuit layout guidelines. Knowledge of GSM
               physical layer, GSM 03.50, GSM 05.02, GSM06.10, IEEE Std 743, IEEE Std 823, FCC Part 68, LSSGR
               Section 7-Transmission. OrCAD 3.22, PALASM (MMI), X Window System Motif Edition (X/Motif), Apollo
               Domain OS SR10.3, Frame Maker 4, Interleaf 5.0, UNIX V Release 4, VTRX OS

Professional   1993               Under contract to FLIGHTSAFETY INTERNATIONAL INC.
Experience     System Engineer
(continued)    Simulation Systems Division, Tulsa, Oklahoma Research and clean-sheet design of digital audio system for
               flight simulation of the Boeing-777 digital control audio system. Multi-channel voice and digital sound system
               incorporating signal processors, glue-logic, and 16-bit CPU. Audio distribution, control and processing
               implemented on VME platform. Knowledge of ARINC 429, ARINC 629, EIA RS-232, EIA RS-422, EIA RS-
               423, EIA RS-485, IEEE 488 and P1014 – VME bus C.1, SCSI, AES 3 (ANSI S4.40), AES 5 (ANSI S4.28),
               AES 10 (ANSI S4.43), AES17 (ANSI S4.51) and AES18 (ANSI S4.52). Digital signal processing theory and
               concepts, principles and applications. AutoCAD 12, Microsoft Word 5.5, MS-DOS 3.0


               1992               Under contract to BOEING DEFENSE & SPACE GROUP
               Development Engineer
               Commercial Avionics Systems, Seattle Washington Design and development of cabin attendant/flight-deck
               handsets for the Boeing-777 voice communication and passenger-address cabin inter-phone system. Responsible
               for hardware design and computer-aided design release of handset. Solid-state receivers, amplifiers, DTMF


                                        CIPHER    TECHNOLOGIES INC.
                                  890 CHERRY VALLEY ROAD SUITE 302
                     VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
         Cipher Technologies Inc.
encoders, generators, pre-amplifiers, noise-canceling and directional microphones. Knowledge of RTCA/DO-
160C, DO-170, ARINC 600, ARINC 732, MIL-STD-454, EIA RS-485. Knowledge of acoustic theory and
principles, measurement techniques, specialized audio equipment - Bruel & Kjaer. Mentor Graphics NetEd,
SymEd, QuickSim, AccuSim, AutoTherm, Board Station, Apollo Aegis OS, DOC and All-In-1 Desktop
Publishing, VAX server

1988–1990             AG COMMUNICATION SYSTEMS CORPORATION
Member of Technical Staff
A joint venture of AT&T and GTE, Phoenix, Arizona Development of analog and digital line and test cards for
enhancing and maintaining GTD-5 digital switch equipment. Responsible for embedded firmware and hardware
development, simulation, and prototype testing of next-generation facility test unit cards. Intel 8051 MPU, A/D
and D/A converters, pulse-tone dialers, phase-locked loops, voice-frequency filters, clock oscillators, HCMOS,
HCTMOS and ALS logic families. Firmware developed on MCS-51 development system with MICE
Emulator-II, Mice Symbolic Debugger. Responsible for development of auxiliary feature line card employing
‘cutting-edge’ technology. COMBOs, CODECs, switched-capacitor filtering, timing and sequencing control
circuits, tone detection and protection devices, line interface electronics. Knowledge of LSSGR, UL, REA, FCC
Part 68, CCITT, ISDN specifications, DS-0 and DS-1 Line Signal Standards, D2/D3 signaling, Foreign
Exchange (F/X), Bell Core Method 1 Reliability. PL/M-51 programming language, BRIEF Text Editor,
TSO/SPF, Mentor Graphics NetEd, QuickSim, Analog Workbench, Interleaf, 8051 assembly, MS-DOS, VAX
11/780

1982–1988                            MOTORLA INCORPORATED
Electrical Engineer
Communications Division, Schaumburg, Illinois (1986-1988) Development of trunking modems from concept
through manufacture. Design of circuits for base band transmit and receive modem cards. Responsible for
design of 7-pole voice-frequency active filter, input and output conditioning, balanced receivers, audio amplifiers,
and level-shifting attenuators. Assisted with design of 3825-Hz signaling, phase-shifters for signal modulation and
IF recovery, band pass filtering and 4.96 MHz voltage-controlled crystal oscillator reference. Responsible for
output filtering, alarm circuits (over-current, under-voltage) for power converter module. Responsible for circuit
simulation.       Filter worst-case, sensitivity, and Monte-Carlo analyses.             Knowledge of receiver
modulation/demodulation including carrier synchronization techniques. General Analysis Simulation (GAS),
SPICE, Mentor Graphics NetEd, Fortran IV, Macintosh Word Perfect, VAX 11/780
Systems Engineer
Communications Division, Schaumburg Illinois (1985-1986) System design and analysis of multi-site 2-way
radio communications systems utilizing trunked base station repeaters. Responsible for system testing and
evaluation, troubleshooting and system documentation. Detailed system descriptions, system and site block
diagrams, equipment interface and connection diagrams, audio and signal level-setting procedures, unique system
information. Hewlett-Packard CAD workstation, MS-DOS
Electrical Engineer
Communications Division, Schaumburg, Illinois (1985) Hardware test and product verification for next-
generation international base station RF control cards. Responsible for test and trouble shooting of analog, digital,
and radio-frequency (IF) circuits, failure-mode analysis and resolution. Responsible for 800-MHz base station
field-testing. Mobile radios, duplexers, power combiners, isolators, and circulators. MS-DOS, Macintosh Word
Perfect, Hewlett-Packard HP BASIC
Quality Engineer
Components Division, Franklin Park, Illinois (1982-1985) Design of quality systems for frequency-
selective components. Crystals, substrates, reeds, temperature-controlled and ovenized oscillators.
Instructor in Manufacturing Skills Training Seminar series. ASQC Certified Quality Engineer, 1983.
MS-DOS, Word, HP ATE System




                          CIPHER    TECHNOLOGIES INC.
                    890 CHERRY VALLEY ROAD SUITE 302
      VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.



                          5


PROFILES OF CORPORATE CLIENTS




                         5-0




              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                      Cipher Technologies Inc.

                            Profiles of Former Clients & Partners

Baxter International Inc. operates as a global medical products and services company with
expertise in medical devices, pharmaceuticals and biotechnology to assist healthcare
professionals and their patients with the treatment of complex medical conditions, including
hemophilia, immune disorders, infectious diseases, cancer, kidney disease, trauma and other
conditions. The Company's continuing operations consist of three segments: Medication Delivery,
which provides a range of intravenous solutions and specialty products that are used in
combination for fluid replenishment, general anesthesia, nutrition therapy, pain management,
antibiotic therapy and chemotherapy; Bioscience, which develops biopharmaceuticals, biosurgery
products, vaccines and blood collection, processing and storage products and technologies for
transfusion therapies, and Renal, which develops products and provides services to treat end-
stage kidney disease.


                      Industry       Medical Instruments & Supplies
                      Employees 51,300


                                             *****
L-3 Communications Holdings, Inc. (L-3) is a supplier of a range of products used in a number
of aerospace and defense platforms. It is also a supplier of subsystems on platforms, including
those for secure communication networks; mobile satellite communications; information security
systems; shipboard communications; naval power systems; fuses and safety and arming devices
for missiles and munitions; microwave assemblies for radars and missiles; telemetry and
instrumentation, and airport security systems. In addition, the Company is a prime system
contractor for aircraft modernization and maintenance; intelligence, surveillance and
reconnaissance (ISR) collection platforms; simulation and training, and government systems
support services. L-3's four operating segments include Secure Communications and ISR;
Training, Simulation and Support Services; Aviation Products and Aircraft Modernization, and
Specialized Products.


                         Industry       Communication Equipment
                         Employees      38,700


                                             *****
Motorola, Inc. is a global provider of wireless, broadband, automotive communications
technologies and embedded electronic products. It provides software-enhanced wireless
telephone and messaging, two-way radio products and systems, as well as networking and
Internet-access products, for consumers, network operators and commercial, government and
industrial customers. The Company also provides end-to-end systems for the delivery of
interactive digital video, voice and high-speed data solutions for broadband operators, and
embedded semiconductor solutions for customers in wireless communications, networking and



                                    CIPHER   TECHNOLOGIES INC.
                              890 CHERRY VALLEY ROAD SUITE 302
                    VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                       Cipher Technologies Inc.
transportation markets. In addition, Motorola offers integrated electronic systems for the
automotive, telematics, industrial, telecommunications, computing and portable energy systems
markets.

Motorola, Inc.


                          Industry       Communication Equipment
                          Employees      88,000


                                        *****
Andrew Corporation is a global supplier of communications products and systems to the
wireless subsystem infrastructure market. The Company classifies its offerings into five product
groups: Antennas, Base Station Subsystems, Cable Products, Network Solutions and Wireless
Innovations. The Antenna group products include base station antennas, earth station antennas,
multi-band antennas and point-to-point antennas. Base Station Subsystems products are integral
components of wireless base stations. Cable Products include coaxial cables, connectors, cable
assemblies and accessories. Network Solutions includes software and equipment to locate
wireless 911 callers, as well as equipment and services for testing and optimizing wireless
networks. Wireless Innovations products are used to extend the coverage of wireless networks in
areas where signals are difficult to send or receive and include both complete systems and
individual components.

                          Industry       Communication Equipment
                          Employees      7,228



                                        *****
Zebra Technologies Corporation is in the business of making products that enable companies
and organizations to improve productivity, deliver better customer service and provide security
that is more effective. It designs, manufactures and supports a range of direct thermal and
thermal transfer bar code label and receipt printers, radio frequency (RF) identification
printer/encoders, card imaging printers and digital photo printers. The Company also sells related
specialty bar code labeling materials, ink ribbons for bar code and card printers and bar code
label design software. These products are used principally in automatic identification, data
collection and personal identification applications, and are distributed worldwide through a
network of resellers, distributors and end users representing a wide cross-section of industrial,
service and government organizations.




                                     CIPHER   TECHNOLOGIES INC.
                               890 CHERRY VALLEY ROAD SUITE 302
                     VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                       Cipher Technologies Inc.
Zebra Technologies Corporation


                            Industry         Computer Peripherals
                            Employees        2,200



The Boeing Company, together with its subsidiaries, is an aerospace company that operates in
six principal segments: Commercial Airplanes, Aircraft and Weapon Systems, Network Systems,
Support Systems and Launch and Orbital Systems (collectively, Integrated Defense Systems
(IDS)) and Boeing Capital Corporation (BCC). The Commercial Airplanes operations principally
involve development, production and marketing of commercial jet aircraft and providing related
support services, principally to the commercial airline industry worldwide. IDS' operations
principally involve research, development, production, modification and support of products and
related systems, including military aircraft, helicopters and missiles, space systems, missile
defense systems, satellites and satellite launching vehicles, rocket engines and information and
battle management systems. BCC is primarily engaged in the financing of commercial and private
aircraft and commercial equipment.


                Industry       Aerospace/Defense - Major Diversified
                Employees 157,000


                                       *****

Lucent Technologies Inc. (Lucent) designs and delivers the systems, services and software that
drive next-generation communications networks. Lucent has three business segments organized
around the products and services it sells: The Integrated Network Solutions (INS), Mobility
services and Services segment. The INS segment provides a broad range of software and wire
line equipment related to voice networking (primarily consisting of switching products and voice
messaging products), data and network management (primarily consisting of access and related
data networking equipment and operating support software) and optical networking. Mobility
provides software and wireless equipment to support radio access and core networks. Services
are a worldwide service organization that provides deployment, maintenance, professional and
managed services in support of both product offerings, as well as multi-vendor networks.

AG Communication Systems, a subsidiary of Lucent Technologies, is a leading developer
and manufacturer of advanced telecommunication products and services, including access,
wireless and intelligent network products. AG Communication Systems’ GTD-5b digital switching
systems, serve more than 17 million customers worldwide in business, industry and government,




as well as subscribers serviced by the public telephone network. Annual revenues for the fiscal
year ended September 1997 were $400 million.




                                    CIPHER   TECHNOLOGIES INC.
                              890 CHERRY VALLEY ROAD SUITE 302
                    VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                         Cipher Technologies Inc.
AG Communication Systems


                         Industry         Processing Systems & Products
                         Employees        31,800

PRESS RELEASE:                                               FRIDAY JANUARY 23, 1998

AG Communication Systems to provide advanced videoconferencing
products for Lucent Technologies

WASHINGTON, D.C., (ComNet '99) - Lucent Technologies (NYSE: LU) and AG Communication Systems, a
subsidiary of Lucent Technologies, today announced an OEM agreement for a new multiple voice line
solution. Called the SuperLine™ Access System, this solution enables service providers to deliver up to
two additional phone lines to residential and small office/home office (SOHO) customers over the same
copper wire used today for their existing phone service.




                                       CIPHER   TECHNOLOGIES INC.
                                 890 CHERRY VALLEY ROAD SUITE 302
                      VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.


                          6


   PAST CONSULTING AGENCIES




                         6-0




              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                         Cipher Technologies Inc.
                          CONSULTING-CONTRACTING AGENCIES


Name                                    Professional Relationship             Dates

Dale Schoenbeck                         Senior Vice President                 2002 - 2003
Accord Consulting Service Inc.
10301 W. Roosevelt Rd.
Westchester, Illinois 60154
Bus. (708) 345-7900
Baxter Healthcare Corp.

Steve Bauer                             Branch Manger
Tech Staff of Illinois
804 East Park Avenue
Libertyville, IL 60048
(847) 816-0500

Formerly:
Randall Reed                            Recruiter                             2001 - 2002
Tech Staff of Illinois
9801 West Higgins Road
Suite 580
Rosemont, Illinois 60018-4732
(847) 692-3090
L-3 Communications

Ed Gaeke                                Human Resources Manager               2000 - 2001
ESPO Engineering
855 Midway Drive
Willowbrook, IL 60527
(630) 789-2525
Zebra Technologies Corporation

Steve Bauer                             Branch Manager
Tech Staff of Illinois
804 E. Park Ave.
Libertyville, IL 60048
(847) 816-0500

Formerly:
Joseph Hubbard                          Senior Account Representative         2000
Tech Staff of Illinois
9801 West Higgins Road
Suite 580
Rosemont, Illinois 60018-4732
(847) 692-3090
Motorola AIEG




                                     CIPHER   TECHNOLOGIES INC.
                                 890 CHERRY VALLEY ROAD SUITE 302
                     VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                         Cipher Technologies Inc.
Name
                                       Professional Relationship              Dates
Rose Mazza                             Account Executive                      1996 - 1999
Pollak & SKAN Group
25 Northwest Point Blvd.
Suite 950
Elk Grove Village, IL 60007
(708) 437-0909
Motorola AIEG

John P. Fortino                        Account Executive                      1995 - 1996
Pollak & SKAN Group
25 Northwest Point Blvd.
Suite 950
Elk Grove Village, IL 60007
(708) 437-0909
Andrew Corporation

Aerotek CE (#808)
1125 Tri-State Pkwy.
Suite 710
Gurnee, Illinois 60031
(847) 782-5430
(888) 494-9343

Formerly:
Adam Szczepanski                       Contracts Manager                      1994-1995
Aerotek Contract Engineering
3701 Algonquin Road
Suite 780
Rolling Meadows, Illinois 60008
(847) 590-9595
Motorola Libertyville

Joyce (Endicott) Coble                 Manager, Marketing and                 1993
Wyatt & Associates Inc.                Recruiting
9235 E. Harry, P.O. Box 782500
Wichita, Kansas 67278-2500
(316) 682-6740
(800) 762-1421
Flight Safety International
EDC Inc.
419 Emmerling Place
Friday Harbor, WA 98250
(360) 378-8433
Formerly:                            Contracts Manager                        1992
(206) 657-0497
Tukwila, Washington
Boeing Commercial Aircraft Group (BCAG)


                                   CIPHER   TECHNOLOGIES INC.
                              890 CHERRY VALLEY ROAD SUITE 302
                     VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.




              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
         Cipher Technologies Inc.


                                 7


SURVEY OF ELECTRONIC & COMPUTER-AIDED-DESIGN
          (CAD/CAM) TOOLS & UTILITIES




                                7-0




                     CIPHER   TECHNOLOGIES INC.
                890 CHERRY VALLEY ROAD SUITE 302
       VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                   Cipher Technologies Inc.

Document: Electronic Design Tools-Business Utilities-Software Applications
Original Draft:   January 26, 2005
Page: 1 of 3
                                                                 Rev: 0.0
________________________________________________________________

This document identifies and provides a brief description of some of the standard
electronic design and computer-aided-design (CAD) tools and software
applications available and/or recommended for use at Cipher Technologies Inc.
Several business platforms/utilities that are recommended for reports,
presentations, electronic and/or hard copy communications are also included.

1. Analog Circuit Analysis
WinSpice3 is a general-purpose circuit simulation program for non-linear DC,
non-linear transient, and linear AC analyses. Circuits may contain resistors,
capacitors, inductors, mutual inductors, independent voltage and current
sources, four types of dependent sources, lossless and lossy transmission lines
(two separate implementations), switches, uniform distributed RC lines, and the
five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and
MOSFETs. WinSpice3 is utilized in our analogue circuit design and electronic
modeling.

2. Printed Circuit Board (PCB) Layout and Design
CADintPCB is currently recognized as one of the best layout and schematic tools
currently available for Printed Circuit Board layout and schematic capture,
delivering a suite of functionality that was only available with heavy-duty
engineering work stations in the not too distant pass. CADintPCB allows
“dimming” of various board layers while viewing them on the workstation monitor,
rendering them opaque and resulting in the ability to view other layers
unobstructed. CADintPCB allows 3-dimensional viewing of the circuit board. We
can review the circuit board with your engineering team with all the components
placed in real 3-D viewing before the drawings and drill tapes go to fabrication.
Observing the results of ‘possible’ layout errors or issues, the appropriate
component placement, the correct height and size (footprint) of the part, and the
desired component version, can result in considerable cost savings to you. The
ability to make crucial corrections before the printed circuit boards are ‘fabbed’
can most likely save the design team weeks in ‘hunting-down’ and finding the
right component substitutions or replacements. At the minimum, we should be
able to save the build at least a “pass” or two. With the current cost of PCB




                               CIPHER   TECHNOLOGIES INC.
                          890 CHERRY VALLEY ROAD SUITE 302
                 VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                    Cipher Technologies Inc.
Document:                                                    Electronic Design Tools-
Business Utilities-Software Applications
Original Draft: January 26, 2005
Page: 2 of 3                                                               Rev: 0.0

fabrication prices, this may easily result in a savings of tens of thousands of
dollars.

3. Computer Operating Systems
Windows ME (Millennium Edition)

4. Reports and Presentations
Microsoft Word 2000 (9.0.6926 SP-3) for Microsoft Publisher 2000 SP-3

5. Tables, Spreadsheets, Selected Mathematical Computations (i.e. FMEAs)
Microsoft Excel 2000 (9.0.6926 SP-3)

6. Publications and Distributions
Adobe Acrobat/Distiller 5.0.0

7. FPGA Development (i.e. coding, programming, testing, fault-simulation)

7.1    AHDL (Altera’s High-Level Design Language)
7.2    VHDL (VLSI High-Level Design Language)
7.3    MAX+PLUS II 10.2 Development Environment for FPGAs

8. Microprocessor Development, Modeling, and Test

8.1    Embedded Systems Academy’s (ESA) Flash Magic ISP In-System
       Programming Software Version 1.74
8.2    Keil uVision2 IDE and 8051 “C” Debugger
       The Philip Corporations’ WinISP (In-Systems Programming for
       Windows) Version 2.29

9. Business Communications: Email, Web Access, Reports, Memos, Informal
   Correspondence
Microsoft Office Outlook, Microsoft Outlook Express, Internet Explorer
6.0.2800.1106, Netscape 8.0




                                CIPHER   TECHNOLOGIES INC.
                           890 CHERRY VALLEY ROAD SUITE 302
                  VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                    Cipher Technologies Inc.

Document: Electronic Design Tools-Business Utilities-Software Applications
Original Draft: January 26, 2005
Page: 3 of 3                                                    Rev:0.0
________________________________________________________________

fabrication prices, this may easily result in a savings of tens of thousands of
dollars.

The originator is expected to document any addendum or changes to this policy
in a timely and expeditious manner.

Date:                Type:                   Originator:          Summary:

1
2
3
4
5




                                 CIPHER   TECHNOLOGIES INC.
                             890 CHERRY VALLEY ROAD SUITE 302
                  VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
        Cipher Technologies Inc.


                                8


PARTS LIST & BILL-OF-MATERIAL (BOM) EXAMPLES




                               8-0




                    CIPHER   TECHNOLOGIES INC.
               890 CHERRY VALLEY ROAD SUITE 302
      VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
     Cipher Technologies Inc.




8-1 Bill-of-Material for Stepper Motor Control PCB Design




                 CIPHER   TECHNOLOGIES INC.
            890 CHERRY VALLEY ROAD SUITE 302
  VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.



                          9



      PRINTED CIRCUIT BOARDS


     9.1 CIRCUIT LAYOUT GUIDELINES

       9.2 COMPONENT PLACEMENT

      9.3 BENCH TEST PROCEDURES

       9.4 CONFIRMATORY TESTING




                         9-0




              CIPHER   TECHNOLOGIES INC.
         890 CHERRY VALLEY ROAD SUITE 302
VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                         Cipher Technologies Inc.


CTI
Date:   December 20, 2004
To:     Gene McDonald @ CADinc
Cc:     M. Park, P. Hunter @ Bio-Medics
From:   Phillip Joseph
Subject: Name of New Product Design: PCB Layout Guidelines



1 Description of the New Circuit
(A brief description of the assembly, product, or sub-system for which this printed circuit board or
PCB is currently in development for.)

2 Conductor Layout Guidelines

2.1 Multi-layer Printed Wiring Boards

A multi-layer board should be used with internal conductor layers. Each layer should be
separated by a power or ground plane. Every available square inch of the printed circuit board,
which does not contain circuits or conducting runs, should be ground plane. If the circuit density
is too high, the density must be reduced in order to create more ‘real estate’ for the ground plane.
This will help to insure a uniform dielectric field for the conductors, thereby minimizing capacitive
or electric coupling and the interaction of electric fields between the circuits located on the PCB.

2.2 USE the Ground Plane Liberally

It has been shown that analog-to-digital coupling noise is reduced by at least 30 dB if regions
between analog signal traces are filled with copper and then electrically attached to the analog
ground plane.

2.3 Conductor Layers (a.k.a. Signal Traces)

Adjacent conductor layers (whether analog or digital) should ‘run’ perpendicular to each other and
cross at right angles. This will minimize parallel runs and subsequently reduce crosstalk and
interference. Adjacent is where each pair of layers is assumed to be sandwiched between power
and/or ground planes.

2.4 Power and Ground Conductors (Supply Leads)

Power supply and ground leads should be heavy and well located. The supply and ground-return
traces must be routed in such a way as to achieve maximum (horizontal) isolation from the other.
The supply and ground-return leads should not cross one another on the different layers of the
PCB.



                                     CIPHER   TECHNOLOGIES INC.
                                890 CHERRY VALLEY ROAD SUITE 302
                     VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
                        Cipher Technologies Inc.
2.5 Routing Supply Lines
Maintain a ground plane directly underneath (along the vertical axis) the supply line or trace. In
the previous section, we spoke about keeping ground and supply isolated as much as possible -
in the HORIZONTAL plane. Maintaining a ground directly vertical to each supply line, the supply
line can be kept at its LOWEST characteristic impedance, where electrically Z0 = (L/C)-1/2. This
keeps the capacitance high and the inductance low. Strategically located bypass capacitors can
further increase the capacitance in the equation, thus lowering the supply impedance.

2.6 Routing Either Signal or Power Supply Lines

Avoid allowing a signal and especially a supply trace to travel without a close ground-return:
utilize either a trace or solid plane. This is not always easy in analog or mixed-signal circuits,
however this is where it can be most critical.

2.7 The Best Routing for Ground Conductors

The ground conductors should be parallel to each other in the PCB (use either a grid or plane
configuration). Make the ground plane as wide as possible. Avoid right angle bends in the
primary ground conductors. Of course, apply ground liberally where possible on the other layers
as well.

2.8 The Benefits of Using a Ground Plane or Grid

By using the largest ground areas as possible, the “copper lands” then function as noiseless
shields. A low inductance path to ground for the power supply is also provided for. A ground grid
can be similarly effective (it’s the positive and negative potentials that should not cross or overlap)
by providing many parallel paths for the ground return currents, thus minimizing the ground
inductance. This inhibits high-frequency noise coupling.

2.9 Ground Plane Voltage Differentials

Two grounds are seldom at the same potential; therefore, the difference in ground potentials will
invariably couple into a circuit if the circuit is grounded at more than a single point.
Interrupting or splitting the ground plane will produce a voltage difference across the split or
opening. This voltage difference can exceed several hundred millivolts in the case of TTL and
ECL technologies. This level of energy can seriously compromise the performance of voltage
sensitive IC’s. If an interruption is unavoidable, install a wire across the cut or separation in the
ground thereby reducing the loop area and thus the troublesome ground inductance.

2.10 Good Grounding When Using Different Supply Voltages

The grounds for each supply should be kept separate and each ground should then be separately
returned to its respective supply. This is especially true when using one supply to power the
analog circuits and another supply to power the digital circuits. Do not connect the two grounds
first and then return a single ground line to the power supply.

2.11 Mixed-Signal Layouts

Use separate voltage supplies for circuit cards that contain both analog and digital circuits.




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2.12 When to Split the Ground Plane

It is advantageous for the ground planes of the analog supply and the digital supply to be SPLIT
and located on the same layer when possible. The analog and power circuits should be situated
above the analog ground plane and the digital circuits and supplies placed above the digital
ground plane. This concept can be extended to circuits powered by different supplies as well.
Connect the separate ground planes at ONE point only (in most cases). The distance between
the planes should be at least 1/8 inch wide. Make vias available in the PCB to allow alternative
connection points.

2.13 Analog and Digital Planes

For boards with more than two layers, the analog and digital-related planes should not overlap.
Do not place a plane, which crosses the split between the analog ground plane and the digital
ground plane. If you do, you are providing a bridge or conduit for analog-to-digital coupling.

2.14 When NOT to use the Ground Plane Liberally

Do not place an electrical ground plane or trace in between adjacent pins of a DIP, SOIC, or any
other monolithic IC package.

2.15 Ground the Oscillator

Sources of continuous emissions such as oscillator components should be housed in metal
enclosures and grounded to frame ground. Avoid connecting the source clock through analog
multiplexers, CPLD’s, PAL’s, FPGA’s, gate arrays, or circuits similar to these and then
subsequently to another clock input. These circuits have a tendency to induce clock noise and
phase jitter.

2.16 Minimum Conductor Trace Lengths and Conductor Spacing Distances:

2.16.1 Spacing between internal, straight, parallel conductors: 15 mils minimum.

2.16.2 Spacing between internal pads and between conductor and pad (including component
       pad or even via): 30 mils minimum.

2.16.3 Spacing between interconnecting signal lines for digital circuits: 6 inches maximum (to
       avoid ringing).

2.16.4 Spacing between the signal lines connecting HCMOS logic with LSTTL logic: 10 inches
       maximum.

2.16.5 Maximum trace or conductor length for circuitry composed of LSTTL gates: 15 inches
       maximum.

2.16.6 Spacing between any metallic structure attached to the PCB and the closest conductor
       (including ground and power planes): 2 centimeters minimum including air spacing.




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3.0 Component Layout Guidelines

3.1 Component Legends

The usefulness and utility of a component legend (especially for a first article or bread board)
cannot be over-estimated. Please provide a component legend in any area where components
are present.

3.2 Common Circuit Groupings

Circuitry which has been grouped on the schematic as comprising common functions and that
share common functionality should be grouped accordingly and as close as possible. Priority
should be given to keeping the components listed together at the group level and keeping the
groups close together on the board.

3.3 Fast Digital Circuits Should Be Close to the Connector

In order to balance common-impedance coupling, radiation, and cross-talk, locate the higher-
speed logic circuits as close to the connector as possible and the low-speed logic and memory
furthest from the connector (if applicable). The exception is when using isolation transformers,
filters, or opto-isolators to reduce the incoming noise levels. Of course, in this case, these types
of components take priority and should be placed as close to the connector as possible.

3.4 Use Multiple Grounds and Power Pins on the Connector

The connector pin of the PCB can introduce noise problems. A varying current will produce a
substantial IR drop with sufficient contact resistance of the conducting pin. Using multiple ground
pins lowers the resulting contact resistance and subsequently can help alleviate potential drops.
Using multiple power pins has the effect of paralleling and thus neutralizing the IR drops. This
applies especially to +5V supplies, VCC or VDD.

3.5 More about the Connector

For a one-connector system (to the outside world) avoid the configuration of having the analog
circuits near the connector and the digital signals at the opposite end of the card and vice-versa
(except hi-speed digital circuits should be close to the connector). Either situation will result in the
analog and digital paths passing in close proximity to one another. The solution then is to
separate and place the digital set and analog set of components nearly equidistant and on either
side of the connector (see Figure 2)

3.6 Digital Circuits Can Corrupt Voltage References and Seriously Compromise Signal
Integrity

Keep the digital circuits as far away as possible from voltage references and analog input pins.

3.7 Unused Logic Gates

Unused logic inputs should be connected to either ground or a reference supply through a series
resistor. This can prevent unnecessary switching and random noise generation.



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3.8 Placement of the Clock and Timing Circuits

It is advisable to locate the timing circuits near the center of the printed circuit board especially
when connected to major circuit components of the board. A central location not only helps to
minimize the paths for the digital signals but also helps assure minimum path lengths.

3.9 Keep Digital Circuits and Analog Circuits Separated

Keep the analog and digital signal traces as physically separate as possible to minimize cross
talk between the two. Keep digital signal lengths to a minimum, lowering the likelihood of
coupling to the analog circuits. If the two different types of signals have to cross, they should do
so at right angles to minimize interference. (Remember Maxwell’s equations and the “right-hand
rule” for magnetic and electrical coupling). If analog circuits must be on the same PCB as digital
circuitry, partition the board with all analog components grouped together in one area and all
digital components in the other. Common parts like power supply-related components should be
centrally located.

3.10 Mixed-Signal Components

The mixed-signal components (i.e. an A/D converter or a PCM CODEC) should bridge the
analog/digital partition with the analog IC pins located in the analog area only and the digital IC
pins located in the digital area only.

3.11 Comparators and Operational Amplifiers

A comparator is considered an analog device (it’s only an amplifier) although in many cases it is
used to condition an analog line on it’s way to becoming a digitized representation. Keep
comparator input lines as short as possible in order to minimize output noise resulting from the
high input-impedance of these amplifiers.

3.12 Clock Lines for the Digital Circuits

Please keep the clock lines as short as possible. High-frequency clock signals can radiate
excessive broadband EMI if they are too long. Avoid multiple or asynchronous clocks when
possible.

3.13 CPLD’s, ASICs, FPGA’s, PALs and Other Such Creatures

These programmable array devices tend to generate an appreciable amount of heat due to
internal power dissipation. In fact, FPGA’s tend to run hotter than Asics’s. These devices should
be well spaced and PLACED on the layout in order to maximize the air-circulation around them.
This will benefit the amount of current drain required from the voltage supplies and extend the
longevity of the programmable devices and the longevity of the components in close enough
proximity to these hot spots.

4.0 Cables

4.1 Conductor Length

For good electric field shielding, minimize the length of the conductor that extends beyond the
shield, and provide a good ground on the shield. Use multiple ground connections if the cable is
longer than one-twentieth of a wavelength. It is desirable to connect the shield and signal


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conductors together at just one point. This point should be one in which the noise currents from
the shield do not have to travel down one of the signal conductors to get to ground. If the current
return of the circuit is through the shield instead of the ground plane, use coaxial cable in order to
have effective magnetic shielding. In a two-conductor system, decrease the area of the loop by
using twisted pair. See Figure 3.

4.2 Grounds Should Be Soldered

Hardware grounds produced by intimate contact, such as welding, brazing, or soldering are
superior to those made by screws and bolts.

5.0 A Few Techniques for Noise Reduction and Suppression

5.1 De-coupling Filters:

Resistor-capacitor and inductor-capacitor de-coupling networks can be used in order to isolate
the susceptible circuits from the power supply, and to keep power supply noise from entering the
circuits. L-C filters usually provide more filtering for the same decrease in power supply voltage;
the voltage drop in the resistor (and in the resistance of the inductor) causes a decrease in power
supply voltage. However, the inductor must be able to pass the DC current in the circuit without
saturating. The dissipative filter is usually more desirable than the reactive filter. In the R-C filter
the noise energy is dissipated as heat. In the reactive filter, the noise voltage appears across the
inductor instead of the load; in effect, the noise voltage just moves to a different location. The
noise voltage across the inductor can be radiated and become a problem in some other part of
the circuit. A shield may then have to be employed in order to eliminate the radiation.
Adding a second capacitor to the RC or LC filter network increases the ratio of filtering-to-noise
fed back to the power supply from the circuit. What results is a pi-network filter.

5.2 Ferrite Beads

Ferrite beads are an inexpensive and convenient means to add high-frequency loss in a circuit
without introducing power loss at DC and low frequencies. The beads are small and can be
simply slipped over a component lead or conductor. They are usually most effective for providing
attenuation to unwanted signals above 1 MHz. Ferrite beads can provide high frequency de-
coupling, parasitic suppression, and shielding. High frequency oscillations caused by switching
transients, or parasitic resonance (s) within a circuit are prime candidates for damping by ferrite
beads. They can also be useful in preventing high-frequency noise from being conducted in a
circuit on the power supply or other leads.

5.3 Isolation Transformers

Inserting an isolation transformer can break ground loops between two circuits. This may not be
practical, for instance, in some circuits where direct current (or very low frequency continuity) is
required between the two circuits. In this case, a transformer can be used as a longitudinal
choke. The transformer when used in this fashion presents low impedance to the signal current
and this allows dc coupling. However, the transformer at the same time presents high impedance
to the longitudinal or common mode noise currents.

5.4 De-Coupling Capacitors

Totem-pole output circuits (i.e. TTL logic) experience a short time during their switching when
both output transistors are “on”. This results in a low-impedance connection between the chip’s


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power supply and ground. A power-supply current spike of anywhere from 10 to 100 milliamps
can result each time the circuit changes state. A de-coupling capacitor provides an additional
source of current, preventing disruptive power supply voltage transients from occurring. The
loads seen by these output circuits are also largely capacitive, requiring large charging currents.
These currents can be provided by the de-coupling capacitor.

 The de-coupling capacitor should not be placed more than ½ inch away from the associated IC
package and as close to the IC’s pins as possible. The de-coupling component leads should be
as short as possible and kept to less than 2mm in length (surface-mount ceramic chips are
usually ideal when usable for this purpose). Low frequency de-coupling can be achieved with a
good aluminum electrolytic or tantalum capacitor anywhere from 3 to 20 microfarads. One each
should be assigned to each power-supply voltage. An additional power supply de-coupling
capacitor from 10 to 100 micro- farads should be used on each printed wiring board where the
power enters the board. For high frequency de-coupling, capacitor values between 0.02 and 0.1
microfarads should be used.




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                                          Bibliography




IPC-2221, “Generic Standard on Printed Board Design”, ANSI/IPC-2221, February 1998, Northbrook,
Illinois. (www.ipc.org)


Ott, H.W., “Noise Reduction Techniques in Electronic Systems,” John Wiley and Sons, New York,
1976.


Karkowski, A. and Toy, D., “Electronic Techniques Manual”, GTECSC, Phoenix, 1988.




                                  COMPONENT PLACEMENT




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RS-422 COMPONENT PLACEMENT ARRANGEMENT




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          BENCH TEST PROCEDURES




 EXAMPLE PROTOTYPE TEST PROCEDURE:




HONDA EPS -- CONTROL PCB TESTS


         Code Version. 2000cntrl test2-rev3a

         Serial Number _________________

         Design Level __________________

         Inspected By __________________

        Date Inspected _________________

         Location _____________________




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 SCOPE The various manual bench tests within this document do not intend to provide 100% test coverage, but the testing will have
sufficient coverage so that the hardware supplied by Motorola, with a reasonably good confidence level, should operate as intended.

OBJECTIVE Specify methods and create a recording document for board level testing of the initial Honda EPS Control printed circuit
    board, before shipment to Sterling Heights for software/hardware/system integration/vehicle testing.

TESTS

I. VISUAL INSPECTION

1. Verify that all diodes, Zeners diodes, ICs, tantalum caps, electrolytic caps, connectors are properly oriented, result
2. Inspect for solder shorts, cold solder, insufficient solder, notes
3. Check for damaged components, PCB traces, components sitting on the board properly, notes
4. Verify that the board has a unique serial number, s/n
5. Identify test connector pins 1, 7, 8, and 14 on back & front sides of board with permanent markings, applied?
6. Verify, that both the sensor connector is mounted at a right angle to the board, result
7. Verify that the reset pull down resistor R3 12 is not placed, verified?
8. Verify that the reset filter capacitor, C3 12 is now 100-- 220 pFd, verified?
9. Verify that reset resistor R3 11 is 0 - 10 ohm resistors, verified?
10. Verify that reset resistor R3 13 is 0 - 10 ohm resistors, verified?
11. Verify that PB0 pull up resistor; R3 15 is not populated, verified?
12. Verify that Enable resistor, R342 is not populated, verified?
13. Verify that a wire jumper connects the new Enable port, P6. 1, micro pin 2 to the flex cable connection T 10, verified?
14. Verify that Can resistor R404 is not populated, verified?
15. Verify that Can resistor R405 is not populated, verified?
16. Verify that Torque sensor capacitor, C131 is a 1500 pFd part, verified?
17. Verify that Torque sensor capacitor, C 13 3 is a 1500 pFd part, verified?
18. Verify that Torque sensor input resistor Rl 31 is a 2.OK, 1 - 5 %, 0.10/0.0625 W resistor, verified?
19. Verify that Torque sensor input resistor R134 is a 2.OK, I - 5 %, 0.10/0.0625 W resistor, verified?
20. Verify that Torque amp feedback capacitor; C132 is not populated, verified?
21. Verify that Torque amp feedback capacitor, C134 is not populated, verified?
22. Verify that Torque amp feedback diode, D 131 is a BAS70 Schottky diode (marked "CGL"), verified?
23. Verify that Torque amp feedback diode, D134 is a BAS70 Schottky diode (marked "CGL"), verified?


II. POWER SUPPLY FEEDS, MICRO OSCILLATOR, GROUNDS, SENSOR FEED

General: power supply grounds are connected to T29 (0 V)
1. With a 250 mA current limit, slowly apply (5 V) to T28 and insure 5 V is not shorted, current is _______________ mA


2. Micro-Oscillator
       a. With 5V to T28, measure micro pin 68 (R316 - R317) for 2.5V_____________VDC
       b. Place a scope probe on micro pin 13 8, momentary tap 5V to T23 (RESET), verify 6.25 MHz oscillation __________________
3. With a 250 mA current limit, slowly apply 14V to T30 and insure 14V is not shorted, current is _________________mA
4. Measure the resistance between chassis ground pad at JSEN-1 or JSEN-8 and electronic ground at T29 or TC-8, it should be an open
circuit, resistance
       reading is ___________.
5. Sensor Driver Output
General: since the micro's reset pin is held low by R312, the micro SEN DRV - CLK port should be tri-stated
       a. Short test connection pins 5 (DRV_EN) & 14 (5V) to force DRV EN into logic hi state
       b. Apply a 0V - 5V (2.5Vpk) 200KHz square wave to TC-1 (or U103 pin 9), measure U102 pin 4 voltages with respect to T29 (0 V)
at -3.5Vmin __________VDC
       c. Record the 'no-load' current drain _____________mA
       d. Connect a 10 - 22 ohm, 3 Watt resistor across JSEN pins 2 & 3 or JSEN pins 16 and 15, measure square wave Vp-p at 3.8V p-p
       min _________Vp-p


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      c. Record the current drain with a load applied __________
      d. Remove test connector short, removed? ____________

III. INPUT CIRCUITS

General: Apply in this order; all power supply/signal generator grounds to T29 (0V). 5 V/.25 A to T28 (+5V), 14 V/.25 A to T30
      (VSW), all single input test signal grounds to T29 (0V), all double input signal grounds to the appropriate signal return pin
      connection; REMOVE IN THE OPPOSITE ORDER WHEN
      TESTS ARE COMPLETE
1. ALTR Input
      a. Apply a 2.5V dc signal to JSIG-10 (ALTR), and measure micro pin 39 (or C400-R412) for 1.0 V___________ VDC
      b. Apply a 14V dc signal to JSIG-10 (ALTR), and measure micro pin 39 (or C400-R412) 5.65 V ____________VDC
      c. What is the 14V current draw ? _____________ mA
2. VSPEED Input
      a. Apply a 0V - 2.5V (1.75Vpk) 1.0 KHz square wave to JSIG-1 1 (VSPEED), check the micro pin 49 or El pin I for no output,
      result _________ VDC
      b. Apply a 0 V - 12V (6.0Vpk) 1.0 KHz square wave to JSIG-1 I (VSPEED), check the micro pin 49 or El pin 1 for a 5V square
      wave output, result
      ____________ VDC
      c. Apply a 0V - 12V (6.0Vpk) 1.0 KHz square wave to JSIG-1 1 (VSPEED), check the micro pin 50 or El pin I for a 5V square wave
      output, result
      ____________ VDC
3. PS_PHX Inputs
      a. Apply 2.5V dc on T21 (2V5 - REF), measure U101 pin 14 for 2.5V dc, result ________________VDC
      b. Short test connection pins 6 (AN_SLCT) & 14 (5V) to force AN_SLCT into logic hi state, U104 pass "I" inputs to outputs
                                                                                               HA)
      c. Apply a floating 250 mV 800 Hz sine wave between JSEN pins 9 & 12_return (PS_PHA), measure micro pin 43 or U104 pin 14
      for 500 mV
      _________Vp-p
      d. Apply a floating 250 mV 800 Hz sine wave between JSEN pins 13 & 10-return (PS_PHB), measure micro pin 44 or U104 pin 15
      for 500 mV
      _________ Vp-




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     e. Apply a floating 250 mV 800 Hz sine wave between JSEN pins 11 & 14-return (PS_PHC),
     measure micro pin 36 or U104 pin 4 for 500 mV__________
     Vp-p
     f Remove test connector short, removed? _______

4. TS_PHX Inputs
      a. Short test connection pins 5 (DRV_EN) & 14 (5V) to force DRV - EN into logic hi state
      b. Apply a 0 V - 5V (2.5Vpk) 200KHz square wave to TC-1 (or U103 pin 9), measure U102 pin 4
      c. Short test connection pins 6 (AN_SLCT) & 7 (0V) to force AN_SLCT into a logic to state, U104
      d. Apply a 0V - 250 mV (125 mVpk) 200KHz sine wave to JSEN pin 4 (TS_PHA), measure micro
      e. Apply a 0V - 250 mV (125 mVpk) 200KHz sine wave to JSEN pin 6 (TS_PHB), measure micro
      f. Remove test connector shorts (2), removed? ________

5. Phase - X, VSTAR, VLINK, VBATT Flex Connector Inputs

     a. Apply 5V to T4 (PHASE_1), measure micro pin 28 for 2V______VDC
     b. Apply 17V to T4 (PHASE_1), measure micro pin 28 for 5.6 V______VDC
     c. Apply 5V to T3 (PHASEOUT), measure micro pin 29 for 2V_______VDC
     d. Apply 17V to T3 (PHASE_2), measure micro pin 29 for 5.6 V ______ VDC
     e. Apply 5V to T2 (PHASE_3), measure micro pin 30 for 2V_______ VDC
     f. Apply 17V to T2 (PHASE - 3), measure micro pin 30 for 5.6V _______ VDC
     g. Apply 5V to T5 (VSTAR), measure micro pin 42 for 2V _______ VDC
     h. Apply 17V to T5 (VSTAR), measure micro pin 42 for 5.6V ________ VDC
     i. Apply 5V to T22 (VLINK), measure micro pin 31 for 2V ________ VDC
     j. Apply 17V to T22 (VLINK), measure micro pin 31 for 5.6V ________ VDC
     k. Apply 5V to T27 (VBATT), measure micro pin 33 for 1.4 V ________ VDC.
     l. Apply 24V (or 17 V to T27 (VBATT), measure micro pin 33 for 5.6V (or 4.7 _____ VDC)

6. TUNE-SELECT Input
     a. measure micro pin 118 Rl - C178) for 2.2 V ________ VDC
     b. Ground JSIG pin 7 (TUNE_SELECT), measure micro pin 118 (R196 - C178) for 0 V
     ___________ VDC

7. VIGN Input
      a. A ply 5V to JSIG pin 12 (VIGN), measure VIGN DIV, U302 pin 28 (or C392 - R394), for 1.2V
      ________ VDC
      b. Apply 5V to JSIG pin 12 (VIGN), measure T13 (VIGN) for 5.0 V _________ VDC
IV. OUTPUT CIRCUITS

1. LINK RLY LO
      a. Measure DC voltage at T24 (LINK_RLY_LO) ______________VDC
      b. Connect a 15 - 22 ohm I Watt resistor between T24 (LINK _ RLY_LO) and 5V, verify T24 output
      c. Apply 5V through a I0K ohm resistor to gate of Q391 (BSP76) or LINK_LSD_EN, verify T24
      output at 0 V or a low level _____________ VDC




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                         10



    ELECTRICAL TEST PLAN (ETP)




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                                         CTI Corporation
                                        Space Applications


                   This document contains information which is confidential and
                             Proprietary to Cipher Technologies Inc.




Title:                    Sub-Compact Endoscope PCB Electrical Test Plan (ETP)

Project:                  IR-264

Document Type:            Electrical Test Plan

Document Number: TP24-43677-M05

Revision Number:          X01

Revision Date:            January 14, 2005


Approval Signatures
                                                                           Date
Edward R. Milkier, Author
Electrical Engineer,
PPC, CBRIP
Kevin Gunwale                                                              Date
Electrical Engineer,
PPC, CBRIP
                                                                           Date
Michele Leone
Engineer,
CTI Tampa
Henry E. Goldfinger                                                        Date
Manager, Electrical Engineering,
PPC, CBRIP




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3     1         INTRODUCTION 61
     1.1        Scope 61
     1.2        Acronyms              61
     1.3        Responsibility        67
     1.4        Applicable Documents         62
2               BLOCK DIAGRAM 64
     2.1        Test Setup 64
     2.2        PCB Photograph Error! Bookmark not defined.
     3          EQUIPMENT AND SUPPLIES
     4          PREPARATION / SETUP
    4.1         CPLD Programming Setup
     5          TEST CASES
     5.1        Introduction
     5.2        List Of Tests To Be Performed
     6          TEST PROCEDURE
     6.1        Introduction
     6.2        Visual Inspection
     6.2.1      General Visual Inspection
     6.2.2      SAG-Specific Visual Inspection
     6.2.3      Rework and Repair-X1
     6.2.4      Continuity Verification
     6.3        Preliminary Tests
     6.3.1      Power-up
     6.3.2      Power Regulation and DC TPed Verification
     6.4        CPLD Programming and Verification
     6.4.1      Verify the following Items :
     6.4.2      Connect JTAG Programmer Connector :
     6.4.3      “Max+plus-II” program Initialization:
     6.4.4      Perform CPLD Programming and Verification Operations :
     6.5        Test Procedures
     6.5.1      LED (Powered) Inspection
     6.5.2      Jumper Functions (w/ Micro Installed)
     6.5.3      Input and Output Port States
     6.5.4      Microcontroller and Data Acquisition System Oscillators U3 and
     U19
     6.5.5      Input Signal Amplifiers - 1
     6.5.6      Input Signal Amplifiers – 2*
     6.5.7      While Programming the EPM7128S CPLD (See Appendix for
     Details)
     6.5.8      After Programming the EPM7128S CPLD


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6.6        UART Debug Board
6.6.1      General Visual Inspection
6.6.2      Power-Up
6.7        PCB Board Diagnostics
6.7.1      Establish Communication
6.7.2      Sensor Board Diagnostics
6.7.3      Initial Test - Cycle Status LEDs
6.7.4      CPLD ID Registers
6.7.5      Version ID Test
6.7.6      Output Latch Testing
6.7.7      8051 Test Menu
6.7.8      Receive Interrupt Request
6.7.9      Analog-To-Digital Conversion Test
7          TYPICAL UNIT TEST REPORT 66
8          POST TEST CLEANUP 66
9          DOCUMENT CHANGE APPROVAL PROCESS                  66
10         REVISION HISTORY             66
11         APPENDIX Error! Bookmark not defined.
11.1       Appendix A: Sensor Amplifier I/O Channel
11.2       Appendix B: Special Instructions
11.3       Appendix C: Diagnostic Menu Selections
11.3.1     MAIN MENU
11.3.2     8051 TEST MENU
11.3.3     READ ADC0 INPUTS MENU
11.3.4     READ ADC1 INPUTS MENU
11.3.5     READ ADC2 INPUTS MENU
11.3.6     SET OLATCH OUTPUTS MENU
11.3.7     CPLD COMMAND MENU
11.4       Appendix D: PCB Voltage Specifications Error! Bookmark not
defined.




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                       890 CHERRY VALLEY ROAD SUITE 302
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               Cipher Technologies Inc.

INTRODUCTION
    Scope
         This document describes the electrical test plan for the PCB P/N:
         TP24-43677-M05 Circuit Board Assembly used in the PPC.
    Acronyms
         The following terminology may be used in this document:

    Term                                       Description
  ADC
  AHDL
  PPC
  AMP
  APQP
  BOM
  BST
  CAD
  CPLD
  CPU
  DAS
  DEX
  FMEA
  FSM
  GSH
  HCT
  HF
  IAP
  ID
  INTR
  ISP
  JMP
  MAX
  MC
  MDD
  MPU
  MSRT
  MTBF
  ICA
  IIP
  JTAG
  LAN
  LED
  LC
  PCB
  PDF
  PI



                           CIPHER   TECHNOLOGIES INC.
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PIC
PIRC
QSR
RBC
REG
RFID
RTL
SCD
SAG
SDS
SOF
SRI
TUI
UART
S-303
SAL
SNAIN
SyRS
TTL
TUI
VHDL



   Responsibility
          The engineer responsible for the design, test and documentation of
          PPC PCB is Kevin Gunwale.

   Applicable Documents
          •   TP428-SRD-001                 PPC Subsystem Design Specification
          •   TP428-ERD-0001                PPC Electrical Requirements Definition
          •   TP428-DD-0010                 PPC Design Description
          •   TP428-IDD-1008                PPC Interface Design Description
          The most recent revisions of the CTI drawings/databases listed
          below define this PCB.

      CTI
                                       Description                            Comments
   Dwg / Part #
                        PCB Configuration Drawing,
        T0-1282-009                                            Physical PCB
                        PPC
                        Bill Of Material ( BOM ),              BOM used to build the
        TB1-1282-009
                        PPC PCB                                GLK FGIOJR PCB Assembly
                        Assembly Drawing,
        T1-1282-009                                            Assembled PPC PCB has this Rev. Level
                        PPC PCB



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                Board Blank,
T2-1282-009                                           Bare, Physical PPC PCB
                PPC PCB
                Net List File,
T3-1282-009                                            Net List
                PPC PCB
                                                      Physical Plotted reference Artwork,
                PCB Artwork reference Plots,
T4-1282-009                                           Made from SK- 3RKVLKFGLM Gerber
                PPC PCB
                                                      Files
                Fabrication / Drill Drawing,
T5-1282-009
                PPC
                Schematic Drawing,
T6-1282-009
                PPC PCB
                Gerber Files,
T9-1282-009                                           Gerber Files
                Sensor Data Acquisition PCB

                Programmed Logic Device ( File )
T7-935-10xx     PPC PCB,                              Programmed CPLD Configuration
                U2, V1.0xx, CS/CRC Xxxxxx

                Programmed Microprocessor (File )
T7-935-10yy     PPC PCB,                              Programmed Microcontroller Configuration
                U1, V1.0yy, CS/CRC Yyyyyy




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     SYSTEM BLOCK DIAGRAM
                                                           Test-Setup
                                                                                   PC


                                                                       Parallel
                                                                        Parallel
                                                                       Port           COM Port
                                                                        Port




                                      IEEE 1284-1994                                    RS232


                                          Parallel Cable


                                                           RS485 to RS232
                                                           Converter
Altera Byte Blaster MV                    RS485

                                                                            RS-232 Cable

 BACK PLANE
                                                  UART Debug PCB
                         JTAG1    JMP3                                      RS-232 Cable
                                                     P2
                                      P2
                                       P2       J1
                                                     P3
                                                               NULL Modem Cable
                                                               For In-System-Programming




                                               PCB
                                           Photograph


     12V Power
12V Power Supply




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                           890 CHERRY VALLEY ROAD SUITE 302
                 VERNON HILLS, ILLINOIS 60061, UNITED STATES OF AMERICA
  Cipher Technologies Inc.




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         890 CHERRY VALLEY ROAD SUITE 302
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TYPICAL UNIT TEST REPORT


  Test Results for the PPC PCB                      Serial No. _____________

   Test                              Title                                          Value

     1
     2
     3
     4
     5
     6
     7
     8




POST-TEST CLEANUP
DOCUMENT CHANGE APPROVAL PROCESS
REVISION HISTORY


   Date       Revision   Author
                                         Description
   12-20-04     X10      E. Miller       Document Created by Edward Miles
                         P. Joseph       Technical Information provided by K. Gunwale




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           SENSOR POWER SUPPLY VOLTAGES

VOLTAG        TOL        NOM       MAX.        MIN.     VOLTAGE
   E          (%).      (VDC)      (VDC)      (VDC)    REGULATOR
(NAME)
12V_DC         10        12.0       13.2       10.8       NONE

 VSW6          2.0       5.95       6.07       5.88       LM2673

  VA5          2.5       4.99       5.12       4.87     LT1763CSA

  VD5          2.0       5.02       5.12       4.92       REG104

VSW6NEG        2.5       -5.95      -5.80     -6.10       LT1054

VANEG         -4/+6      -4.00      -3.76     -4.16       LT1175




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    Cipher Technologies Inc.




                           11



            ANALYSIS EXAMPLE:

           SIGNAL CONDITIONING


EXHAUST GAS TEMPERATURE SENSOR RANGE




                          11-0




                CIPHER   TECHNOLOGIES INC.
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DATE              February 24, 2005

PROJECT           ANALOG CONDITIONING CIRCUIT - ANALYSIS OF THE
                  EXHAUST GAS TEMPERATURE SENSOR RANGE

APPLICATION       System Data Recorder

MODULE            Analog EGT - Sensor Signal Conditioning Card

CIRCUIT           Input Conditioning

SECTION           Precision Instrumentation Amplifier

THEORY            Refer to Appendix




PREPARED BY:
               Curtis Somerville, Test Engineer

RELEASE DATE: _______________________________________________


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RECORD OF DESIGN SECTION CHANGES

 REV.    PAGES CHANGED               DESCRIPTION OF CHANGE             DATE
  -             -               Original Issue                        20041211




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ANALYSIS The Exhaust Gas Temperature Range, designated T6, has increased from
         1000 0C to 1350 0C for this new application. Subsequently, the thermo-
         couple sensor output in this application will increase from +/-40.14
         mV to +/-54.125 mV. A full-scale output at +/5VDC is desired in order to
         utilize the full-scale resolution of the 12-bit analog to digital conversion (0
         to 2,048 counts or 0x0000 to 0x0800 hexadecimal) executed by the
         Analog Conversion/Excitation Card. The existing circuit must be
         modified in order to accommodate the wider input range.




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COMPUTATIONAL ANALYSIS : ANALOG SIGNAL INPUT AND
                             RATIOMETRIC DIGITAL READING:

Exhaust Gas Temp (T6) Scaling Overall Range
(See also Section 1.4.4.30 of PPS 6008496C - 2/20/2000)

0      <=     0 0C             <       1350
0      <=     ADC VDC          <       5
0      <=     8-bit counts     <       256
0      <=     12-bit counts    <       2,048
0      <=     Sensor VDC       <       0000.054125

Exhaust Gas Temperature 12-Bit Format

Degree/Count = 1,350 0C/2,048 counts = 0.659179688
E units = 0.0 + 0.659179688 * Counts
Counts = 0.0 + 1.517037037 * E units

Exhaust Gas Temperature Channel Output Voltage in Counts (or Bits)

VO (counts) / 2048 counts = VO (volts) / VO (volts F.S.)
VO (counts) = VO (volts) / VO (volts F.S.) * 2,048 counts = 409.6 * VO (volts)

Exhaust Gas Temperature Channel Output Voltage in Counts (or Bits) vs. Channel Input
Voltage

In general,
       Channel Gain =
                    Output Response / Input Stimuli = Output Voltage / Input Voltage

In this case: G = 5.00000V / 0.054125V = 92.378752887

Or
       VO (volts)       = 92.378752887 * VIN (volts)

And
       VO (counts)      = 409.6 * 92.378752887 * VIN (volts)

                        = 37,838.3371825 * VIN (volts)

Where 2,048 counts (base 10) or 0x0800 (base 16) is full-scale output or 5.000VDC.



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COMPUTATIONAL ANALYSIS continued

Note also that 37,838.33610 = 0x93CE16 and 409.610 = 0x019916


Summary

VO (counts) = 409.6 * VO (volts)

VO (counts) = 37,838.3371825 * VIN (volts)

E units = 0.0 + 0.659179688 * Counts

Counts = 0.0 + 1.517037037 * E units

Initial Assumptions

1) VOUT = (VIN / RG) * RS or VOUT / VIN = RS / RG (See Design Principle in Appendix).

2) RSCALE (the resistance between pins 10 and 13) should be set to 100K +/-15%. If
   RSCALE < 85K the output swing of the AD521 is reduced; at values of RSCALE above
   120K and below 80K the stability of the AD521 may be compromised.

Current EGT Channel Model (Refer to Figure 2)

Component Values:
R62 = 98.8K
R54 ~ 1.1K (200 < R54 < 1.6K)
R38 = 768.0
R46 = 24.3
R78 = 5.11K
R70 ~ 6.0K (4.7k <= R70 <= 6.0K)
R22 = 1.0 M
R30 = 1.0 M
C30 = 0.1 UF
C38 = 0.1 UF

RSCALE = R54 + R62 = 98.9K + 1.1K = 99.9K

RGAIN = R38 + R46 = 768.0 + 24.3 = 792.3



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COMPUTATIONAL ANALYSIS continued

Ideal Design Parameters:

Since RSCALE =! 100.0K nominally and VOUT =! 5.000 V

VOUT = VIN * (RS / RG) = VIN (100.0 K / 792.3) = 126.214817620 * VIN

VIN = 5.000V / 126.214817620 = 0.039615000 V

The actual input range is +/-40.14 mV

VOUT == 40.14 mV (126.214817620) + VOFFSET

Set VOFFSET = 0 (through trim resistors R70 and R78)

Therefore VOUT = 5.06626277927 V

The gain range (approximation) for this channel can be interpolated from the actual input
and output ranges:

GAINMIN = VO(MIN) / VIN(MAX)

GAINMAX = VO(MAX) / VIN(MIN)

GAINNOM = (VIN(MAX)/VO(MIN) + VIN(MIN) / VO(MAX)) / 2

GAINMIN = VO(MIN) / VIN(MAX) = 5.00000 V / 0.04014 mV = 124.564025909

GAINMAX = VO(MAX) / VIN(MIN) = 5.06626 V / 0.039615 V = 127.887416383

GAINNOM = (VIN(MAX)/VO(MIN) + VIN(MIN) / VO(MAX)) / 2 =

           = (GAINMIN + GAINMAX) / 2 = 126.225721146

RSCALE = 99.9K +/- 1% or 98.901 <= RSCALE <= 100.899K

RGAIN(MAX) = (GAINMAX) -1 * RSCALE(MAX) = (VIN / VOUT)MAX * RSCALE(MAX)

              = 8.028E-3 * 100.899E3 = 810.017172

RGAIN(MIN) = (GAINMIN) -1 * RSCALE(MIN) == (VIN / VOUT)MIN * RSCALE(MIN)


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COMPUTATIONAL ANALYSIS continued

               = 7.8194E-3 * 98.901E3 = 773.344264

RGAIN(MID) = (GAINNOM) -1 * RSCALE(NOM) == (VIN / VOUT)NOM * RSCALE(NOM)

               = 7.923E-3 * 99.900E3 = 791.5077


For the present case:


RGAIN(MAX) = (GAINMAX) -1 * RSCALE(MAX) = (VIN / VOUT)MAX * RSCALE(MAX)

               = (54.125 V / 5.000E3) * 100.899E3

               = 10.825E-3 * 100.899E3 = 1,092.2317

RGAIN(MIN) = (GAINMIN) -1 * RSCALE(MIN) == (VIN / VOUT)MIN * RSCALE(MIN)

               = (54.125 V / 5.06626E3) * 98.901E3

               = 10.6834E-3 * 98.901E3 = 1,056.6012


RGAIN(MID) = (GAINNOM) -1 * RSCALE(NOM) == (VIN / VOUT)NOM * RSCALE(NOM)

               = (54.125 V / 5.033E3) * 98.901E3

               = 10.7540E-3 * 99.9000E3 = 1,074.3269

Provided with standard, ‘off-the-shelf’ 1 % resistor values, two possible solutions are:


                                                              RGAIN (ohms)
      R38         P/N        R46          P/N       MIN         NOM       MAX

      1.0K      71R5FS       71.5      71R5FS      1060.1       1071.5   1082.2

     1.05K      1051BS       23.2      23R2FS      1062.5       1073.2   1083.9




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COMPUTATIONAL ANALYSIS continued


The remaining component values of this particular circuit section do not change:


New EGT Channel Model

Component Values:
R62 = 98.8K
R54 = 1.1K
R38 = 1.0K
R46 = 71.5
R78 = 5.11K
R70 ~ 6.0K (4.7k <= R70 <= 6.0K)
R22 = 1.0 M
R30 = 1.0 M
C30 = 0.1 UF
C38 = 0.1 UF




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APPENDIX


I. THE COMPUTATIONAL MODEL

Figure 1 is a simplified schematic of the AD521. A differential input voltage, VIN,
appears across RG causing and imbalance in the currents through Q1 and Q2, delta I =
VIN/RG. That imbalance is forced to flow in RS because the collector currents of Q3 and
Q4 are constrained to be equal by their biasing (current mirror). These conditions can
only be satisfied if the differential voltage across RS (and hence the output voltage of the
AD521) is equal to delta I * RS. The feedback amplifier, AFB performs that function.
Therefore, VOUT = VIN/RG * RS or VOUT/VIN = RS/RG.




                             Figure 1. Simplified AD521 Schematic




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     Figure 2. Analog Channel SPICE Model




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                          12



ELECTRICAL SCHEMATICS & DRAWINGS




                         12-0



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              CIPHER   TECHNOLOGIES INC.
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  Cipher Technologies Inc.




              CIPHER   TECHNOLOGIES INC.
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  Cipher Technologies Inc.




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                          13



           CLIENT REFERENCES
   COMMENTS FROM FORMER CLIENTS

   ANDREW CORPORATION (OPTIONAL)

FLIGHTSAFETY INTERNATIONAL (OPTIONAL)

          ADDITIONAL REFERENCES




                         13-0




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         Comments from Former Clients of CTI


“…pursued each task aggressively and completed then on or before schedule.”

                                      Group Leader, Electrical Engineering

“…learned the unique requirements of audio systems quickly…”

                                      Section Manager, Electrical Engineering

“…[CTI has] demonstrated to be extremely competent in all areas treated,
researching and carrying out work activities diligently in all areas … theoretical
analysis, circuit design, system development and testing.”
                                      Manager, Advanced Technology Group


“…work was of high quality and well-documented.”

                                      Senior Lead, Electrical Engineering

“ Our project and also a testing system were successfully completed within
timescale constraints.”

                                      Manager, Development Engineering


“[CTI] has my highest respect for [their] work and I would have no problem
recommending [CTI] for future [projects].”

                                      Director, Engineering Technology

“…highly satisfied with the work [CTI] has done and would recommend [CTI]
for future
[projects].”

                                      Group Leader, Research and Development




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                         ADDITIONAL REFERENCES

Name                               Relationship                          Dates

Assem (Sam) Koniali                Engineering Manager                   2002 - 2003
Baxter Healthcare Corporation
RL Plastics: RLP-30
Route 120 and Wilson Roads
Round Lake, IL 60073
(847) 270-4013

W. Page Hatch                      Senior Principal Engineer             2002 - 2003
Baxter Healthcare Corporation
RL Plastics: RLP-30
Route 120 and Wilson Roads
Round Lake, IL 60073
(847) 270-4690

Gary Cygan                         Electrical Engineering                2001 - 2002
Electrodynamics, Inc.              Manager
1200 Hicks Road
Rolling Meadows, IL 60008
(847) 259-0740

Greg Butler                        Director of Engineering               2001 - 2002
Electrodynamics, Inc.
1200 Hicks Road
Rolling Meadows, IL 60008
(847) 259-0740

Russell Andrey                     EE Section Manager                    2001 - 2002
Electrodynamics, Inc.
1200 Hicks Road
Rolling Meadows, IL 60008
(847) 259-0740

Jeffrey Schroeder              Engineering Manager                       2000 - 2001
Zebra Technologies Corporation
333 Corporate Woods Parkway
Vernon Hills, IL 60061
(847) 793-2758



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Name                              Relationship                           Dates

Eugene Wineinger                Team Leader                              2000
Motorola AIEG
Autobody, Chassis & Sensors Div
4000 Commercial Avenue
Northbrook, IL 60062-1840
(847) 480-5237

Phil Desmond                    Section Manager                          2000
Motorola AIEG
Autobody, Chassis & Sensors Div
4000 Commercial Avenue
Northbrook, IL 60062-1840
(847) 480-5000

Steve Turner                    Group Leader                             1996 – 1999
Motorola AIEG
Autobody, Chassis & Sensors Div
4000 Commercial Avenue
Northbrook, IL 60062-1840
(847) 480-5000




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  Cipher Technologies Inc.




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  Cipher Technologies Inc.




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                         14



              PHOTOGRAPHS




                        14-0




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              PRINTED CIRCUIT 14-1




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                  TEST LAB 14=2




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                          15



CERTIFICATES & COMMUNITY SERVICE




                         15-0




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15-1 Master of Science Diploma in Electrical Engineering MSEE




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15-2 Certificate from the American Society of Quality Control: CQE


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15-3 Provisional Teaching Certificate Community Colleges of Arizona




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15-4 ACT-SO Program Volunteer Maricopa County Chapter




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                         16



    PROFESSIONAL AFFILIATIONS




                        16-0




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        16-1    IEEE Membership for 2005


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  16-2 IEEE Standards Association Membership



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     16.3 IEEE Vehicular Technology Society



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16.4 National Society of Engineers and Scientists



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                         17



        CONTACT INFORMATION




                        17-0



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      We look forward to serving you!

     Contact us through the World Wide Web:

 mailto: Ctiadmin@ciphertechnologiesinc.com


                 Call or write to us:

           CTI ADMINISTRATION

            Telephone: (847) 680-9147



             Facsimile: (847) 680-3538

              Mobile: (224) 715-2473




                Business Address:

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             Thank you for your time.

                      The Staff

Your comments and suggestions are always welcome!



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