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					Equalization and System in Package (SiP)
               Solutions
Whitepaper




March 2010
Introduction
High speed serial interfaces are becoming more demanding, with ever-increasing requirements for
higher data rates and higher density ports. At the same time the CMOS technology used for leading edge
ASIC designs is becoming less suitable for implementing the functionality associated with these high
speed interfaces as geometries are shrinking to keep pace with Moore’s Law.

This white paper outlines how separating analogue front-end (AFE) functions from the digital ASIC core
can enable improved high performance serial interfaces. When these functions are separated into
stand-alone chips, packaging them together in a System in Package (SIP) becomes attractive. The metrics
for a successful separation and effective packaging are outlined here below.


Equalization: integrate or separate?
During the last decade, chip development has been dominated by SoC, or System on Chip efforts, driving
to higher and higher integration of functions. The advantages of combining all required functionality on
a single chip have led to significant cost and power reductions. However, it seems that for some
applications the SoC approach has reached the end of the road. For example, large scale LSIs for
networking applications combine hundreds of millions of digital gates with large numbers of multi-
Gigabit per second interfaces. The large and complex digital content of these types of chips requires
implementation in the latest generation of CMOS technology to offer acceptable die size and power
levels.

However, while the power and size of digital logic scales very well with the reducing geometry of the
CMOS process, this does not apply the same way to high performance I/O blocks. This means that some
of these blocks become relatively more expensive, and are more difficult to implement in these leading
edge processes. Specifically some key analogue functions required in serial receivers, such as
equalization and pre-amplification do not scale well in small geometry CMOS technologies.


                OUTP

                         PARALLEL
               OUTM      TO SERIAL




                            PLL                                       DIGITAL CORE



                 INP

                                                   SERIAL TO
                            CDR           DFE
                 INM                               PARALLEL




                                  Figure 1 – SoC with high-speed interfaces



A Phyworks & GUC Whitepaper                                                                      Page 2
One approach is to implement complete serial equalizers as separate chips. Such products implement an
initial gain stage, equalization (such as FFE and DFE) and clock data recovery (CDR). The advantage is
that such chips will be subject to less noise and can often offer better performance than the serial inputs
implemented in the SoC. This then enables the external equalizer to be used at the interfaces that really
required the enhanced performance, for example in case of a difficult backplane. The SoC can use the
same high-speed I/O on all interfaces, with the implementation of this I/O optimized for the chip-to-chip
connections.

             RETIMING EQUALIZER                                                         ASIC/SoC
                                                                            REFCLK
                                    PLL                                                PLL



                                                                         OUTP    INP
INP
         LINEAR     LINEAR                                      OUTPUT
                                   CDR             DFE                                 CDR        DFE
           VGA     EQUALIZER                                    BUFFER   OUTM    INM
INM



                                  CONTROL



                                  Figure 2 – stand-alone Equalizer and ASIC

A drawback of using these types of equalizers is that they effectively duplicate a large section of the SoC
inputs, as these will still have to implement at least the CDR function. This is shown in figure 2 as the
hatched area in the retiming equalizer.

                                                                                        ASIC/SoC
                                                                            REFCLK
                                                                                       PLL
                  PRE-EQUALIZER

                                                         OUTP                    INP
INP
         LINEAR        LINEAR             LINEAR
                                                                                       CDR        DFE
           VGA        EQUALIZER           BUFFER         OUTM                    INM
INM



                      CONTROL



                                      Figure 3 – Pre-Equalizer and ASIC

The solution to this dilemma is to use external solutions that work together with the essential SoC high-
speed I/O functions such as CDR and DFE to provide optimal power, cost and performance metrics. A
shown on figure 3, such stand-alone equalizer products can be placed as separate chips on the PCB,
offering flexibility and high performance.




A Phyworks & GUC Whitepaper                                                                        Page 3
                                                                         HSIO


       High
Performance
  Backplane       Backplane               Pre-
                                                                        ASIC with                Other
                                        Equalizer         HSIO                         HSIO
                                                                     High-Speed I/O              chip
                                           #1



   Standard
Performance
Chip-to-Chip                                                             HSIO




                                                         ASIC with
                                                                         HSIO
                                                           High-
                                                         Speed I/O




                              Figure 4: right-scaling the performance of the serial interfaces


System in Package
System in Package (SiP) solution will be a more effective approach by combining ASIC and equalizer die
in a single package. As shown in the previous section, separate pre-equalizer chips offer better flexibility
and performance. SiP will differentiate this approach, and will further enhance product competitiveness
by realizing following benefits:

    •   Better performance: close integration of the ASIC and the equalizer will improve the signal
        integrity by reducing the interconnect distance between equalizer and ASIC
    •   Noise and power consumption can be reduced by lowering the required signal swings on the
        chip interface as result of shorter trace distance. This in turn will reduce EMI.
    •   Better time to market, lower development cost and risk through heterogeneous integration.
    •   Miniaturization: the PCB size can be reduced
    •   Higher flexibility for pre-equalizers to be used in a package.
    •   Lower total cost through less PCB size and layers

Global UniChip Corp. (GUC) is a leader in providing SiP/3DIC service. GUC has shipped over 15 million SiP
units to worldwide Tier 1 customers for applications such as consumer, wireless, networking, and
computers. Today projects using a SiP approach account for around 25% new projects developed by
GUC for its customers which contribute approximately to 30% of GUC’s revenue.




A Phyworks & GUC Whitepaper                                                                         Page 4
Figure 5 below details some specific and diverse applications in which GUC has deployed SiP. As can be
seen SiP has been successfully proven in Networking and Data communication applications,
demonstrating the maturity of SiPs in the area in which the pre-equalizers would be used. Additionally
as can be seen from Figure 02, GUC has deployed the so called “Ultra Large SiP” for large scale Network
and Data Communication of which over 500K units have been shipped meeting with all customer quality
and reliability standards.

                     Application                 KGD              PKG    Size (mmxmm)

                Network              8x RLDRAM, ~300 Passives   FCBGA          53x72

                Camcorder            2 x MDDR                   LFBGA          15x15

                Cellular Phone       PMIC, SDRAM, Flash         PoP            12x12

                Security Camera      SDRAM                      LFBGA          12x12

                Multimedia           SDRAM, Ethernet PHY        LFBGA          14x14

                T-Con                SDRAM                      LQFP           24x24

                Mobile TV            SDRAM                      TFBGA          12x12

                Car Camera           SDRAM, Rx, Tx              LFBGA          14x14

                Mobile TV            RF, ~20 Passives           TFBGA          12x12

                PC                   PCI-E PHY                  BGA            23x23




                                   Figure 5: GUC’s SiP Success Stories




                                   Figure 6: Ultra Large SiP for networking application



A Phyworks & GUC Whitepaper                                                                     Page 5
The ultra-large SiP shown in figure 6 above combines 1 ASIC, 8 memory chips and 300 passive
components in a 53mm x 72mm Flip Chip BGA with ~2000 pins. The SiP substrate uses 10 layers,
substantially reducing the PBC complexity and overall power consumption.

GUC strategy for SiP implementation involves close collaboration with customers from initial conceptual
brainstorming, through designing, prototyping and all the way to mass production. GUC has provided
values listed below to customers:

    •   SiP Feasibility and trade-off analysis
    •   Total and complete engineering solution
         Known Good Die (KGD) solution and sourcing
         Optimum package identification through Chip-Package-Board co-design/ co-simulation to
              achieve optimum performance
         Electrical/Thermal/Mechanical analysis
         Design for Manufacturing (DFM) and Design for Test (DFT)
         Total test solution
    •   Professional production service
         Production flow optimization and yield enhancement
         Close collaboration with world class partners
    •   Quality and reliability service
         Qualification
         Failure analysis - Feasibility and trade-off analysis


Benefits of pre-equalization
A novel approach aims to offer the best performance by implementing external (standalone) pre-
equalization, which does work together with the CDR and equalization in the ASIC. There are many
factors impacting on the performance of an equalizer. We already alluded to the noise and crosstalk
issues that impair SoC equalizers, but these are not the only ones.

Another important factor is the linearity and noise performance of the gain stage in the input of the SoC.
If this stage does not provide linear amplification it will make the job of the following equalizer much
harder.

Additionally, many high performance I/O blocks designed for ASIC integration use some sort of Analogue
to Digital Conversion (ADC) function. The ADC is used to enable a digital (and more process portable)
implementation of the DFE, and needs to be extremely high speed and offer enough resolution to let the
DFE work optimally. However, the effective number of bits of resolution is dependent on the input
range.

An external pre-equalizer can help with all of these challenges. This chip can be implemented in a
process that is suitable for high speed linear amplification. Additionally it is possible to offer an output
signal with a constant level, enabling the ASIC input to operate at its optimum operating point. An


A Phyworks & GUC Whitepaper                                                                         Page 6
example of such a circuit is Phyworks’ PHY1090 10Gbps linear Trans-impedance Amplifier (TIA). This part
offers in excess of 26dB of gain, while integrating an AGC function that keeps the output constant over
almost 2 decades of input level.


Key requirements for SiP success
There are many suppliers of standalone equalizers, but not all of them are suitable for implementation
in SiP solutions. What makes an equalizer suitable for such as solution?

   •   DC-coupled outputs: the addition of AC-coupling capacitors in a SiP is extremely unattractive.
       Therefore it is paramount to have equalizer outputs that are compatible with the DC common
       mode voltage of the ASIC inputs. This is not always straight-forward, since the equalizer and the
       ASIC are probably implemented in different technologies, with different power supply
       arrangements and levels.
   •   Low power outputs: generally, equalizers have to provide sufficient output swing to enable the
       transmission of the signal over several inches of FR-4. The XFI standard for example requires the
       support of at least 8” of FR-4. When implemented in an SiP, only short distance will separate the
       equalizer and ASIC die. Moreover, no complex die-to-package and package-to-PCB support is
       required. This will enable the equalizer output to be much lower power.
   •   Die size and pad-pitch: it is important that the equalizer output align easily with the ASIC, either
       using bonding or flip-chip arrangements. This will also enable the connection to be kept short. If
       the connection between the chips is less than 5mm (1/4th wavelength at 10Gbps), it can be seen
       as a lumped element, instead of requiring the implementation of matched transmission lines.




                                           Pre -
                                                        CDR and
                                         equalizer
                                                          DFE
                                            #1



                                                                     ASIC w /
                                                                  High-Speed I /O
                                           Pre -
                                                        CDR and
                                         equalizer
                                                          DFE
                                            #n




                   Figure 7: block diagram of SiP with pre-equalizer and system ASIC




A Phyworks & GUC Whitepaper                                                                        Page 7
SiP/TSV Options
System in Package implementations can be realized in multiple ways:

    •   SiP in side by side configuration ( wire bond)
    •   SiP in side by side configuration(Flip-chip)
    •   Stacked dies by Through Silicon Via (TSV)

Large system ASICs are currently packaged in bonded BGAs or using flip-chip technology. In either case it
is possible to combine the pre-equalization solution in the same package as the system ASIC. Figure 8
shows a pre-equalizer on the same substrate as the system ASIC, connected using bond wires.




Figure 8: Bonded SiP with pre-equalizer and ASIC

Figure 9 shows an alternative implementation where both chips are bumped and placed on the
substrate using flip-chip technology.




A Phyworks & GUC Whitepaper                                                                       Page 8
Figure 9: Flip-chip SiP with pre-equalizers and ASIC


Future possibilities
System in Package is receiving a lot of attention in the industry, with the associated developments in
chip design. Figure 10 illustrated GUC’s SiP/TSV Service Roadmap. TSV (Through Silicon Via,) is to stack
silicon dies and interconnect them vertically by using electrode through all dies as indicated in
illustration of Figure 11, TSV can pack a great deal of functionality into a small “footprint.” In addition,
critical electrical paths through the device can be drastically shortened, leading to much faster operation
and high signal integrity as illustrated in figure 12. Future Phyworks equalizers can be supplied with TSV
technology and combined with large ASICs once this technology becomes mature, so as to enable
extremely highly-optimized networking chips with very high density interfaces.

                                                                         Silicon substrate
                                                                     Device layer
                                                                                                                   3DIC6.0
                                                                                                                  Via first TSV
                                                                     Device layer
                                                           Package                                                Platform design

                                                                                                     3DIC5.0
                                                                                             Via last TSV
                                                                                             Direct migration from SiP
                                  RF
                                                   SDRAM
                                                   ASIC



                                                                                     SiP3.0
                                                                     RF (<6Ghz) SiP
                          ASIC Die                                   RF Chip/Package/Board co-design
                         Spacer die
                         MDDR Die
                         Spacer die
                                                      SiP2.0
                         MDDR Die
                                              High Speed Interface DDR2/3
                                              Chip/Package/Board co-design
                        SiP1.0                                                                                           DDR2
                    Under 200Mhz
                    KGDs<3

                 2008                 2009                           2010                                       2011


                                      Figure 10: GUC’s SiP/TSV Service Roadmap




A Phyworks & GUC Whitepaper                                                                                                         Page 9
                        Figure 11: Illustration of wire bond SiP to TSV evolution




                                                   Substrate



                                                     ASIC




                                                 Pre-equalizers




                                                Pre-equalizers
                                                                      ASIC


                                                   Substrate


             Figure 12: Planned configuration for ASIC & pre-equalizers integration by TSV


Conclusions
This whitepaper has outlined some of the benefits offered by the combination of low power pre-
equalization and modern SiP packaging technology. Standalone equalizer die can be packaged with the
system SoC to provide an optimal solution for high-speed serial interfaces without taking up additional
PCB real-estate. Design cycles can be shortened and risk can be lowered by combining known-good-die
in the SiP, which in itself is a proven and reliable method for packaging die.




A Phyworks & GUC Whitepaper                                                                   Page 10
About GUC
Global Unichip Corp. (GUC), a dedicated fabless ASIC provider based in Taiwan, was founded in 1998.
GUC is now publicly traded on the Taiwan Stock Exchange under the symbol 3443 with 2009 revenue of
8.27 billion NTD or 252MUSD. GUC provides total solutions from silicon-proven IPs to complex time-to-
market SoC and SiP turnkey services. GUC is committed to providing the most advanced and best price-
performance silicon solutions through close partnership with TSMC, GUC’s major shareholder, and other
key packaging and testing powerhouses. With state of the art EDA tools, advanced methodologies, and
experienced technical team, GUC ensures the highest quality and lowest risks to achieve first silicon
success. GUC has established a global customer base throughout Greater China, Japan, Korea, North
America, and Europe. Its track record in complex SoC/SiP designs has brought benefits to customers in
time to revenue at the lowest risk. For more information, please visit http://www.globalunichip.com


About Phyworks
Phyworks, a privately held company founded in 2001 and based in Bristol, UK, is a developer of high-
speed communications chips designed to significantly cut the cost of 10Gbit/s and below copper and
optical interconnect.

Phyworks uses proprietary algorithms and high-speed mixed-signal design to create chips that
compensate for the optical characteristics of fibre, such as dispersion and noise, as well as copper cables
and circuit board traces and connectors in standard mixed-signal CMOS devices.

The company sells its products into telecom - specifically FTTH - and datacom markets worldwide.
Phyworks has a substantial presence in the PON market, with customers in the U.S. and Asia, including
China, Korea and Japan.

For more information, please visit http://www.phyworks-ic.com




A Phyworks & GUC Whitepaper                                                                       Page 11

				
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