The International Technology Roadmap for Semiconductors 2002 by 8be89c015e72c297

VIEWS: 47 PAGES: 29

									The International Technology
Roadmap for Semiconductors
        2002 Update Summary

Overall Roadmap Technology Characteristics
            (ORTC) Overview
                      12/04/02
           Alan Allan / Intel Corporation




                                     4 December 2002, ITRS 2002 Update
                        Key Messages
• The Technology Roadmap for Semiconductors has
  guided the R&D activities for the last 10 years!
• 2003 marks the year of 100nm or below: Welcome to the
  challenges of the Nanotechnology Era!
• NO CHANGES from the 2001 Scaling targets and Chip Size
  models– First Time Since 1994!
   – Economics (Chip Size) consistent with historical trends through 2004
   – Performance (Frequency) consistent with historical trends through 2005
   – Density (Functionality) consistent with historical trends through 2004
• …..but need ―breakthroughs‖ after 2005!
• We will continue to look for evidence of Industry Trend
  Acceleration/Deceleration in 2003



                                                  4 December 2002, ITRS 2002 Update
                        Production Ramp-up Model and Technology Node
                             2002 ITRS Update – (No Changes from 2001 ITRS)
                 100M
                                          Development               Production                     200K
Volume (Parts/Month)




                                                                                                           Volume (Wafers/Month)
                       10M
                                                                                                   20K

                       1M
                                                                                                   2K
                 100K           Alpha        Beta Production
                                 Tool        Tool    Tool                                          200

                       10K                                             First Two
                                         First                                                      20
                                                                      Companies
                       1K                Conf.
                                                                       Reaching
                                        Papers                                                       2
                                                                      Production

                                      -24             -12       0       12               24
                         Source: 2001 ITRS - Exec. Summary   Months
                                                                       4 December 2002, ITRS 2002 Update
MOS Transistor Scaling
  (1974 to present)

      S=0.7
[0.5x per 2 nodes]
         Pitch       Gate



                 4 December 2002, ITRS 2002 Update
                  2002 ITRS Update –
                (No Changes from 2001 ITRS)
               SCALING Timing Highlights
• Technology Node and Industry Pace: The DRAM Half-Pitch (HP)
  on a 3-year-cycle trend after 130nm/2001

• The MPU/ASIC HP remains on a 2-year-cycle trend until
  90nm/2004, and then remains equal to DRAM HP (3-year cycle)
• The MPU Printed Gate Length (Pr GL ) and Physical Gate Length
  (Ph GL) will be on a 2-year-cycle until 45nm and 32nm,
  respectively, until the year 2005
• The MPU Pr GL and Ph GL will proceed parallel to the DRAM/MPU
  HP trends on a 3-year cycle beyond the year 2005

• The ASIC/Low Power Pr/Ph GL is delayed 2 years behind MPU
  Pr/Ph GL
• ASIC HP equal to MPU HP

                                        4 December 2002, ITRS 2002 Update
                                                             ITRS Roadmap Acceleration Continues...Half Pitch
                                           2002 ITRS Update – (No Changes from 2001 ITRS)
                                                      1000



             Technology Node - DRAM Half-Pitch (nm)


                                                                                                               2001 DRAM ½ Pitch
                                                                                                               2001 MPU/ASIC ½ Pitch

                                                                                                                 1999 ITRS DRAM
                                                                                                                        Half-Pitch
                                                       100

                                                                2-year Node
                                                                   Cycle
                                                                              3-year Node
                                                                                 Cycle




                                                        10
                                                         1995        1998         2001        2004      2007       2010      2013      2016

                                                                                            Year of Production

Source: 2001 ITRS - Exec. Summary, ORTC




                                                                                                                   4 December 2002, ITRS 2002 Update
                                                ITRS Roadmap Acceleration Continues…Gate Length
                                         2002 ITRS Update – (No Changes from 2001 ITRS)
                                         1000


Technology Node - DRAM Half-Pitch (nm)



                                                                                   2001 MPU Printed Gate Length
                                                                                   2001 MPU Physical Gate Length

                                                                                              1999 ITRS MPU
                                                                                                 Gate-Length
                                          100




                                                             2-year
                                                             Cycle
                                                                                   3-year
                                                                                   Cycle
                                           10
                                            1995      1998      2001      2004       2007     2010      2013       2016

                                                                       Year of Production
                                         Source: 2001 ITRS - Exec. Summary, ORTC



                                                                                               4 December 2002, ITRS 2002 Update
                            MPU Clock Frequency Actual vs ITRS
                                                  Historical <- > 1999 ITRS                      2002 ITRS
      100,000
                                                                  2001 ITRS
                                                                                                 Update – (No
                                                                                                 Changes from
                                                                                                 2001 ITRS)
                                 2X / 4 Years
            10,000
                                                                                            Actual Scaling
                                                                                            Acceleration, Or
Frequency (MHz)




                                                                                            Equivalent Scaling
                  1,000
                                                                                            Innovation
                                                                                            Needed to
                                                                     2X / 2½ Years          maintain historical
                                                                                            trend
                   100
                                                                                            MPU Clock Frequency
                                                                                            Historical Trend:
                                                          2X / 2 - 2½ Years
                                                                                            Gate Scaling,
                                                                                            Transistor Design
                    10
                                                                                            contributed
                                                                                            ~ 17-19%/year
                                                                                            Architectural Design
                                                                                            innovation contributed
                     1
                                                                                            additional
                     1980        1985     1990     1995       2000   2005     2010   2015
                                                                                            ~ 21-13%/year
                          Sources: Sematech, 2001 ITRS ORTC                                                      28
2001 ITRS DRAM Model Trend Analysis (cont.)
 2002 ITRS Update – (No Changes from 2001 ITRS)


                                                   1.26/yr
                           1.41/yr



0.71/yr

                         1.34/yr
  1.59/yr



               1.47/yr
                            0.74/yr




                                     4 December 2002, ITRS 2002 Update
MPU Chip size (mm2) – Historical Trends vs 2001 ITRS Model*
          2002 ITRS Update – (No Changes from 2001 ITRS)
 1000
           800mm2 Litho Field Size

           572mm2 Litho Field Size




           286mm2 2 per Field Size                                                        HP MPU 310mm2


                                                                                          CP MPU 140mm2

  100
                                                                                           CP Shrink 70mm2

           *1999 Leading-            *1999 Leading-
           Edge .18u   HP MPU:       Edge .18u CP MPU:          * ITRS Design TWG MPU
           2MB (113Mt [81.9%]        512KB (28Mt [58.3%]        Transistors/Chip Model:
           x 1.18u2/t = 135mm2)      x 1.18u2/t = 34mm2)
           + 25Mt Logic x            + 20Mt Logic x
                                                                ~2x/Node =
           5.19u2/t = 130mm2 +       5.19u2/t = 104mm2 +        2x/2yrs from 1999 - 2001;
           45mm2 OH= 310mm2          2mm2 OH= 106mm2
           = Total 138Mt x ave       = Total 48Mt x ave         then 2x/3yrs from 2001- 2016
           2.25u2/t = 310mm2         2.92u2/t = 140mm2

    10
    1980        1985          1990        1995           2000      2005      2010         2015        2020

                                                                      4 December 2002, ITRS 2002 Update
Density Trends (bits/cm2, t/cm2) – ITRS / ORTC
  2002 ITRS Update – (No Changes from 2001 ITRS)




                                                             ITRS 2001 “Moores
                                                               Law” Targets:
                                                             DRAM: 2x/2.5yrs;
                                                             1.05x/yr Chip Size
                                                               MPU: 2x/node =
                                                             2x/3years;   FLAT
                                                                  Chip Size




                                    4 December 2002, ITRS 2002 Update
                        Key Messages
• The Technology Roadmap for Semiconductors has
  guided the R&D activities for the last 10 years!
• 2003 marks the year of 100nm or below: Welcome to the
  challenges of the Nanotechnology Era!
• NO CHANGES from the 2001 Scaling targets and Chip Size
  models– First Time Since 1994!
   – Economics (Chip Size) consistent with historical trends through 2004
   – Performance (Frequency) consistent with historical trends through 2005
   – Density (Functionality) consistent with historical trends through 2004
• …..but need ―breakthroughs‖ after 2005!
• We will continue to look for evidence of Industry Trend
  Acceleration/Deceleration in 2003



                                                  4 December 2002, ITRS 2002 Update
Backup




         4 December 2002, ITRS 2002 Update
Production
Definition
      4 December 2002, ITRS 2002 Update
                                                                              Technology Node vs
                                                                        Actual Wafer Production Capacity
                                        2002 ITRS Update – (No Changes from 2001 ITRS)
                                 10
Feature Size (Half Pitch) (mm)

                                                                                                                                                                   For 1995-1999
                                                                                                                            W.P.C.= Total Worldwide Wafer
                                                                      W.P.C.   W.P.C.   W.P.C.   W.P.C.   W.P.C.   W.P.C.       Production Capacity                   >0.7 mm
                                                                                                                                   (Relative Value)
                                                                                                                                                                      0.4-0.7 mm
                                         Feature Size of Technology



                                                                                                                            Sources:
                                                                                                                            1995 to 1999: SICAS                       <0.4mm
                                  1                                                                                         2000: Yano Research Institute& SIRIJ

                                                                                                                                                                     For 2000
                                                                                                                                                                       >0.8 mm

                                                                                                                                                                       0.5-0.8 mm

                                                                                                                                                                       0.35-0.5 mm
                                  0.1
                                                                                                                                                                       0.25- 0.35 mm

                                                                                                                                                                       0.2 - 0.25 mm

                                                                                                                                                                       0.18 - 0.2 mm

                                                                                                                                                                      <0.18 mm
                                 0.01
                                                  1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005
                                                                           Year
                                  Source: 2001 ITRS - Exec. Summary




                                                                                                                                       4 December 2002, ITRS 2002 Update
 Scaling –
Technology
  Nodes
       4 December 2002, ITRS 2002 Update
2002 ITRS Update – (No Changes from 2001 ITRS)
   Half Pitch (= Pitch/2) Definition



       Metal                                    Poly
       Pitch                                    Pitch




   (Typical                             (Typical
    DRAM)                              MPU/ASIC)
   Source: 2001 ITRS - Exec. Summary


                                       4 December 2002, ITRS 2002 Update
2002 ITRS Update – (No Changes from 2001 ITRS)

  Scaling Calculator +
                                                                                 1994 NTRS -




                                                               Log Half-Pitch
                                                                                   .7x/3yrs

                   Node Cycle Time:                                             Actual -
                                                                                .7x/2yrs
                             0.7          0.7                                       Linear Time
                              x            x
 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 ->
 16
                                    0.5x                 Node Cycle Time
                                                            (T yrs):
                       N            N+1         N+2          *CARR(T) =
                                                       [(0.5)^(1/2T yrs)] - 1
                         * CARR(T) = Compound
                         Annual Reduction Rate        CARR(3 yrs) = -10.9%
                        (@ cycle time period, T)
                                                      CARR(2 yrs) = -15.9%
      Source: 2001 ITRS - Exec. Summary



                                                      4 December 2002, ITRS 2002 Update
       2001 ITRS ORTC Node Tables – w/Node Cycles
     [Node = DRAM Half-Pitch (HP)]                                       [3-Year Node Cycle]
       Table 1a Product Generations and Chip Size Model Technology Nodes—Near-term Years
    YEAR OF PRODUCTION                                     2001     2002     2003        2004   2005      2006   2007
    DRAM ½ Pitch (nm)                                      130      115         100       90     80       70     65
    MPU/ASIC ½ Pitch (nm)                                  150      130         107       90     80       70     65
    MPU Printed Gate Length (nm) ††                            90   75          65        53     45       40     35
    MPU Physical Gate Length) (nm)                             65   53          45        37     32       28     25
    ASIC/Low Power Printed Gate Length (nm) ††             130      107         90        75     65       53     45
    ASIC/Low Power Physical Gate Length) (nm)                  90   75          65        53     45       37     32

         [MPU Gate Length Cycle                      [2-year cycle]             [3-year
                    (GL)]:
       Table 1b Product Generations and Chip Size Model Technology Nodes—Long-term years
                                                                                 cycle]
2002 ITRS YEAR OF PRODUCTION                                               2010          2013    2016

Update – DRAM ½ Pitch (nm)                                                 45            32       22

(No       MPU/ASIC ½ Pitch (nm)                                            45            32       22

Changes   MPU Printed Gate Length (nm) ††                                  25            18       13

from 2001 MPU Physical Gate Length) (nm)                                   18            13           9

ITRS)     ASIC/Low Power Printed Gate Length (nm) ††                       32            22       16
                   ASIC/Low Power Physical Gate Length) (nm)               22            16       11

                         [MPU HP/GL Cycle]:                                           [3-year cycle]

                                                                            4 December 2002, ITRS 2002 Update
     2001 ITRS ORTC MPU Frequency Tables – w/Node Cycles
                                           ips:
         Table 4c Performance and Package Ch Frequency On-Chip Wiring Levels— Near -Term Years
  YEAR OFPRODUCTION                                     2001     2002    2003           2004           2005         2006        2007
  DRAM ½ Pitch (nm)                                     130      115     100             90              80          70          65
  MPU/ASIC ½ Pitch (nm)                                 150      130     107             90              80          70          65
  MPU Printed Gate Length (nm)                          90       75      65              53              45          40          35
  MPUPhysical Gate Length (nm)                          65       53      45              37              32          28          25
  Chip Frequency (MHz)
  On-chip local clock                                   1,684    2,317   3,088          3,990         5,173         5,631       6,739
                   -chip) speed
  Chip-to-board (off                                    1,684    2,317   3,088          3,990         5,173         5,631       6,739
  (high-performance, for peripheral buses)[1]
  Maximum number wiring levels —maximum                   7       8       8               8              9           9           9
  Maximum number wiring levels —minimum                   7       7       8               8              8           9           9

      [MPU Gate Length Cycle                 [2-Yr GL Cycle;                  then 3-Yr]
       Table 4d Performance and Package Chips: Frequency, On               —Long
                                                          -Chip Wiring Levels   -term
2002 ITRS        (GL)]:                      Years
Update –              YEAR OFPRODUCTION
                      DRAM ½ Pitchnm) (
                                                                                2010
                                                                                 45
                                                                                                2013
                                                                                                 32
                                                                                                              2016
                                                                                                               22
(No                   MPU/ASIC ½ Pitch (nm)                                      45              32            22

Changes               MPU Printed Gate Length (nm)                               25
                                                                                 18
                                                                                                 18
                                                                                                 13
                                                                                                               13
                                                                                                                9
from 2001
                      MPU Physical Gate Length (nm)
                      Chip Frequency (MHz)
ITRS)
  Sources:
                      On-chip local clock                                     11,511            19,348        28,751
                                       -chip) speed
                      Chip-to-board (off                                      11,511            19,348        28,751
  2001 ITRS                                          buses)[1]
                      (high-performance, for peripheral
    ORTC              Maximum number wiring levels —maximum                      10              10            10
                      Maximum number wiring levels —minimum                      9               9             10           [3-year
                                                                                                                             cycle]

                                                                                       4 December 2002, ITRS 2002 Update
Chip Size
 Trends

      4 December 2002, ITRS 2002 Update
Chip Size Model Calculation Illustration - DRAM
(Cell Array Area / Chip Size)
x 100 = Cell Array Efficiency (%):    Cell Array Area = Cell Area x
                                                 number of bits (2 n)
Chip Size = (A x f 2 x Nbits)/CAE

                                               f2




                     Cell Area = Cell Area Factor (A) x f 2 ; f =
                     technology node (half-pitch) feature size;
                     Example: Cell Area = 2x4 x f 2 = 8 f 2

                                          4 December 2002, ITRS 2002 Update
2001 ITRS DRAM Model Trend Analysis
2002 ITRS Update – (No Changes from 2001 ITRS)


                                   3-yr
                                   Node
                                   Cycle vs
    0.89/yr                        2-yr
                     0.95/yr
  0.71/yr



                                                               [Cell Design
                                 0.74/yr                Improvement Factor]




                               4 December 2002, ITRS 2002 Update
                             DRAM Cell Area History / 2001 ITRS Model
                                  2002 ITRS Update – (No Changes from 2001 ITRS)
                                                                         DRAM Cell Area

                                                                 History <-- 2000 --> F'cast
                   10                                   Historical Actual <- > 2001 ITRS
  1 Mb
  (est.)                                                             0.35x / 3 Years                         Actual Scaling
CAF (A)
 = 31 =                                                                  –29%/yr                             Acceleration, Or
31/1.0^2
 29 (per                                                                                                     Equivalent Scaling
 FEP) 1                                                                                                      Innovation
                                  4 Mb      16 Mb
                                CAF (A)    CAF (A)
                                                           64 Mb
                                                                                                             Needed to maintain
                                 = 22 =
                                11/.71^2
                                            = 16 =        CAF (A)                                            historical trend
                                           4.0/.5^2        = 11 =
Cell Area (u2)




                                26 (per    21 (per
                                FEP)                    1.3/.35^2;
                                           FEP)
                                                         .71/.25^2
                   0.1
                                           16->10 (per FEP)
                                                                      128/256Mb
                                                                                      512Mb
                                                                   CAF (A) = 8.0 =
                            DRAM Cell Size                       .35/.21^2; .26/.18^2
                            Historical Trend:                    10 -> 8 (per FEP)         1Gb / 2Gb
                                                                                          CAF (A) = 6
                            Half-Pitch Scaling,
                  0.01      contributed
                            ~ .5x / 3 years [(.7x)^2]
                            Cell Design innovation                                                         4Gb / 8Gb
                                                                                                           CAF (A) = 6
                            contributed additional                                                                       16Gb / 32Gb
                            ~ .7x / 3 years                                                                              CAF (A) = 4

                 0.001
                     1986         1989        1992        1995         1998         2001         2004         2007       2010      2013          2016
                                                                                    Year                                                  64 Gb/128Gb
                                Sources: Sematech, 2001 ITRS ORTC                                                                          CAF (A) = 4


                                                                                                        4 December 2002, ITRS 2002 Update
ORTC Table TWG Line Item Ownership Chk's by L. Wilson/A.Allan

ORTC Table     ORTC Table Line Item(s)              TWG Owner                  TWG Table
- Table 1a-d   DRAM Model                           FEP                         [DRAM Model] -no change
- Table 1f-j   MPU Model                            Design                      [MPU Model] -no change
- Table 2a,b   Litho Field Size Table unchgd        Litho                   57a,b Table not changed
               Wafer Size line item unchgd          FEP, FI                 50a,b AA to review-done-no change
- Table 3a,b   # of Chip I/O’s Table unchgd         Test, Design            24a,b Table not changed
               # of Package Pins Table unchgd       Test, A&P               25a,b Table not changed
               # of Package Balls HP updtd-NOchg to#        A&P, Test       75a,b AA to confirm-done-no change
- Table 4a,b   Chip Pad Pitch Flip chip area array updtd A&P                77 AA to confirm -done/updated
               Cost-Per-Pin Low Cost updtd                  A&P             75a,b AA to confirm -done/updated
- Table4c,d    Chip Frequency                        Design, PIDs           [MPU Model] -no change
               Chip-to-Board Frequency               Design, A&P            [MPU Model] -no change
               Max # Wire Levels line item unchgd    Interconnect   62a,b AA to review- done/corrections
- Table 5a,b   Electrical Defects                Yield Enhance.      90, 91 only notes AA to review –done
                                                                    -no change
- Table 6a,b   P.Supply Volt. line item unchgd    PIDs              35a,b AA to review-done-no change
               Max. Power CP & HP updtd -NOchg to#A&P, Design, PIDs 75a,b AA to confirm -done-no change
- Table 7a,b   Affordable Cost                    Economic (AA actg) n/a -no change
               Test Cost Table unchgd                Test                   24a,b Table not changed



                                                                        4 December 2002, ITRS 2002 Update
   2002 Update vs 2001 ITRS
Example: ORTC Line Item Update:
    A&P Chip-to-Next-Level
   (ORTC Table 4a,b; A&P Table 77)




                        4 December 2002, ITRS 2002 Update
       Assembly and Packaging – 2002 Update vs. 2001
                               Table 77 Chip to Next Level Potential Solutions
                  Year of Production                  2001   2002   2003   2004   2005   2006   2007   2010   2013   2016
      DRAM ½ Pitch (nm)                               130    115    100    90     80     70     65     45     32      22
      MPU / ASIC ½ Pitch (nm)                         150    130    107    90     80     70     65     50     35      25
      MPU Printed Gate Length (nm)                    90     75     65     53     45     40     35     25     18      13
      MPU Physical Gate Length (nm)                   65     53     45     37     32     28     25     18     13      9
      Chip Interconnect Pitch (µm)
Was Wire bond—ball                                    45     35     30     25     20     20     20     20     20      20

 Is   Wire bond—ball                                  45     40     35     30     25      20    20     20     20      20

Was Wire bond—wedge                                   40     35     30     25     20     20     20     20     20      20

 Is   Wire bond—wedge                                 50     50     40     40     35     35     30      20    20      20

Was TAB*.                                             40     40     40     40     30     30     30     30     30      30
      TAB* Japan TWG has the lead for
 Is                                                   45     40     35     35      30    30     25     20     20      15
      Tab technologies
      Flip chip (area array for cost-performance
Was and high-performance)                             160    160    150    150    130    130    120    90     80      70

 Is   Flip chip area array                            200    180    150    150    100    100    80     70     70      50
      Peripheral flip chip for hand-held, low-cost,
Was and harsh                                         150    130    120    110    100    90     80     60     45      30

 Is   Peripheral flip chip                            80     80     60     60     40     40     30     20     20      15



                                                                                  4 December 2002, ITRS 2002 Update
                                                     2002 ITRS Update versus 2001 ITRS -
                                             Assembly and Packaging Flip-Chip Peripheral Pad Pitch
                                                                      (A&P Table 77; ORTC Table 4a,b)
                 160

                                                                                                           Chip-to-Next- Level
                 140
                                                                                                             Potential Solution:
                 120                                                                                        Conductive Adhesive
                                                                 2001 ITRS - "WAS"                      Peripheral Pad Attachment
Pad Pitch (um)




                 100
                              Flip-Chip Pad
                 80


                 60


                 40

                                2002 Update - "IS"
                 20


                  0
                       2001   2002    2003    2004     2005     2006     2007                   2010                2013                           2016
           Sources: 2001 ITRS (12/2001); 2001 ITRS Update (11/2002)                 Year
                              Peripheral flip chip for hand-held, lo-cost, harsh - WAS (2001)                   Peripheral flip chip - IS (2002)




                                                                                                        4 December 2002, ITRS 2002 Update
                                                         2002 ITRS Update versus 2001 ITRS -
                                                Assembly and Packaging Flip-Chip Peripheral Pad Pitch
                                                                       (A&P Table 77; ORTC Table 4a,b)
                 160

                                                                                                                 Chip-to-Next- Level
                 140
                                                                                                                   Potential Solution:
                 120                                                                                             Conductive Adhesive
                                                                    2001 ITRS - "WAS"                       Peripheral Pad Attachment
Pad Pitch (um)




                 100
                                   Flip-Chip Pad
                 80


                 60
                          Wire Bond (Ball)
                 40


                 20

                               2002 Update - "IS"
                  0
                        2001    2002     2003     2004    2005     2006     2007                 2010                        2013        2016
           Sources: 2001 ITRS (12/2001); 2001 ITRS Update (11/2002)                      Year
                       Peripheral flip chip for hand-held, lo-cost, harsh - WAS (2001)          Peripheral flip chip - IS (2002)
                       Wire bond—ball - WAS (2001)                                              Wire bond—ball - IS (2002)




                                                                                                           4 December 2002, ITRS 2002 Update

								
To top