Richland College Digital Fundamentals Engineering Technology CETT 1425 Rev 0 – B Donham

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Richland College Digital Fundamentals Engineering Technology CETT 1425 Rev 0 – B Donham Powered By Docstoc
					                 Richland College                        Digital Fundamentals
             Engineering Technology                              CETT 1425
                  Rev. 0 – B. Donham
              Rev. 1 (7/2003)– J. Horne                          Lab 5
             Rev. 2 (1/2008) – J. Bradbury
                                                          Latches & Flip-Flops

Name: ___________________________________________ Date: ____________________


Objectives
To construct and investigate the operation of a NAND and NOR latch
To investigate the operation of a J-K Flip-Flop
To investigate the operation of a D Flip-Flop

Suggested Reading
Chapter 5, Digital Systems, Principals and Applications; Tocci

Equipment and Components

7400 IC – Quadruple 2-Input Positive-NAND Gates
7402 IC – Quadruple 2-Input Positive-NOR Gates
7474 IC – Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear
74LS112 IC – Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear
2 toggle switches

Breadboard & wires
VOM
0-10 Volt power supply
Logic probe

Circuit Simulator (MultiSIM or an equivalent)




                                                                                 Page 1 of 8
Introduction
The outputs of a sequential logic circuit are dependent upon the current and past input states,
which requires a memory element. Examples of basic memory devices are Latches and
Flip-Flops.

NOR Latch
The NOR latch has 2 active-high inputs, SET and CLEAR, that determine the state of the output
(Q). This is an asynchronous device. The symbol and truth table for the NOR latch are shown
below.

         S      C          Q
         0      0      No Change                                              S      Q
         0      1     CLEAR, Q=0
         1      0      SET, Q=1                                               C      Q
         1      1       Invalid


NAND Latch
The NAND latch has 2 active-low inputs, SET and CLEAR, that determine the state of the
output (Q). This is an asynchronous device. The symbol and truth table for the NAND latch are
shown below.

         S      C          Q
         0      0       Invalid                                               S      Q
         0      1      SET, Q=1
         1      0     CLEAR, Q=0                                              C      Q
         1      1      No Change


J-K Flip-Flop
The operation of the J-K flip-flop is similar to the S-C latches described above, except that it
does not have an invalid state. The invalid state is replaced with a TOGGLE state, which causes
the output (Q) to change logic levels. The state of the flip-flop is determined by the value of the
J and K inputs when the specified clock edge is detected. This flip-flop may also have
asynchronous PRESET and CLEAR inputs. The asynchronous inputs can be used to change the
state of the flip-flop regardless of the state of the synchronous inputs. The inputs can either be
active-low or active-high depending upon the device type.

D Flip-Flop
The logic level of the input (D) will be transferred to the output (Q) when the specified clock
edge is detected. This device may also have asynchronous PRESET and CLEAR inputs. The
asynchronous inputs can be used to change the state of the flip-flop regardless of the state of the
synchronous inputs. The inputs can either be active-low or active-high depending upon the
device type.




                                                                                         Page 2 of 8
Procedure:

1.   Draw the schematic for a NOR latch in the space below. Using a data sheet for a 7402 IC,
     write pin numbers on the schematic that will be used when constructing the circuit.




2.   Using the schematic in procedure 1, construct the NOR latch circuit on a breadboard. Use
     a toggle switch for the inputs (S, C). Apply VCC and Ground to the proper pins on the IC.
     Place the S & C inputs to a logic ‘0’ initially.

3.   Turn on the power supply. Using a logic probe or VOM, measure and record the logic state
     of the outputs.

               Q = __________

               Q = __________

4.   If ‘Q’ is a logic ‘1’, toggle the ‘C’ input to a logic ‘1’ and then back to a ‘0’. If ‘Q’ is a
     logic ‘0’ then go to procedure 5.

5.   Set the ‘S’ input to a logic ‘1’. Using a logic probe or VOM, measure and record the state
     of the outputs.

               Q = __________

               Q = __________

     What state is the flip-flop in? ___________________

6.   Return the ‘S’ input back to a logic ‘0’. What effect did this have on the outputs? Explain
     your answer _____________________________________________________________


7.   Set the ‘C’ input to a logic ‘1’. Using a logic probe or VOM, measure and record the state
     of the outputs.




                                                                                            Page 3 of 8
                Q = __________

                Q = __________

      What state is the flip-flop in? ___________________

8.    Turn off the power supply and disconnect the circuit.




9.    Draw the schematic for a NAND latch in the space below. Using the data sheet for a 7400
      IC, write pin numbers on the schematic that will be used when constructing the circuit.




10.   Using the schematic in procedure 9, construct the NAND latch circuit on a breadboard. Use
      a toggle switch for each input (S, C). Apply VCC and Ground to the proper pins on the IC.
      Place the S & C inputs to a logic ‘1’ initially.


11.   Turn on the power supply. Using a logic probe or VOM, measure and record the logic state
      of the outputs.

                Q = __________

                Q = __________

12.   If ‘Q’ is a logic ‘1’, toggle the ‘C’ input to a logic ‘0’ and then back to a ‘1’. If ‘Q’ is a
      logic ‘0’ then go to procedure 13.


                                                                                             Page 4 of 8
13.   Set the ‘S’ input to a logic ‘0’. Using a logic probe or VOM, measure and record the state
      of the outputs.

               Q = __________

                Q = __________

      What state is the flip-flop in? ___________________

14.   Return the ‘S’ input back to a logic ‘1’. Set the ‘C’ input to a logic ‘0’. Using a logic
      probe or VOM, measure and record the state of the outputs.

               Q = __________

                Q = __________

      What state is the flip-flop in? ___________________

15.   Turn off the power supply and disconnect the circuit.

16.   Refer to the data sheet for a 74LS112, edge triggered J-K flip-flop.

      What clock edge triggers the flip-flop? _______________

      What logic level must be applied to the asynchronous inputs to SET or CLEAR the flip-
      flop? _______________

      What is the pin number for VCC? _____________

      What is the pin number for Ground? ______________

      How many J-K flip-flops are in this device? _____________

17.   Use MultiSIM or an equivalent circuit simulator to evaluate a J-K flip-flop. Select a
      74LS112 flip-flop with active-low asynchronous inputs from the digital menu. Connect
      toggle switches to the J, K, CLOCK, and asynchronous inputs. Set the switches for the
      following initial conditions:

               J=0
               K=0
               CLOCK = 1
               Asynchronous SET or PRESET = 1
               Asynchronous CLEAR = 1

      Note: For information about a component, highlight a device and select HELP under
      the help menu.


                                                                                         Page 5 of 8
18.   Measure and record the value of ‘Q’ for the following input states.

        SET      CLR       J       K        CLK            Q
         1        0        X       X         X
         0        1        X       X         X
         1        1        0       0         ↓
         1        1        0       1         ↓
         1        1        1       0         ↓
         1        1        1       1         ↓

19.   Set the asynchronous CLEAR input to ‘0’. Toggle the CLOCK input from ‘1’ to ‘0’ and
      back to ‘1’. Did ‘Q’ change states on the clock edge? Explain why or why not.


      _______________________________________________________________________

20.   Refer to the data sheet for a 7474, edge-triggered D flip-flop. Construct the following
      circuit in MultiSIM or an equivalent circuit simulator. Select the actual 7474 IC from the
      digital menu rather than a D flip-flop symbol.

                                           VCC




                                       D         Q


                                                 Q



                                             CLEAR

      Connect VCC and Ground to the appropriate pins on the IC. Connect a toggle switch to the
      asynchronous CLEAR line and set the switch to a logic ‘1’. Connect VCC to the
      asynchronous PRESET or SET line. Connect the Function Generator to the CLOCK input.
      To get a 0 – 5 V square wave, select a 50% duty cycle, 1 kHz square wave with an
      amplitude of 2.5V and an offset of 2.5V. (Connect the + output to the clock input and the
      common input to ground. The – output should not be connected). Monitor the CLOCK
      input and the ‘Q’ output using a Logic Analyzer.

      Print out a copy of your schematic and attach it to the lab.




                                                                                     Page 6 of 8
21.   Turn the simulator on and then turn off the simulator after a number of clock signals has
      occurred. Sketch a output waveform as shown on the logic analyzer.



       CLK



           Q




22.   Measure and record the frequency of the ‘Q’ waveform.

               Frequency = _______________

23.   What is the function of this simple D flip-flop circuit? _____________________________

24.   Turn the simulator back on. Toggle the asynchronous CLEAR input to a ‘0’. What
      happens to the output? ________________________________________________

25.   Turn off the simulator.




                                                                                       Page 7 of 8
Review Questions:    Answer the following questions after the lab is completed.

1.   A D flip-flop can be implemented from a J-K flip-flop and an inverter. Connect the J – K
     inputs to either the D or D signal to cause circuit to behave like a D flip-flop.


                                                     J         Q

       D
                                                     K         Q




2.   Based upon the results in procedure 21, sketch the waveforms for the following circuit.




           CLK




           Q1


           Q2




                                                                                     Page 8 of 8

				
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